12th NASA Symposium on VLSI Design, Coeur d’Alene, Idaho, USA, Oct. 4-5, 2005
CMOS Current Mode Logic Gates for High-Speed
Applications
Lisha Li, Sripriya Raghavendran, and Donald T. Comer
Department of Electrical and Computer Engineering
Brigham Young University, Provo, UT 84606
Email: ll229@et.byu.edu
Abstract— This paper presents results of a design that uses
CMOS current mode logic that can be used to implement the high
precision, speed critical elements of the mixed-signal systems. The
design is based upon the 0.25-µm CMOS TSMC process. The
propagation delays of the new current mode logic are compared
to those of equivalent gates implemented in conventional CMOS
logic. The results show a propagation delay improvement of more
than 200% using the current mode logic. The application of the
proposed current mode building blocks is illustrated in a typical
mixed-signal circuit, the phase detector for a high-speed phase
locked loop with good speed improvement over conventional
CMOS logic.
II. MCML C IRCUIT
The operation of CML logic circuits is based on the steering
of constant current similar to the “differential pair” used in
analog circuits. Fig. 1 shows the structure of a Conventional
NOR gate and a MCML NOR/OR gate. Device scalings are
typically selected as small as possible with the constraint that
sufficient swing and noise margins are produced by the circuit.
A
I. I NTRODUCTION
B
Conventional pull-up PMOS, pull-down NMOS static logic
is popular because of its convenient availability in standard
library cells, small area usage, low power dissipation, and high
noise margins [1]. Even though the static power consumption
of the conventional CMOS logic gate is zero ideally, it
dynamically generates a large current pulse flowing from the
power supply to the ground during the state transition. The
coupling of the high switching spike noise may cause cross
talk between the analog and the digital circuitry. Even worse,
the switching noise might induce latch up which can possibly
destroy devices with the integrated circuit due to overheating
[2], [3].
Current mode logic (CML) is a popular logic style for highspeed circuits. This type of logic was first implemented using
bipolar transistors [4] and extended for application with MOS
transistors. MOS current mode logic (MCML) circuits with
constant bias currents are intended for accurate high-speed
mixed signal application [3], [5], [6], [7], [8]. Compared to
conventional CMOS logic, MCML dissipates constant static
power and requires techniques more analogous to analog
design. However, MCML requires smaller dynamic power
than that of the conventional logic because of the smaller
output swings. The reduced output swing and faster switching
makes MCML a promising candidate for certain mixed-signal
applications [9], [10], [11], [12]. The constant supply currents,
lower cross talk between the analog and the digital circuits
of MCML improves the accuracy of mixed-mode systems.
Additional efficiency can be obtained using more than one
level of logic.
Norout
MN1
MN2
B
A
(a)
Orout
Norout
M1
A
M4
M3
M2
B
Vref
M5
(b)
Fig. 1. Basic logic gates: (a) Conventional NOR gate. (b) MCML NOR/OR
logic gate.
III. S IMULATION R ESULTS AND T EST M ETHODOLOGY
Three identical gates are cascaded in Fig. 2 to test the
MCML technique and the conventional logic respectively. The
12th NASA Symposium on VLSI Design, Coeur d’Alene, Idaho, USA, Oct. 4-5, 2005
middle gate with fanin and fanout both equal to one is used
for propagation delay measurements. Although the proposed
Vin A
Norout
Norout
A
Low B Gate1 Orout
Low B Gate2
Fig. 2.
Orout
Norout Out
A
Low B Gate3 Orout
Test bench of logic gates
design has not yet been fabricated, the results based upon
simulations using the BSIM3 model [13] are verified using
two simulation engines: Spectre Spice (CADENCE) and ADS
(Agilent). Because the CADENCE tool has been widely used
and good experimental correlation for gate delays have been
achieved, the confidence level in the simulation results is high.
The results are tabulated in Table I.
TABLE I
L OGIC GATES PROPAGATION DELAY COMPARISON
Tpd
Conventional NOR
MCML NOR
MCML OR
CADENCE
140.86ps
56.121ps
55.4871ps
ADS
140.05ps
64.3ps
63.5ps
IV. A PPLICATION E XAMPLE
The phase detector is a key element in a phase locked loop
system. The use of the MCML gates may be used in the
implementation of a phase detector for use in a charge pump
based phase locked loop such as shown in Fig. 3 [5], [9].
An early arriving data pulse activates the Pup that increases
the frequency of the VCO input Fvco while a late arriving
data pulse activates the Pdn that decrease the frequency of
Fvco . Fig. 4 shows a gate level implementation of the phase
detector circuit of Fig. 3, where the basic building block is the
conventional NOR gate shown in Fig. 1(a) or the MCML NOR
gate shown in Fig. 1(b). As presented in Fig. 4, three cascaded
NOR gates are employed for AND function with appropriate
delay to reset the S/R latch.
High
D
Q
V. S IMULATION C OMPARISON
The performance of a PLL system is ultimately determined
by the ability of the phase detector to respond to incoming
data with a short delay time [9]. To compare the behavior
of the phase detector built on the MCML and CMOS NOR
gates, the respective results are tabulated in Table II and
do
Table III. The error term ² is defined as ² = tdit−t
. tdi is
di
the input delay, representing the time delay between the two
inputs |Fref − Fvco |. tdo is the resolution width, representing
the difference between the pulse widths of the outputs Pup
and Pdn measured at the midpoint of the input swing. The
CMOS logic implementation provides a phase resolution of 1.2
degrees, while the MCML provides 0.25 degrees of resolution,
both measured at 400 MHz with the error tolerance about 10%.
With a propagation delay improvement of about 200% using
the current mode nor gate over the CMOS nor gate, the corresponding MCML phase detector gains the resolution degree
improvement of 480% over the CMOS phase detector. Besides
the slower propation delay compared to that of MCML, the
conventional logic doesn’t have the dynamic symmetry in
NOR/AND gate because of one connection is dynamically
faster than the other connection due to the unsymmetric circuit
configuration shown in Fig. 1(a). As shown in Table II, the
resolution widths of the conventional logic phase detector
in the situation when Fref is ahead or behind of Fvco are
unbalanced. On the other hand, the MCML phase detector has
the dynamic symmetry because of the balanced architecture of
the basic NOR cell as shown in Fig. 1(b).
TABLE II
C ONVENTIONAL LOGIC PHASE DETECTOR RESOLUTION
Input Delay (ps)
(Fref is earlier than Fvco)
Resolution Width (ps)
² (%)
(Fref is later than Fvco)
Resolution Width (ps)
² (%)
R
R
Q
25
10
98.815
1.19
47.256
5.49
21.713
13.15
6.078
39.2
106.93
-6.93
55.87
-11.74
29.53
-18.12
13.87
-38.7
Q
R
D
50
Pup
Fref
High
100
Fref
S
Fvco
S
Pup
Q
Pdn
Q
Fvco
Q
R
Fig. 3.
Charge pump phase detector for PLL
Fig. 4.
Gate level schematic of phase detector
Pdn
12th NASA Symposium on VLSI Design, Coeur d’Alene, Idaho, USA, Oct. 4-5, 2005
TABLE III
MCML
[13] W. Liu, MOSFET models for SPICE simulation including BSIM3v3 and
BSIM4. New York: Wiley, 2001.
LOGIC PHASE DETECTOR RESOLUTION
Input Delay (ps)
(Fref is earlier than Fvco)
Resolution Width (ps)
² (%)
(Fref is later than Fvco)
Resolution Width (ps)
² (%)
100
50
25
10
104.7
-4.7
53.186
-6.37
26.434
-5.74
10.916
-9.16
104.4
-4.4
52.76
-5.52
26.2
-4.8
10.6
-6.0
VI. C ONCLUSION
The benefit of a faster logic propagation delays in speed
critical paths of mixed signal applications such as the phase detector of a high-speed PLL is invaluable. The advantage for the
MCML phase detector is larger than just the propagation delay
advantage due to symmetry considerations. Even though additional static power is required for the MCML (approximately
1.2 mW per gate), this can produce a substantial improvement
in performance as demonstrated in the PLL phase detector
application. The proposed gates may be easily integrated with
conventional CMOS logic with minimal interface problems.
ACKNOWLEDGMENT
The authors would like to thank Seth Nielsen for his help
on the PSPICE simulators.
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