LOW-DROPOUT LINEAR REGULATORS WITH Q
REDUCTION
Man-Chuen Choi）
Prof. Shu-Chuan Huang
Thesis for Master of Science
Department of Electrical Engineering
Tatung University
7
July 2011
10
IC
R&D
IC
i
(LDO)
PSRR
PCB
PMOS
TSMC 0.35um CMOS
View Draw Hspice Laker
EDA
150mA
190.6mV
1058µm x 947µm (
ii
I/O PADs)
ABSTRACT
The popularization and rapid growth of portable electronic products results in that
more and more attention has been paid to the high performance and low cost power
manage projects. As a competitive kind of power management, the new generation of low
dropout linear regulator (LDO) with ultra low noise, high PSRR, micro-power loss and
the lowest cost will be holding an important position.
This thesis focuses on the design of a low dropout linear regulator (LDO) IC with
improved stability. Not only lead to the reduction of the required PCB space and
component cost, but also make the power management more efficient and reasonable. In
order to improve efficiency, the PMOS transistor is adopted to achieve the low dropout
voltage. The bypass circuit is designed to reduce the output voltage noise and improve
power supply rejection, which make the chip adapt to audio devices. Furthermore, its fast
start-up circuit is designed to reduce the start-up time. The circuit is added to ensure the
stability in whole load range, improve the transient response and greatly reduce the cost
of the application.
Based on the principle of LDO and TSMC 0.35um CMOS process, the whole chip
and its sub-blocks have been designed and simulated using the EDA software, such as
View Draw, Hspice and Laker. The results of simulation indicate that the dropout voltage
is just 190.6mV at the condition of output current 150mA, and all of other characteristics
meet the specification. The layout area is 1058µm x 947µm without I/O PADs.
iii
TABLE OF CONTENTS
ACKNOWLEDGEMENT............................................................................................i
CHINESE ABSTRACT...............................................................................................ii
ENGLISH ABSTRACT......................................................................................... …iii
TABLE OF CONTENTS ...........................................................................................iv
LIST OF FIGURES ................................................................................................. viii
LIST OF TABLES...................................................................................................... xi
CHAPTER 1 INTRODUCTION ................................................................................1
1.1 DEFINITION ...................................................................................................…….1
1.2 MOTIVATION ..........................................................................................................4
1.3 SPECIFICATIONS……………………………………………………………......... 4
1.4 LDO MARKET SEGMENT………………………………………………………..... 5
1.5 THESIS ORGANIZATION…………………………………………………………...7
CHAPTER 2 FUNDAMENTALS OF LOW DROPOUT LINEAR REGULATOR 8
2.1 INTRODUCTION OF LOW DROPOUT LINEAR REGULATOR ....................................... 8
2.2 SPECIFICATIONS AND DEFINITIONS OF LDO ..........................................................10
2.2.1 LINE REGULATION .......................................................................................10
2.2.2 LOAD REGULATION .....................................................................................11
2.2.3 DROPOUT VOLTAGE .....................................................................................12
2.2.4 QUIESCENT CURRENT ..................................................................................13
2.2.5 EFFICIENCY .................................................................................................14
2.2.6 TRANSIENT RESPONSE.................................................................................15
iv
2.2.7 FREQUENCY RESPONSE ...............................................................................17
2.2.8 EQUIVALENT SERIES RESISTANCE (ESR) ......................................................20
2.2.9 ACCURACY OF LDO OUTPUT VOLTAGE........................................................21
2.2.10 POWER SUPPLY REJECTION RATIO .............................................................22
2.2.11 OUTPUT NOISE ...........................................................................................23
2.2.12 POWER DISSIPATION ..................................................................................23
2.2.13 SERIES PASS DEVICE ..................................................................................24
2.3 DESIGN CONSIDERATIONS OF LDO ......................................................................26
CHAPTER 3 BUILDING BLOCKS OF REGULATOR TOPOLOGIES............27
3.1 BANDGAP REFERENCES ......................................................................................27
3.1.1 TEMPERATURE-INDEPENDENT REFERENCES ...............................................28
3.1.2 NEGATIVE-TC VOLTAGE ...............................................................................29
3.1.3 POSITIVE-TC VOLTAGE ................................................................................29
3.1.4 ZERO TEMPERATURE COEFFICIENTS AND CURVATURE CORRECTION .........33
3.1.5 CONVENTIONAL BANDGAP REFERENCE CIRCUITS......................................33
3.2 ERROR AMPLIFIER...............................................................................................34
3.2.1 DESIGN OF ERROR AMPLIFIERS ...................................................................34
3.2.2 ONE-STAGE OPERATIONAL AMPLIFIERS ......................................................35
3.2.3 TWO-STAGE OPERATIONAL AMPLIFIERS......................................................36
3.3 PASS DEVICES .....................................................................................................37
3.3.1 PASS DEVICES DESIGN ISSUE.............................................................................. 37
3.3.2 STABILITY ............................................................................................................ 39
3.3.3 FREQUENCY COMPENSATION ............................................................................ 42
3.3.4 POLE SPLITTING................................................................................................... 43
3.3.5 EQUIVALENT SERIES RESISTANCE (ESR) COMPENSATION .............................. 43
v
3.3.6 USE CHARGE PUMP BOOSTER............................................................................. 45
3.3.7 PROTECTION CIRCUIT ........................................................................................ 46
3.3.7.1 OVERLOAD CURRENT PROTECTION .......................................................... 46
3.3.7.2 REVERSE BATTERY PROTECTION ............................................................... 47
3.3.7.3 ELETROSTATIC-DISCHARGE PROTECTION ................................................... 48
3.3.7.4 THERMAL SHUTDOWN PROTECTION ............................................................ 50
CHAPTER 4 PROPOSED LDO DESIGN ..............................................................51
4.1 DESIGN LDO BLOCK LEVEL .................................................................................51
4.2 DESIGN CHALLENGE ...........................................................................................51
4.3 BANDGAP REFERENCE CIRCUIT DESIGN .............................................................52
4.4 BIAS, ERROR AMPLIFIER & PASS DEVICE CIRCUIT DESIGN ..................................53
4.5 OVERALL LDO STRUCTURE .................................................................................54
CHAPTER 5 LDO SIMULATION RESULTS........................................................58
5.1 BANDGAP REFERENCE ........................................................................................58
5.2 LDO .....................................................................................................................59
5.2.1 OPEN-LOOP GAIN .........................................................................................59
5.2.2 START-UP TIME.............................................................................................61
5.2.3 LINE REGULATION .......................................................................................62
5.2.4 LOAD TRANSIENT RESPONSE.......................................................................65
5.2.5 LINE TRANSIENT RESPONSE ........................................................................67
5.2.6 DROPOUT VOLTAGE .....................................................................................68
5.2.7 QUIESCENT CURRENT ..................................................................................69
5.3 PERFORMANCE SUMMARY OF THE PROPOSED LDO ............................................70
5.4 PROTOTYPE AND FLOOR PLAN ...........................................................................72
vi
CHAPTER 6 CONCLUSIONS.................................................................................74
6.1 CONCLUSIONS .....................................................................................................74
6.2 FUTURE WORK .....................................................................................................74
REFERENCES...........................................................................................................75
vii
LIST OF FIGURES
Figure 1-1 Simple series voltage regulator block diagram (a) and (b) ..........................2
Figure 1-2 Linear regulators and their corresponding subclasses..................................3
Figure 1-3 Portable electronics products .......................................................................5
Figure 1-4 Simplified power distribution of SOC .........................................................5
Figure 1-5 LDO market segment ...................................................................................7
Figure 2-1 Functional blocks of a typical LDO voltage regulator.................................9
Figure 2-2 Traditional PMOS-type low dropout regulator ..........................................10
Figure 2-3 Typical characteristic of VOUT vs VDD.........................................................13
Figure 2-4 Quiescent current of the LDO itself ...........................................................14
Figure 2-5 Typical LDO transient response to a load-current step ..............................15
Figure 2-6 Traditional block diagram of PMOS-type LDO ........................................16
Figure 2-7 Equivalent model for AC analysis..............................................................18
Figure 2-8 Frequency response of LDO under two different loading current levels...20
Figure 2-9 (a) stable with a proper ESR, (b) unstable due to a large ESR, and (c) unstable
due to a small ESR ....................................................................................21
Figure 2-10 Power supply rejection of a LDO.............................................................22
Figure 2-11 Output noise voltage of LDO ...................................................................23
Figure 2-12 Pass devices of LDO ................................................................................24
Figure 3-1 Generation of PTAT voltage.......................................................................30
Figure 3-2 Family of zero temperature coefficients and the summing diagram ........ 31
Figure 3-3 Curvature correction (a) Curvature in temperature dependence of and a
bandgap voltage, (b) Variation of the zero tc for difference samples, (c)
Temperature behavior of first order bandgap Vbe + VPTAT, and (d)
viii
Temperature behavior of first order bandgap Vbe+VPTAT+VPTAT2 ...........32
Figure 3-4 Conventional bandgap reference circuit.....................................................33
Figure 3-5 Generation of a PTAT current ....................................................................34
Figure 3-6(a) One-stage cmos op amp with n-channel input pair and (b) One-stage cmos
op amp with p-channel input pair .............................................................35
Figure 3-7(a) Two-stage cmos op amp with n-channel input pair and (b) Two-stage cmos
op amp with p-channel input pair .............................................................36
Figure 3-8 Pass elements of LDO linear regulator ......................................................38
Figure 3-9 Open-loop gain and phase ..........................................................................40
Figure 3-10 Resulting closed-loop gain responses of a negative-feedback circuit as phase
margin (PM) decreases to its unstable state of 0o .....................................41
Figure 3-11 Stable bode-plot response of a negative feedback circuit ........................42
Figure 3-12 Equivalent series resistance (ESR) of Resr................................................44
Figure 3-13 Stability of LDO using dominant-pole compensation..............................45
Figure 3-14 Charge pump booster of Cgdpass ................................................................45
Figure 3-15 Current limiting circuit protection ...........................................................46
Figure 3-16 Reverse battery protection........................................................................47
Figure 3-17 Common electrostatic-discharge (ESD) protection circuits.....................49
Figure 3-18 Thermal shutdown protection circuit .......................................................50
Figure 4-1 Loop gain of pole-splitting-based LDO at different output currents .........51
Figure 4-2 Proposed bandgap reference circuit ...........................................................52
Figure 4-3 Proposed bias, error amplifier, pass device and feedback network............54
Figure 4-4 LDO structure (open loop) .........................................................................54
Figure 4-5 Schematic of the proposed LDO ................................................................57
Figure 5-1 VREF vs Temperature ..................................................................................58
ix
Figure 5-2 VREF vs VDD ................................................................................................59
Figure 5-3 Gain and phase without Q reduction circuit .............................................59
Figure 5-4 Gain and phase with Q reduction circuit....................................................60
Figure 5-5 Gain and phase without Q reduction circuit...............................................60
Figure 5-6 Gain and phase with Q reduction circuit....................................................61
Figure 5-7 Start-up time...............................................................................................61
Figure 5-8 VOUT vs VDD (corner: TT) ..........................................................................62
Figure 5-9 VOUT vs VDD (corner: SS)...........................................................................62
Figure 5-10 VOUT vs VDD (corner: SF).........................................................................63
Figure 5-11 VOUT vs VDD (corner: FS).........................................................................63
Figure 5-12 VOUT vs VDD (corner: FF).........................................................................64
Figure 5-13 Load Transient Response without Q reduction ........................................65
Figure 5-14 Load Transient Response with Q reduction .............................................65
Figure 5-15 Load Transient Response with heavy load...............................................66
Figure 5-16 (Post-sim) Load Transient Response with heavy load .............................66
Figure 5-17 Line Transient Response ..........................................................................67
Figure 5-18 (Post-sim) Line Transient Response.........................................................67
Figure 5-19 Dropout Voltage .......................................................................................68
Figure 5-20 (Post-sim) Dropout Voltage......................................................................68
Figure 5-21 Quiescent Current.....................................................................................69
Figure 5-22 (Post-sim) Quiescent Current ...................................................................69
Figure 5-23 The floor plan of the layout......................................................................72
Figure 5-24 Whole chip layout ....................................................................................72
Figure 5-25 A test setup used to measure the LDO chip .............................................73
x
LIST OF TABLES
Table 1.1 The comparison of power supply technologies..............................................6
Table 2.1 Comparison of different pass devices of LDO.............................................25
Table 5.1 VOUT of five corners from TT to FF under pre-layout simulation.............. 64
Table 5.2 Performance summary of the proposed LDO ..............................................70
Table 5.3 Comparison of result ....................................................................................71
xi
CHAPTER 1
INTRODUCTION
1.1 Definition
The fundamental classes of voltage regulators are linear regulators and switching
regulators. There are two basic types of linear regulator. One is the series regulator and
the other is the shunt regulator. A simple representation of a series type of linear
regulators is shown in the block diagram in Fig.1-1(a). Linear regulators modulate the
conductance of a series pass switch connected between an input dc supply VDD and the
regulated output VOUT to ensure the output voltage is a predetermined ratio of its bias
reference voltage. The term “series” refers to the pass element that is in series with the
unregulated supply and the load. Since the current flow and its control are continuous in
time, the circuit is linear and analog in nature, and because it can only supply power
through a linearly controlled series switch, its output voltage cannot exceed its
unregulated input supply (i.e: VOUT < VDD ). The basic components are shown in the block
diagram in Fig.1-1(b).
Notice that the control element is in series with the load between
input and output. The output sample circuit senses a change in the output voltage. The
error detector compares the sample voltage with a reference voltage and causes the
control element to compensate in order to maintain a constant output voltage [1]. A series
or low dropout linear regulator (LDO) is a circuit that supplies a good specified and stable
DC voltage [2]. In summary, linear regulators can be high or low power, externally or
internally compensated, and high or low dropout, as depicted in Fig.1-2 [3].
1
VDD
Series
Regulator
VOUT
VSS
(a)
Control
Element
VDD
Voltage
Reference
Error
Detector
VOUT
Sample
Circuit
VSS
(b)
Figure 1-1 Simple series voltage regulator block diagram [1]
2
Linear Regulators
High power
Low power
( ILOAD >1A )
( ILOAD <1A )
Externally
Internally
Compensated
Compensated
( Pole Dominant @VOUT )
(Pole Dominant@inside)
Off-chip cap
On-chip cap
Off-chip cap
High dropout (HDO)
On-chip cap
Low dropout (LDO)
( VDROPOUT > 0.6V )
( VDROPOUT < 0.6V )
Figure 1-2 Linear regulators and their corresponding subclasses [1]
3
1.2 Motivation
The demand for low dropout regulators has been driven by the portable electronics
market as well as industrial and automotive applications. Most recently, the increasing
demand for portable and battery operated products have forced these circuits to operate
under lower voltage conditions. Furthermore, high current efficiency has also become
necessary to maximize the lifetime of the battery. Battery life is determined by the total
current drain composed of quiescent current and load current. The objective of the
research is then identified and defined according to the demands that drive regulator
design into the future [1].
1.3 Specifications
The important aspects of the LDO can be summarized into three categories, namely,
(1) dc- and ac- regulating performance, (2) power characteristics and (3) operating
requirements. Some of the specifications that serve as metrics for the LDO include
dropout voltage, line regulation, load regulation, power-supply rejection, tolerance over
temperature, output voltage variation resulting from transient load-current steps, output
capacitors and ESR range, quiescent current flow, maximum load-current, sleep-mode
current, power efficiency and input/output voltage range. The requirements of these
performance characteristics often contradict each other giving rise to necessary
compromises. The priority of the performance parameters is defined according to the
particular application [3].
4
1.4 LDO Market Segment
Why do we need the Power Management IC (PMIC)?
The PMIC will be used in
the next-generation handsets, from voice-centric telephones to message and
multimedia-based “smart” phones. The PMIC is also used in the computer and portable
electronics products as shown in Fig.1-3.
Figure 1-3 Portable electronics products
Fig.1-4 shows the simplified power distribution of SOC. Therefore, the features of the
PMIC should provide (1) regulation of voltage, (2) lower current in power distribution
bus, (3) flexibility and (4) selective shutdown.
Batteries
V-Reg 1
Analog block 1
V-Reg 2
Analog block 2
V-Reg 3
Analog block 3
V-Reg 4
RF block
V-Reg 5
Digital block 1
V-Reg 6
Digital block 2
Figure 1-4 Simplified power distribution of SOC [4]
5
LDO is suitable choice for local on-chip voltage regulation in SOC due to its
low-noise. Table 1.1 illustrates the comparison of power supply technologies.
Table 1.1 The comparison of power supply technologies
Switching
Switching
LDO
SC
PWM
PWM/PFM
Poor
Efficiency at heavy
Good if
Best
(good only if
load
Vo=Mi Vbat
Vo=Vbar)
Light-load
Lowest
Highest
Power consumption
Switching noise
None
Footprint area
Smaller
Conversion ratio
Step-down only
Highest
Largest
Step-down, step-up, inverting
Analog baseband
Typical application
uP/DSP
& RF
6
Display Lighting
5,000
Load Current (mA)
Adaptor
Based
3,000
Network/Communication
1,000
LCD
600
Transportable
300
Portable
150
TV
Automotive
Mobile
1
15
30
Output voltage (V)
1.2 ~ 4.5
Provided by Yobon Co.,Ltd.
Figure 1-5 LDO market segment
Based on the LDO market segment as shown in Fig.1-6, in this thesis we will focus
on the mobile and portable devices. The input voltage is 3.3V with the load current
around 150mA and the output voltage of 2.8V.
1.5 Thesis Organization
The organization of this thesis is as follows. Chapter 2 introduces the structure of
the LDO regulator, including fundamental operations and key function of traditional LDO
regulators. Chapter 3 demonstrates the recent researches about the regulator topologies
and the system of the LDO design. In order to improve the stability, the Q reduction
circuit of the proposed LDO regulator with a current capability of 150mA is implemented
and the sub-circuit design of the LDO such as start-up, bandgap and bias circuit will be
discussed in chapter 4. Chapter 5 shows the layout of the LDO and describes the
simulating result. Chapter 6 will draw the conclusion and future works.
7
CHAPTER 2
FUNDAMENTALS OF LOW DROPOUT LINEAR
REGULATORS
In this chapter, we introduce the fundamental operational concepts of LDOs such as
line regulation, load regulation, drop-out voltage, quiescent current, power efficiency and
so on. Furthermore, several types of pass element of LDOs will also be discussed, for
example: PMOS-type LDO voltage regulators, NMOS-type LDO voltage regulators and
others.
Proper design of LDO involves intricate knowledge of the system and its load. The
tasks of maximizing load regulation, maintaining stability, and minimizing transient
output voltage variations prove to be challenging and often conflicting. The IC designer
could choose the type of the low dropout linear regulator to be used according to the
requirements. Finally, we discuss design issues that we face during the implementation of
the whole low dropout linear regulator.
2.1 Introduction of low dropout linear regulator
Fig.2-1 illustrates the functional block diagram of a typical low dropout linear
regulator (LDO). It consists of four main sections, (A) a reference voltage, (B) an error
amplifier, (C) a series pass element and (D) a feedback network. The reference voltage
aims at generating a stable, accurate and temperature-tolerant reference voltage. Then the
error amplifier detects the difference between the feedback voltage and the reference
voltage (VREF) [5].
8
VDD
Start-up
Reference
Voltage
VREF
－
Error
Amp
Pass
Element
+
Current
Sensing
Protection
VOUT
RF1
Resr
Feedback
Network
RF2
Cout
VSS
Figure 2-1 Functional blocks of a typical LDO voltage regulator
The voltage from an accurate reference voltage is connected to one input of the error
amplifier. Another input of the error amplifier is connected to the feedback network. The
error amplifier amplifies the voltage difference of the reference voltage and feedback
voltage, and applies an appropriate drive to the output pass element. If the feedback
voltage is smaller than the reference voltage, the drive voltage is adjusted by the error
amplifier and allows more current to pass to the output load. As a result, the output
voltage is regulated at a value that is decided by how the feedback signal is generated and
the level of the reference voltage [5].
The output voltage is:
RF1 + RF2
( 2.1 )
RF2
are the resistors of the feedback network and VREF is the reference
VOUT ≈ VREF x
where RF1 and RF2
voltage. Sometimes an external feedback point is provided by the LDO and its output
voltage can be configured to some voltage level at users’ will.
9
2.2 Specifications and Definitions of the LDO
In this section, some terms and definitions are reviewed and the fundamental
concepts are described that it will be easier to design or to verify a low dropout linear
regulator (LDO). These terms includes the categories of a low dropout linear regulator
(LDO), line regulation, load regulation, drop-out voltage, quiescent/ground current,
efficiency, transient response, frequency response, equivalent series resistance (ESR) of
the output capacitor, accuracy of LDO output voltage, power supply rejection ratio,
output noise, power dissipation and series pass device [5].
2.2.1 Line Regulation
Line regulation means the resistance of LDO against the variation of supply voltage
which is stated in Eq. (2.2) and illustrated in Fig.2-2.
Line Regulation =
∆VOUT
∆VDD
( 2.2 )
VDD
VREF
VFB
－
Error
Amp
+
IOUT
VOUT
RF1
RL
RF2
VSS
Figure 2-2 Traditional PMOS-type low dropout regulator
The low-frequency line regulation can be analyzed as follows:
10
RL
∆VOUT =
x ∆VDD－∆VFB x Av x ga x RL
RL + Rds
where Rds is the effective resistance of series PMOS pass transistor, RF1 and RF2 are
the feedback resistors, RL is the load resistor, IOUT is the loading current, ga is the
transconductance of the series PMOS-type pass transistor and Av is the voltage gain of the
error amplifier. Here, we assume RL << (RF1+ RF2). Rewrite the equation, and we can get
[1+
RF2
RL
x Av x ga x RL] x ∆VOUT =
∆VOUT
∆VDD
x ∆VDD
RL + Rds
RF1 + RF2
RF1 + RF2
≈
RF2
1
x
Av x ga x ( RL+ Rds )
Referring Eq. (2.2), we can increase Av and ga to improve the line regulation [6].
2.2.2 Load Regulation
Load regulation means the resistance of low dropout linear regulator (LDO) against
the variation of transient loading current which is stated in Eq. (2.3) and illustrated in
Fig.2-2.
Load Regulation =
∆VOUT
( 2.3 )
∆IOUT
The load regulation can be analyzed as follows:
∆VOUT = ∆IOUT x (RF1 + RF2) ⁄⁄ RL
∆IOUT =
∆VOUT
∆IOUT
RF2
∆VFB x Av x ga = Av x ga x (
) ∆VOUT
RF1 + RF2
1
≈
Avga
x
RF1 + RF2
RF2
The load regulation is a steady-state parameter, so all the frequency components can be
cancelled. Referring to Eq. (2.3), the load regulation could be improved by increasing the
11
loop gain of low dropout linear regulator (LDO) which is composed of the gain of error
amplifier (Av) and the trans-conductance of series PMOS pass transistor (ga). When
designing, we strike to obtain a smaller undershoot or overshoot with shorter response
time [5].
2.2.3 Dropout voltage
The definition of drop-out voltage is the “minimum voltage difference” between
input and output voltages of LDO at which the output voltage is still regulated. Fig.2-3
shows a typical relationship between VDD and VOUT. It can be seen that when VDD is too
small, the output voltage is no longer regulated to a fixed value. In this low-VDD operating
region, it is usually called as “dropout mode”. The drop-out voltage is mainly related to
the architecture of the error amplifier and the output pass transistor. Take an output pass
transistor of a PMOS-type as an example; the pass transistor’s I-V characteristic is
determined by the feature size of this PMOS transistor and the lowest output voltage of
the error amplifier which gives the largest VGS to the PMOS transistor. As a result, once
the feature size of the PMOS transistor and the architecture of the error amplifier are
determined, the drop-out voltage is also determined and can be found with the PMOS I-V
characteristic and load line [5].
Since the power consumption is proportional to the product of the voltage
difference and conducting current, a lower dropout voltage can make a LDO dissipate less
power in itself. According to Fig.2-3, this LDO operates at 3.5V power supply. Its dropout
voltage is typically 200mV when the loading current is 100mA [5]. Then the power
consumption in the output pass transistor is 200mV x 100mA = 20mW.
12
VOUT
Dropout
Region
3.3
0
Off
Regulation
Region
Region
2.0
3.5
10
VDD
Figure 2-3 Typical characteristic of VOUT vs VDD [6]
Drop-out voltage is also a function of the output current because in dropout mode,
the output transistor operates in the triode region and acts like a resistor. On the contrary,
the output voltage is no longer regulated and it is in the off region when the input voltage
is less than 2.5V. When the input voltage value is between 2.5V and 3.5V, the LDO is in
the drop-out region. In this region, the series pass transistor behaves as a resistor and the
drop-out voltage is expressed in terms of its on-resistance (Ron), given in Eq. (2.4) [5].
Dropout Voltage = VDD－VOUT = IOUT Ron
( 2.4 )
where the Ron is the on-resistance of series pass transistor.
2.2.4 Quiescent Current
Quiescent current is also called as ground current. It is the difference between the
input current and the output current. The quiescent current has the relationship in Eq. (2.5)
as shown in Fig.2-4
Quiescent current =IQ = IDD －IOUT
( 2.5 )
Quiescent current is dependent on the types of pass transistors (BJTs or MOSFETs).
When a MOS transistor is used a pass transistor, the quiescent current is almost constant
13
since MOS transistors are voltage-driven devices. On the contrary, the quiescent current
of BJT transistors increases proportionally with the load current because BJT transistors
are current-driven devices [5].
IDD
IN
+
OUT
LDO
Regulator
VDD
GND
－
IOUT
+
Cout
Resr
VOUT
－
IQ
VSS
Figure 2-4 Quiescent current of the LDO itself
2.2.5 Efficiency
The efficiency of a LDO is defined as the ratio of the output power and the input
power and is calculated as follows:
IOUT VOUT
x 100%
( 2.6 )
η=
(IOUT +IQ) VOUT
referring to the above equation, the quiescent current must be minimized to improve
efficiency. When IQ is negligible, Eq. (2.6) can be rewritten as follows:
IOUT VOUT
VOUT
x 100%
x 100% =
η=
( 2.7 )
V
+(V
－
V
)
OUT
DD
OUT
IOUT VDD
It can be seen in Eq. (2.7) that the difference voltage between input and output voltage is
an intrinsic factor in the efficiency of a LDO regardless of its load current. As a result, in
addition to a small quiescent current, a small difference between input and output voltage
(or drop-out voltage) is required to achieve high efficiency. When the ICs driven by the
LDO are in stand-by mode, i.e., they draw little or no current, but their supply voltage
14
must remain active, so that these ICs can be activated immediately. In this case, Eq. (2.6)
should not be used to evaluate efficiency because Io=0. Instead, IQ is the most important
item. It determines how long the battery can last when the system is in stand-by mode [5].
2.2.6 Transient response
Transient response presents the specification of the maximum allowable output
voltage variation at a full range transient loading current step. Fig.2-5 illustrates the
transient response of a typical LDO, and Fig.2-6 shows a typical block diagram of a
VOUT
ILoad, max
∆V3
T1
T4
∆V4
∆V2
∆V1
ILoad, min
T2
T3
0
Time [us]
Figure 2-5 Typical LDO transient response to a load-current step [6]
PMOS-type LDO. The worst-case time required for the loop to respond T1 is specified by
the maximum permissible output voltage variation ∆V1 which is affected by the output
capacitor Cout, the equivalent series resistor (ESR) of the output capacitor, the bypass
capacitors Cb, the maximum load-current (ILoad,
(ILoad, min).
∆V1=
IOUT x T1
Cout+ Cb
max)
and the minimum load-current
+ Vesr , where Vesr α IOUT
where ∆Vesr is the output voltage variation due to the presence of equivalent series resistor
Resr of the output capacitor Cout. And ∆Vesr is proportional to the equivalent series resistor
15
Resr. The relationship is stated in Eq. (2.8) and Eq. (2.9).
ILoad, max x T1
∆V1 ≈
( 2.8 )
+ ∆Vesr
Cout+Cb
VDD
VREF
VFB
－
Error
Amp
+
VOUT
RF1
Cout
Resr Cb
RF2
VSS
Figure 2-6 Traditional block diagram of PMOS-type LDO
T1 ≈
Cout+Cb
ILoad, max
(∆V1
∆Vesr)
( 2.9 )
The output voltage recovers and settles to its final value after going through the
transient stage. ∆V2 is as shown in Eq. (2.10).
( 2.10 )
∆V2 ≈ Ro-reg ILoad, max
where Ro-reg is the closed-loop output resistance of the regulator. This corresponds to the
effect of load regulation performance on the output. The settling time T1 is the time
required for the pass device to fully charge the loading capacitor and is dependent on the
phase margin of the open-loop frequency response. A settling time of T2 is required before
a steady state is reached. The voltage difference, ∆V2 , between zero-load and heavy-load
is essentially the effect of load regulation. The length of T2 is dependent on the time
required for the pass element to charge the output capacitor and the phase margin of the
close loop response in the LDO.
16
When the load is removed suddenly from the LDO, a time T3 elapses until the LDO
shuts off the pass element completely. The feedback network does not response
immediately to turn off the series pass device. Hence, the output loading current still
charges the output capacitor through the series pass device. Finally, the LDO generates an
overshoot output variation. The overshoot output voltage variation (∆V3) is stated in
Eq.(2.11).
∆V3 ≈
ILoad, max x T3
Cout+Cb
+ ∆Vesr
( 2.11 )
After the loading transition, the response will recover back to its nominal state
after the time interval T4. The time interval T4 is a function of the feedback resistors, the
output capacitor and the bypass capacitor. It can be written as Eq. (2.12).
(Cout+Cb) RF1
Cout+Cb
∆V4
∆V
=
( 2.12 )
T4 ≈
4
Ipull-down
VREF
The feedback network resistors are designed to be larger value to suppress the
leakage current while a larger output capacitor is designed to improve the frequency
response. These two design efforts will maintain the whole stability of the LDO and
reduce the amount of overshoot and undershoot at the output voltage of the LDO. But the
corresponding response time may increase a little bit. Hence, it is a trade-off problem and
should be taken into the consideration before the analog IC designers start designing the
LDO [6].
2.2.7 Frequency response
In order to analyze the frequency response of a LDO, its closed feedback loop is broken
and the LDO can be modeled as shown in Fig.2-7. In this model, only one dominant pole
in the error amplifier is assumed. The loop gain is calculated as the gain from VREF to VFB
and is described as follows:
17
VDD
VREF
－
Error
Amp
+
gmp
RDS
Cpar
VOUT
Roa
Resr
RF1
RL
A
VFB
Cb
Cout
RF2
VSS
Figure 2-7 Equivalent model for AC analysis
gma Roa gmp Zo
VFB
RF2
L(s)= －
x
=
VREF
1+sRoa Cpar
RF1+ RF2
( 2.13 )
where gma and gmp are the trans-conductance of the error amplifier and the output pass
element, respectively. Cpar and Roa are the equivalent resistance and capacitance seen at
the internal node of the error amplifier, that is, Zo is the equivalent impedance at the
output node, and can be described as Eq. (2.14):
1+sResr Cout
Zo= RDS ⁄⁄ (RF1 + RF2) ⁄⁄
sCout
⁄⁄
1
sCb
( 2.14 )
where RDS is the output resistance of the output pass device and Cb is an estimated
capacitance placed at the input of the electronic system that is powered by the LDO. In
case, the value of bypass capacitor is much smaller than Cout. Due to its small value, ESR
of this bypass capacitor is almost negligible.
It can be shown that from Eq. (2.13) and Eq. (2.14) the transfer function of the
LDO’s loop gain consists of three poles and one zero. The first pole is due to the output
capacitor and the LDO’s output resistance.
1
1
≈
2π RDS Cout
2π (RDS + Resr) Cout
where RDS is the output resistance of the series pass device.
fp1 =
18
( 2.16 )
The second pole is derived from the internal pole of the error amplifier and it is usually
located at the output node of error amplifier. It is described as:
1
fp2≈
( 2.17 )
2π RoaCpar
The third pole is due to the bypass capacitor and the ESR of output capacitor.
1
1
fp3 =
≈
( 2.18 )
2π ResrCb
2π (RDS ⁄⁄ Resr) Cb
There is one zero in the overall transfer function and it is:
1
fz1 =
2π Resr Cout
( 2.19 )
The location of the poles and zero depend on the topologies and the architectures of
the error amplifier used by the LDO and types and values of the output capacitors. In
some LDOs, for example, fp1 is the smallest dominant pole and fp1 < fp2 < fp3. By using
the frequency compensating technique, we could push the location of the zero to be near
to the second-dominant pole fp2 to achieve pole-zero cancellation. And the third pole fp3
should be placed behind the unity-gain frequency to ensure the system is stable.
|A(s)|dB
Loading current Increases
-20dB/decade
-20dB/decade
-40dB/decade
fp1
fp1’ fz1
fp2
fp3
Frequency(Hz)
Figure 2-8 Frequency response of LDO under two different loading current levels [5]
Now, we will discuss the dominant pole fp1 which acts as an important role in the
frequency response. We observe in Eq. (2.16) that the location of the dominant pole fp1 is
changed with the loading current. since RDS is inversely proportional to the loading
19
current. The location of the dominant pole fp1 stays at low frequency when the loading
current is low. On the contrary, the location of the dominant pole fp1 moves toward high
frequency when the loading current increases. But when the loading current is high, the
other two poles still stay at the original location and may have the conflict with the high
frequency location of the dominant pole fp1. This will decrease the phase margin and
make the LDO unstable.
Fig.2-8 illustrates a typical frequency response of LDO with the increasing loading
current. fp1 in Fig.2-8 is shifted to fp1’ (higher frequency) when the loading current
increases [5].
2.2.8 Equivalent series resistance (ESR)
As described in frequency response, the ESR of an output capacitor is sometimes
used to stabilize a LDO. However, the magnitude of ESR affects the pole-zero relation
and also the stability of a LDO. Fig.2-9 illustrates the effects of different ESR. It shows
that some LDOs, a limited range of ESR and capacitance of output capacitors must be
used to ensure stability. For industrial practice, normally IC companies for LDO products
will provide a datasheet with a figure to illustrate the stability and safety range of the
output capacitor’s equivalent series resistor. The AC response in Fig.2-9(a) is stable, but
those in Fig.2-9(b) and (c) are not stable. It is noted that a larger ESR results in a larger
voltage variation during load transient. Otherwise, a larger capacitor with a smaller ESR
is usually more costly [5].
20
Gain(dB)
Gain(dB)
P1
Gain(dB)
P1
P1
P2
Zesr
0
Zesr
fp3
fp1
P2
P2
fp2 fz
(a)
P3
Freq.(Hz)
P3
0
fp1
0
fp2 fz
fp3
fp1
fp2
Freq.(Hz)
fz fp3
Freq.(Hz)
P3
Zesr
(c)
(b)
Figure 2-9 (a) stable with a proper ESR, (b) unstable due to a large ESR, and
(c) unstable due to a small ESR
2.2.9 Accuracy of LDO output voltage
The overall accuracy of the LDO is deeply affected by many error sources
including line regulation, load regulation, drift of the reference voltage, drift of the error
amplifier, tolerance of feedback resistors and temperature coefficients of feedback
resistors. The accuracy is stated in Eq.(2.20).
Accuracy ≈
|∆VLR|+|∆VLDR|+√∆V o,ref 2 + ∆V o,o 2 + ∆V o,r 2 + ∆V TC 2
Vo
x 100% ( 2.20 )
where ∆VLR, ∆VLDR, ∆Vo,ref, ∆Vo,a, ∆Vo,r, ∆VTC are output voltage variations caused by
finite line regulation, finite load regulation, drift of reference voltage, output voltage drift
of error amplifier, feedback resistors tolerance, and temperature coefficient, respectively.
The output voltage variation in a regulated power supply is primarily because of the
temperature variation of the reference voltage source, difference amplifier as well as the
sampling resistor. Load regulation, line regulation, gain error, and offsets normally
account for 1 to 3% of the overall accuracy [6].
21
2.2.10 Power Supply Rejection Ratio
The power supply rejection is the ability of a LDO to prevent the regulated output
voltage from the variation of AC signal input voltage, which is stated in Eq.(2.21) and
illustrated in Fig.2-10
PSRR1 = A1 ⁄ Add1
( 2.21 )
where A1 and Add1 are the open-loop differential gain and power gain of amplifier
respectively. The value of power supply rejection ratio is often related to the frequency
response of closed-loop feedback system of the LDO. PSRR with absolute value above
50dB should be achieved at the low frequency. When the frequency increases above
1KHz, the PSRR will start to drop down [6].
+
VDD
IN
Co
VDD
Vi ripple
VOUT
+
OUT
Load
GND
－
Resr
VOUT
－
time
Vo ripple
time
Figure 2-10 Power supply rejection of a LDO
2.2.11 Output Noise
Output noise voltage is the RMS value of the output noise voltage over a range of
frequencies between 10Hz to 100KHz, as illustrated in Fig.2-11. When the input voltage
is ripple-free and the load current has no variation, measure the noise source of the output
voltage which is generated from the LDO itself. The value of the output noise voltage is
typically between 50uV and 500uV. The major output noise is produced from the internal
22
voltage reference. There are several methods to reduce the output noise voltage. One is
that adding an external bypass capacitor (Cb) to the output of the reference voltage
generator. The other is using some signal processing techniques such as auto-zeroing,
chopping techniques and auto-calibration [6].
VDD
Constant input
+
IN
+
OUT
VOUT
Co
VDD
Load
VOUT
Vo noise peak
GND
Resr
－
－
time
time
Figure 2-11 Output noise voltage of LDO
2.2.12 Power Dissipation
The permissible power dissipation for any package is a measure of the capability of
the device to pass heat from the power source, the junctions of the IC, the ultimate heat
sink, and the ambient environment. Thus the power dissipation is dependent on the
ambient temperature and the thermal resistance across the various interface between the
die and ambient air as stated in Eq. (2.22).
where TJMAX
( TJ MAX －TA)
( 2.22 )
θJA
is the maximum allowable junction temperature. TA is the temperature of
PD =
ambient, θJA is the thermal resistance junction-to-ambient for the package. The actual
power dissipation across the device can be represented by the following Eq.(2.23):
PD = ( VDD －VOUT) x IOUT
( 2.23 )
This establishes the relationship between the power dissipation allowed due to thermal
consideration, the voltage drop across the device, and the continuous current capability of
23
the device. These two equations should be used to determine the optimum operating
conditions for the device in the application [7].
2.2.13 Series Pass Device
There are many choices of the series pass device to be applied in LDO such as
Bipolar, BiCMOS, and CMOS transistors. As different types of series pass devices are
used in LDO design, its performance will be different. Select the series pass device which
are based on the application’s specifications. Each series pass device has its own
characteristics, advantages and disadvantages. The LDO usually use the series pass
devices such as NPN-Darlington, NPN, PNP, NMOS and PMOS transistors. Fig.2-12
shows these five types of series pass devices topologies.
In
+
Vsat
－
+
2Vbe
－
Out
NPN Darlington
In
+
Vsat
－
+
Vbe－
－
Out
NPN
In
In
+
+
Vsat
－
Vec-sat
－
Out
PNP
+
Vgs
－
Out
NMOS
In
+
Vsd-sat
－
Out
PMOS
Figure 2-12 Pass Devices of LDO [3]
Bipolar-based series pass devices are the current-driven devices, so they could deliver a
huge output current for the loading circuit. For this situation, they also have larger
quiescent current and decrease power efficiency. On the contrary, the MOS-based series
pass devices belong to voltage-driven devices. The driving current of the MOS-based
series pass devices depend on the gate voltage and its value is not larger than
Bipolar-based devices. Hence, the quiescent current of the MOS-based devices are quite
small and making LDO have higher power efficiency.
Table 2.1 shows the comparison of several characteristics of different types of
24
series pass devices.
Table 2.1 Comparison of different pass devices of LDO
Parameter
Darlington
NPN
PNP
NMOS
PMOS
Io-max
High
High
High
Medium
Medium
Iquiescent
Medium
Medium
Large
Low
Low
Vdrop-out
Vsat + 2Vbe
Vsat + Vbe
Vec-sat
Vsat + Vgs
Vsd-sat
Speed
Fast
Fast
Slow
Medium
Medium
The pass device used on the LDO design will affect two characteristics which are
quiescent current and drop-out voltage. In this thesis, the LDO with PMOS-type series
pass devices which have the advantage of low drop-out voltage, is used. The value is
smaller than NMOS-type without additional charge pump circuit. The drop-out voltage of
the PMOS-type depends on the on-resistance of the PMOS-type series pass device. The
other features are low quiescent current with medium speed and output current. If the
NMOS-type series pass device is used for the LDO, the voltage between the gate and
source terminals may be floated. Since the output of the LDO locates at the source
terminal, it changes with the loading transition. The varying voltage at the source terminal
affects the equilibrium of the LDO. On the contrary, the voltage cross the gate and source
terminals of the PMOS-type series pass device is constant due to the source terminal
located in the stable power supply [3].
2.3
Design Considerations of LDO
The main items of the LDO can be classified into three categories, (A) regulating
performance, (B) quiescent current, and (C) operating voltages [14]. Other specifications
for the LDO include line regulation, load regulation, drop-out voltage, the tolerance of
25
temperature, output voltage variation from transient load-current steps, output capacitor
and ESR range, noise, input and output voltage range and maximum load-current. The
specifications of these performance characteristics often contradict each others.
26
CHAPTER 3
BUILDING BLOCKS OF REGULATOR
TOPOLOGIES
In this chapter, we will introduce the building blocks of a basic LDO. The design
criterion for each implementation is determined by the specific application as well as by
the process technology where the circuit is to be fabricated. However, they all have to
function under similar loading conditions, namely, a load-current, an output capacitor and
its associated electrical series resistance (ESR), and some bypass capacitors. Several of
the prevailing design approaches are scrutinized in this chapter. Each structure is
evaluated for its current efficiency and overall performance at low voltage. Moreover,
some performance enhancing techniques are also illustrated and evaluated.
3.1 Bandgap References
The main issue involved in the design of the reference is accuracy and low voltage
operation. Bandgap references are the most appropriate for low voltage. They are accurate
circuits with typical output voltages of roughly 1.25V. The respective input voltage
limitation is roughly 1.4 – 1.5V (a Vsat above the reference). Power supply rejection ratio
is another important factor, especially in mixed-signal designs where noise is coupled
from high speed digital circuits [8]. As a result, the noise floor must be kept low to
maximum the dynamic range. This translates to the design of low noise circuits. Typically,
1/f noise tends to be important in prevailing regulator designs. The difficulty is to
design a precise output voltage while keeping quiescent current at a minimum. The
27
accuracy of references is determined by line regulation and temperature drift performance.
Load regulation is sometimes included in the accuracy but is more appropriately specified
for voltage regulators. Accuracy performance is sometimes limited by the effects of the
package on the output voltage. The causes of this phenomenon are the physical stresses
included on the die by the package. As a result, the physical location of the reference with
respect to the overall chip is important. Package induced drifts can be significant
especially if trimming is performed at the wafer level. The performance can be improved
if trimming is done at the post-package level. Lower dynamic range, a consequence of
low voltage operation, demands that reference voltages be more accurate; as a result,
bandgap references require curvature correcting schemes. Lower dynamic range results
from reductions in power supply voltage, which decreases signal-to-noise ratio in an
environment where the noise floor typically keeps constant [9].
3.1.1 Temperature-Independent References
Two quantities having opposite temperature coefficients (TCs) are added with
proper weighing, and the result shows a zero TC. From Eq. (3.1), for two voltages V1 and
V2 that vary in opposite directions with temperature, we choose
1
and
2 such
that the
temperature coefficients of V1 and V2 are cancelled, obtaining a reference voltage, VREF
=
1V1
+
2V2 , with
zero TC.
∂ V1
∂ V2
( 3.1 )
VREF = 1V1 + 2V2
+ 2
=0
∂T
∂T
Now we must identify two voltages that have positive and negative TCs. Among
1
various device parameters in semiconductor technologies, the characteristics of bipolar
transistors have proven the most reproducible and well-defined quantities that can provide
positive and negative TCs. Although many parameters of MOS devices have been
considered for the task of reference generation, bipolar operation still forms the core of
28
the bandgap circuits [9].
3.1.2 Negative-TC Voltage
The base-emitter voltage of a bipolar transistor or the forward of a pn-junction
diode exhibits a negative TC. For a bipolar device, we have the following equations:
VBE =VT ln(IC /IS)
( 3.2 )
IS α µkTni2
( 3.3 )
where VT = kT/q
where µ denotes the mobility of minority
µ α µoT m
( 3.4 )
where m ≈ -3/2
ni2α T 3exp
Eg / (kT)
( 3.5 )
where ni is the intrinsic minority carrier concentration of silicon and Eg ≈ 1.12eV.
Assume Ic is held constant.
VT ∂ IS
∂ VBE
∂ VT
ln(IC /IS)
=
∂T
IS ∂ T
∂T
Eg
Eg Eg
∂ IS
3+m
exp
+ bT 4+m( exp
)
= b(4+m) T
)(
kT
kT kT 2
∂T
( 3.6 )
VT
Eg
VT ∂ IS
= (4+m)
+
2 VT
IS ∂ T
T
kT
Eg
VT
∂ VBE
VT
ln (IC /IS) (4+m)
VT
=
T
kT 2
∂T
T
VBE (4+m)VT Eg/q
=
( 3.7 )
T
where b is a proportional factor.
In room temperature, with VBE ≈ 750mV and T=300oK, the temperature coefficient
of the base-emitter voltage at a given temperature T is nearly -1.5mV/K [9].
3.1.3 Positive-TC Voltage
Assume that two bipolar transistors operate at unequal current densities, then the
29
difference between the base-emitter voltages is directly proportional to the absolute
temperature. From Fig.3-1, if two identical transistors (IS1 = IS2) are biased at collector
currents of nIo and Io and their base currents are negligible, then we have Eq. (3.8) and
Eq.(3.9) [3].
VDD
nIo= IC1
Io= IC2
－
+
∆VBE
Q2
Q1
VSS
Figure 3-1 Generation of PTAT voltage
∆VBE = VBE1
= VT ln
VBE2
nIo
VT ln
IS1
= VT ln n
where n =
IC1
x
Io
IS2
( 3.8 )
IS2
IC2 IS1
The VBE difference exhibits a positive TC as below
∂ ∆VBE k
=
lnn
∂T
q
( 3.9 )
3.1.4 Zero temperature coefficients and Curvature Correction
A very interesting point with regard to diode voltage VBE is the voltage difference
between two diode-connected BJT biased at different current densities Jc.. From Eq. (3.10),
the voltage difference is:
VBE = Vg0
Vg0
VBE0
T + VT [ ln
T0
∆VBE = VBE 2
VBE 1= VT ln
JC2
JC1
30
=
JC
JC0
kT
J
ln C2
q
JC1
ηln
T
T0
( 3.10 )
It is possible to use the thermal voltage VT, which has a positive temperature
coefficient, to balance the negative temperature coefficient of the diode voltage VBE, as
shown in Fig.3-2 [10].
VBE
VREF
(dVREF/ dT)=0
V
To= 100o
1.28
CTAT
T
T
dVBE/ dT=-2.2mV/K
1.25
To= 0o
VREF
sum
VT
1.23
K
To= -100o
PTAT
-80
0
120
Temp
T
VThermal Gain
ITAT
VREF = VBE+KVT
dVT/ dT=0.085mV/K
Figure 3-2 Family of zero temperature coefficients and the summing diagram [10]
If VBE and ∆VBE are summed together with the correct ratio K, the output voltage
Vref is:
VREF = VBE + K∆VBE
( 3.11 )
The temperature dependency of VREF is:
∂ VREF ∂ VBE
∂ K∆VBE VBE0 Vg0
k
VT0 JC2
(η x) +K”
=
+
=
ln
=0
q
∂T
∂T
∂T
T0
T0
JC1
Vg0 VBE0+(η x) VT0
1
( 3.12 )
K”=
VT0
JC2
ln
JC1
where the value of x is the order of temperature dependency of the bias current.
Letting K is:
K = K” ln
K VT0 = Vg0
JC2
JC1
( 3.13 )
VBE0+(η
x) VT0
Then we have
VREF| T=T0 = Vg0 + (η
x) VT0
( 3.14 )
According to the previous definition of the value of η = 4 - n ≈ 3.5. At a normal
temperature of 27 oC, VREF = 1.205 + 0.026 ( 3.5-1) = 1.27V. Eq. (3.10) is fundamental
31
equation for the design of reference circuits. The voltage difference between the VBE
values of two transistors operating at different current densities has a positive linear
temperature coefficient. Those two characteristics can be combined to give a near zero
temperature coefficient voltage. Eq. (3.10) also describes that the temperature dependence
of a bandgap reference circuit can be zero at a certain temperature To. However, the
reference voltage is not always a constant Vg0 for the whole temperature range.
There are many curvature correction techniques that have been devised to suppress
the variation of VREF in the bipolar bandgap circuits but they are seldom used in CMOS
counterparts. Due to large offsets and process variations, samples of a bandgap reference
display substantially different zero-TC temperature, making it difficult to correct the
curvature shown in Fig.3-3
VREF
VREF
T
T
To
(a)
(b)
VREF
VPTAT
VREF VBE
VPTAT
VBE
VPTAT
Vref= VBE+ VPTAT+ VPTAT
Vref= VBE+ VPTAT
2
2
T
T
(d)
(c)
Figure 3-3 Curvature correction [12]: (a) Curvature in temperature dependence of a
bandgap voltage, (b) Variation of the zero TC for different samples, (c) Temperature
behavior of first order bandgap Vbe+VPTAT, and (d) Temperature behavior of first order
bandgap Vbe+VPTAT+VPTAT2
32
3.1.5 Conventional Bandgap Reference Circuits
Fig.3.4 illustrates the conventional reference circuit [1].
R2
R1
－
Y
A1
VOUT
+
X
R3
nA
A
Q1
Q2
VSS
Figure 3-4 Conventional bandgap reference circuit [9]
Here, amplifier A1 senses VX and VY, driving the top terminals of R1 and R2 (R1=R2)
such that X and Y settle to approximately equal voltages. The reference voltage is
obtained at the output of the amplifier. From Fig.3-4, we have VEB1 – VEB2 = VT ln n,
arriving at a current equal to VT ln n / R3 through the right branch and hence an output
voltage of Eq. (3.15) as below:
VOUT =VBE2 +
VT lnn
R3
(R3+ R2)
=VBE2 + (VT lnn) 1+
R2
)
R3
( 3.15 )
The reference circuit can also be simplified as Fig.3-5(a). Assuming that M1-M2 and
M3-M4 are identical pairs, for ID1 = ID2, the circuit must ensure that VX = VY. Hence, ID1 =
ID2 = (VT ln n)/R1, yielding the same behavior for ID5. In practice, due to mismatches
between the transistors and temperature coefficient of R1 the variation of ID5 deviates
from the ideal equation [9].
33
VDD
VDD
M4
M3
ID2
ID1
M1
ID5
ID1
M2
X
R1
M1
VREF
Y
R1
Q1
nA
ID5
M2
X
Q2
A
M5
ID2
PTAT
Current
Y
Q1
M4
M3
M5
Q2
R2
VPTAT
Q3
nA
A
Vss
Vss
(a)
(b)
Figure 3-5 Generation of a PTAT current [9]: (a) PTAT current using a simple amplifier,
and (b) Generation of a temperature-independent voltage
From Fig.3-5(b), the ideal is to add a PTAT voltage (VPTAT) ID5 R2 to a base-emitter
voltage. The output therefore equals Eq. (3.16) as below:
( 3.16 )
VREF =VBE3 + (R2 /R1) VT ln
3.2 Error Amplifier
3.2.1 Design of Error Amplifiers
Error amplifier is a very important component in LDO design. Before the actual
design of an error amplifier can begin, one must set out of the requirements that will be
used to guide the design. The following list describes many of the items that must be
considered [11].
1. DC Gain
5. Slew Rate
9. Noise
2. Unit Gain Frequency
6. Input Swing
10. Layout Area
3. Phase Margin
7. Output Swing
4. Settling Time
8. Offset
34
3.2.2 One-Stage Operational Amplifiers
From Fig.3-6(a) and Fig.3-6(b), we can select one stage operational amplifier for
high speed design. This structure is only one pole. Therefore, it is no stability issue in the
circuit. The dominant pole is near to the output side and non-dominant pole is near to the
gate of M3. Hence, the gain-bandwidth is approximately gm / 2πCL, where gm is the
transconductance of M1 and M2. The slew rate is ISS / CL. . It has good input and output
swings. However, DC gain = gm (ro2//ro4) is not enough in LDO [12].
VDD
M4
M3
VOUT
M1
VIN
M2
CL
ISS
M5
Vbias
VSS
(a)
VDD
M5
Vbias
M1
VIN
ISS
M2
VOUT
M3
M4
CL
VSS
(b)
Figure 3-6: (a) One-stage CMOS op amp with N-channel input pair and
(b) One-stage CMOS op amp with P-channel input pair
35
3.2.3 Two-Stage Operational Amplifiers
Consider the two-stage op amps shown in Fig.3-7. Assuming that gm1 = gm2 = gmI ,
gm6
=
gmII,
gds2
+
gds4
=
GI
and
gds6
+
gds7
=
VDD
M41 : B
M3
M6
VOUT
M1
CC
M2
CL
VIN
ISS
Vbias
M5
M7
2 : B
VSS
(a)
VDD
M5
Vbias
M1
VIN
2
ISS
:
M2
B
M7
CC
VOUT
M3
M4
M6
1
:
CL
B
VSS
(b)
Figure 3-7: (a) Two-stage CMOS op amp with N-channel input pair and
(b) Two-stage CMOS op amp with P-channel input pair
From Fig.3-7(a) and Fig.3-7(b), we have the relationship as below:
Slew rate = ISS / CC
First-stage gain Av1 = -gm1 / (gds1 + gds4 )
36
GII.
Second-stage gain Av2 = -gm6 / (gds6 + gds7 )
Gain bandwidth = gm1 / CC
RHP zero z1 = gm6 / CC
Since the trans-conductance of N-channel input differential pairs is larger than P-channel
input differential pairs the gain of N-channel input differential pairs is larger than
P-channel input differential pairs. However, P-channel input differential pairs are still
popular to use in the application due to its lower flicker noise [12].
3.3 Pass devices
3.3.1 Design issue of the Pass device
Basically, we can classify the pass element into the bipolar, BiCMOS or CMOS
devices from Table 2.1. Regarding of the pass devices design issue, we must notice that
the drop-out voltage is further increased by series parasitic resistance inherent in the
layout. The size of the transistor must be large under low voltage conditions. There is
large load capacitance for the error amplifier (Cpar). A large device is further demanded
because voltage drive is reduced as a result of decreased input voltage. The increase in
CLoad for the feedback amplifier requires an increase in quiescent current flow. For
CMOS-based pass elements, increasing the aspect ratio, the sub-threshold currents can
become appreciably large. Thermal symmetry and equal current density distribution must
be maintained for reliability and best performance. The size of the pass devices must be
large for increased current capabilities but restrained by stability and slew rate
requirements in a low quiescent current flow and low voltage environment [5].
37
VDD
VREF
－
Error
Amp
+
(b)
VOUT
RF1
RF2
(a)
(c)
VSS
(d)
(e)
Figure 3-8 Pass elements of LDO linear regulator [11]
Fig.3-8(a) that using NPN-Darlington-type series pass element in LDO linear
regulator, typically requires at least 1.6V of voltage difference between input and output.
However, the LDO linear regulators usually have only 0.5V difference between input and
output voltage. The advantage of NPN-Darlington-type series pass element is stated in
Eq.(3.17)
Vdrop(a) =2VBE(NPN) + VCE(sat) (PNP) ≈ 2V
( 3.17 )
The NPN-type series pass element is constructed by a single NPN transistor driven by a
PNP transistor, illustrated in Fig.3-8(b). It is suitable for the LDO linear regulators which
can convert from 5V to 3.3V. The dropout voltage of LDO linear regulator with NPN-type
series pass element is stated in Eq. (3.18).
38
Vdrop(b) =VBE(NPN) + VCE(sat) (PNP) ≈ 1.25V
( 3.18 )
The PNP-type series pass element requires only a single PNP transistor, as
illustrated in Fig.3-8(c). The small dropout voltage is its major advantage. The dropout
voltage of LDO linear regulator with PNP-type series pass element is stated in Eq.(3.19).
Vdrop(c) = VCE(sat) (PNP) ≈ 100mV~600mV
( 3.19 )
Fig.3-8(d) and Fig.3-8(e) illustrate the NMOS-type series pass element and
PMOS-type series pass element. Many LDO linear regulators adopt MOS-based series
pass element because of the low quiescent current features. The NMOS-type LDO linear
regulators have wider bandwidth and do not need any external components such as
capacitors. Moreover, it provides unconditional stability due to its low output impedance
but the higher dropout voltage than PMOS-type LDO linear regulators is the obvious
disadvantage of the NMOS-type series pass element. The dropout voltage of NMOS-type
series pass element is at least one gate-to-source voltage(Vgs). The body effect increases
the threshold voltage of NMOS-type series pass element and thus further increase the
dropout voltage. Some researches utilize a charge pump connected to the gate terminal of
a NMOS-type series pass transistor to decrease the dropout voltage of NMOS-type LDO
linear regulators. The charge pump would raise the gate terminal’s voltage of NMOS-type
series pass transistor to be higher than the supply voltage to reduce the dropout voltage of
the NMOS-type LDO linear regulator. However, this technique may encounter reliability
problems due to the noise from the charge pump circuit [5].
3.3.2 Stability
A positive-feedback loop, instead of working against the conditions that force
variations across the input terminals of its mixer, helps external forces increase their
differentiating impact on what would have otherwise been a virtual short or mirror. This
39
positive-feedback effect is mathematically apparent when loop gain AOLβFB reaches
unity-gain frequency UGF, f0dB with a total shift in phase of 180o, as shown in Fig.3-9. At
this point and under these conditions, there is positive feedback at f0dB and ACL explodes to
infinity at f0dB because ACL ‘s denominator approaches zero: ACL = AOL / (1+ AOLβFB) =
AOL / (1-1) ∞.
The criterion for a feedback circuit to remain stable is therefore to ensure the loop
gain LG or AOLβFB has less than 180o of phase shift at the loop gain’s f0dB. Because of this
unstable point, phase margin (PM) refers to how much margin in phase exists at f0dB
before reaching 180o. Similarly, gain margin (GM) is how much margin there is in gain
below the 0dB axis before reaching the frequency where the loop gain incurs 180o of
phase shift. As a result, the closed-loop circuit’s proneness to instability increase with
decreasing phase and gain margins PM and GM, as illustrated in Fig.3-10.
Loop gain AOLβFB [dB]
X
p1’
AOLβFB
-20dB/decade
Phase [o]
p2’
X
Phase
f0dB,180
0o
90o
180o
-40dB/decade
0dB
Frequency(Hz)
f0dB,0dB
Figure 3-9 Open-loop gain and phase
Each pole shunts incoming signals to ac ground at a rate of 20dB per decade past
the pole’s location as frequency increases, and phase-shifts signals by approximately -90 o
a decade past it, -45o at its location, and 0o a decade before it, as illustrated in Fig.3-9 for
poles p1 and p2. A zero, on the other hand, feeds forward a signal and increases its
40
magnitude by 20dB per decade past the zero’s location and phase-shifts it by +90o, +45o,
and 0o a decade past, at, and a decade before it. Similarly, a right-half-plane (RHP) zero
also feeds forward a signal and increases it by 20dB per decade, like a
left-half-plane(LHP) zero, but like a pole, phase-shifts it by -90o, -45o and 0o a decade
past, at, and a decade before it.
Fig.3-9 graphically illustrates the Bode-plot response of a two-pole system whose
pole locations precede f0dB by at least one decade so PM is zero, which constitutes the
makings of an unstable system. Since each pole phase-shifts a signal -90o, there is already
180o of phase shift by the time the loop gain crosses the 0dB axis, resulting in zero phase
and gain margins. Having the second pole been within a decade of f0dB , there would have
been less than 180o of phase shift at f0dB and more phase and gain margins, attenuating the
close-loop gain’s peaking effect in Fig.3-10, which is a manifestation of instability or
growing oscillations at peaking frequency f0dB [3].
ACL [dB]
PM2
PM1 > PM2
1/βFB
PM1
Frequency(Hz)
0dB
f0dB
Figure 3-10 Resulting closed-loop gain responses of a negative-feedback circuit as
phase margin (PM) decreases to its unstable state of 0o
41
3.3.3 Frequency compensation
The generation strategy for stabilizing negative-feedback circuits is to ensure the
loop gain AOLβFB approaches the unity-gain frequency f0dB at a rate of -20dB per decade,
as illustrated in Fig.3-11, while keeping all right-half-plane (RHP) zeros at considerably
higher frequencies. Conventionally, a single dominant low-frequency pole p1 is
established, a secondary pole p2 placed near or above f0dB,and all remaining parasitic
poles placed at least a decade above f0dB ensuring an overall phase margin of 45o or
greater. We may allow one or two in-band poles and use left-half-plane (LHP) zeros to
cancel their shunting effects within a decade below f0dB. This latter technique is less
popular because the system is more prone to instabilities during start-up conditions, when
the gain and its respective poles and zeros shift before reaching their steady-state
locations. Besides, a rather useful result of a single-pole response is that the
gain-bandwidth product (GBW) along the -20dB per decade drop is constant and equal to
unity-gain frequency f0dB because the gain decreases by the same factor the frequency
increases.
Loop gain AOLβFB [dB]
X
p1’
AOLβFB
Phase shift [o]
-20dB/decade
0dB
0o
p2’
Phase
X
-90o
Frequency(Hz)
f0dB,0dB
-180o
-40dB/decade
f0dB,45
o
Figure 3-11 Stable Bode-plot response of a negative feedback circuit
42
Since regulators suffer from relatively extreme variations in load, allowing one pole
and offsetting its effects with a LHP zero is more acceptable in regulators. A circuit’s
response to a step input change is a time-domain manifestation of phase shift and phase
margin (PM). More explicitly, delay represents phase shift and overall settling time
corresponds to PM, which means multiple poles further delay the circuit and lower PM
values increase oscillations and settling time. On one extreme, zero PM prevents the
output from settling to its intended target, and on the other, 90o of PM eliminates all
oscillations in the response, allowing the output to approach its target without
overshooting it. Similarly, 45o of PM produces less than three oscillating rings in the
output before settling within 10% of its target, extending settling time beyond its 0-90%
delay by approximately three f0dB equivalent periods. Although not always the case, a PM
target of 45o is a popular design objective for feedback circuits [13].
3.3.4 Pole splitting
Miller capacitor must be huge to push the LDO linear regulator output pole beyond
the unity gain frequency (UGF). Miller capacitor with Cgs of pass transistor will form a
direct path for power supply spurs to output. The circuit has to be modified to have an
extra buffer stage and this modification introduces additional parasitic poles. However,
the disadvantages of miller compensation will reduce the bandwidth, slew rate and need
more power and area. The topology that creates the zero by using feedforward techniques
but still Miller techniques is employed [14].
3.3.5 Equivalent series resistance (ESR) compensation
The ESR shown in Fig.3-12 is not properly specified and varies with temperature,
and the high-frequency bypass capacitors placed in parallel with the output capacitor form
43
a pole further decrease the phase margin. Ceramic capacitors are cheaper than tantalum
capacitors, but ESR of ceramic capacitors typically less than 0.05Ω. ESR increases the
overshoot drastically if large resistors are used [4].
VDD
VREF
－
Error
Amp
+
gmp
Cpar
RDS
VOUT
Roa
Resr
RF1
IL
A
VFB
Cb
CL
RF2
VSS
Figure 3-12 Equivalent series resistance (ESR) of Resr
A smaller ESR has a better load transient performance that is less overshoots and
undershoots. The ESR zero would not be involved since it locates at a very high
frequency. Fig.3-13 illustrated that the dominant pole p1 due to the output capacitor is
located at a very low frequency, so the required value of CL is huge. The dominant pole p1
is shifted to higher frequency (p1’) for a higher load current and the LDO may be unstable
at a certain load. p2 may locate before the unity-gain frequency (UGF). The generic LDO
should be compensated at the maximum load current. The UGF of loop gain is
constrained by p2, where the bandwidth is small, and loop response is slow. The LDO
using the dominant-pole compensation usually has a narrow bandwidth and requires a
huge capacitor [14].
44
|T(s)| Load current increases
p1
p1’
X
X
X
0dB
Frequency
X
p2
Figure 3-13 Stability of LDO using dominant-pole compensation [14]
3.3.6 Charge pump booster
From Fig.3-14 it generates a voltage higher than the supply voltage and the error
amplifier utilizes the voltage. The charge pump booster will provide low output
impedance. However, due to the higher voltage generated, it might not be well suited for
advanced technique such as high voltage (HV) process [14].
VDD
VREF
－
Error
Amp
+
gmp
Cgdpass
RDS
VOUT
Resr
Charge Pump
RF1
Booster
IL
A
VFB
Cb
CL
RF2
VSS
Figure 3-14 Charge pump booster of Cgdpass
45
3.3.7 Protection circuit
3.3.7.1 Overload current protection
From Fig.3-15 the current limiting circuit ensures that the current through the
power transistor stays within a specified range. Maximum power dissipation of the power
transistor occurs when the output is short circuited to ground, which corresponds to a
voltage drop across the device equal to the input voltage: Po-max = VIN x IO-max. One
disadvantage of this configuration is the deterioration of the drop-out voltage by the
voltage drop across the resistor RS. Transistor Qn1 (Qp1) is OFF during normal operating
conditions. When the load-current increases to the point where the voltage drop across RS
is roughly 0.7V, then the transistor conducts current [3].
VDD
VDD
RS
VOUT
Qp1
IRs
Qn1
RS
Io-max
VOUT
VOUT
Figure 3-15 Current limiting circuit protection [10]
46
3.3.7.2 Reverse battery protection
Fig.3-16 shows that the backward installation of batteries is a common occurrence
that could irreparably damage a chip if precautions are not taken.
VDD
+
Parasitic
diode
－
－
+
LDO
reverse
battery
VSS
Figure 3-16 Reverse battery protection [3]
The series diode, bipolar switches, and MOS switched are not well suited for a low
voltage, low drop-out regulator. The series diode and the high side switches exhibit
voltage losses that degrade the drop-out voltage of the regulator by a Vbe, a Vec-sat, or a
Vsd-sat. The low side switch versions exhibit voltage losses on the ground terminal. If the
minimum input voltage of the regulator is 1V, then the battery voltage must be greater
than 1V+Vsat, which can be approximately 1.1~1.2V. Bipolar switch versions are
inappropriate for a low quiescent current environment. The advantage of MOS over
bipolar versions is that there is no net current loss during normal operating conditions.
The most appropriate circuit for current efficient, low voltage, low drop-out regulator is
the shunted diode. The disadvantage is its current flow during reverse battery operation is
large [14].
47
3.3.7.3 Electrostatic-Discharge protection
Electrostatic discharges (ESD) are not entirely unlike reverse-battery conditions,
except the former are short lived, occur in both directions, and the voltages involved are
substantially higher. Most ESD strikes result from one of three basic mechanisms. The
first and most obvious source is the human touch, after generating static charge by
walking across a carpet, for example, which is modeled by what is termed the
human-body model (HBM). Similarly, although from a different source, the machine
model (MM) mimics the charge transferred to the IC when machines handle the chips
during the bundling and shipping processes. Finally, the charged-device model (CDM)
describes the electrical conditions that result when a pre-charged chip, after sliding down
its plastic container, touches chassis ground. Note the common thread in all these
conditions is the sudden release of charge, which is why pre-charged picofarad capacitors
with initial voltages ranging from 250V to 5kV and various series resistances emulate
these undesired but realistic events. The performance of ESD circuits is strongly
dependent on device layout and process technology, and predicting the extent to which
they protect the IC is largely empirical. ESD structures, as a result, vary significantly
across process, the junctions and poly-silicon materials they protect, and even
semiconductor companies. What is worse, all input and output pins (I/Os) are susceptible
to positive and negative ESD strikes so they all need protection [15].
48
VDD
Circuit
VDD
RP
_
vPIN
QP
VD
+
_
VD
+
Circuit
QN
RN
VSS
VSS
(a)
(b)
Figure 3-17 Common electrostatic-discharge (ESD) protection circuits [11]
Forward biasing diodes as shown in Fig.3-17(a), where positive and negative
strikes engage the supply and ground diodes, respectively, and clamp vPIN to VDD + VD and
VSS –VDD . The drawback to this approach is that the response to positive strikes relies and
depends on VDD’s ESD clamp, which means current circulates from vPIN through the IC to
VDD before finally reaching ground. Silicon-controlled rectifiers, as illustrated in Fig.
3-17(b), are also popular ESD structures. These circuits rely on latch up, which is a
manifestation of positive feedback, to steer ESD energy away from the sensitive circuit.
During normal operating conditions, for example, there is no base-emitter voltage across
either BJT to engage the circuit. Forward biasing one of the base-emitter junctions,
however, with sufficient transient energy to induce a collector current engages the
complementary BJT and latches the circuit. As QN causes QP to conduct, QP responds by
forward biasing QN further, accentuating the forward biasing process and causing the
collector currents to increase and absorb the incident ESD energy. Bear in mind, noise
energy should not engage the SCR so the design should include sufficient noise margin to
prevent inadvertent latch-up events from occurring [3].
49
3.3.7.4
Thermal shutdown protection
The power transistor operates under extreme temperatures that can cause damage to
the circuit. Thermal shutdown protection circuit prevents such an occurrence from
happening. Thermal shutdown protection circuit as shown in Fig.3-18, The Temperature
coefficient (TC) of Vbe is -2mV/K. If the threshold temperature is roughly 150oC, then
the base of the transistor must be biased at a voltage of approximately 400mV (ie:
0.7V-150 x 2mV). The thermal sensing transistor must be physically close to the power
device [14].
VDD
VREF
－
Mirror
Error
Amp
+
VOUT
VSS
Figure 3-18 Thermal shutdown protection circuit [3]
50
CHAPTER 4
PROPOSED LDO DESIGN
The circuit designs of the LDO were simulated by Hspice with TSMC 0.35µm
2Poly-4Metal CMOS models. It works at 3.3V or 5V supply and operates from 2V to
2.8V of the output. In the following sections, we will introduce the design of the main
circuit blocks and the simulation results will be presented in the next chapter.
4.1 LDO Architecture
From Fig.2-1 shows the block level of LDO, including (1) error operational
amplifier circuit, (2) bandgap voltage reference circuit, (3) start-up circuit, (4) PMOS
pass element circuit and (5) feedback network circuit [14].
4.2 Design Challenge
We point out some problems of LDO design challenge as below [16]:
(1) The non-dominant complex poles have a large Q and locate near UGF in Fig.4-1.
(2) Stability.
(3) Type and value of the output capacitor.
Loop gain
Low output current
LoL
non-dominant
LoH
complex poles
high output current
0dB
Gm(input stage)
UGF
Cm(compensation capacitor)
|
Frequency
Q Damping
Figure 4-1 Loop gain of pole-splitting-based LDO at different output currents [4]
51
4.3 Bandgap Reference Circuit Design
The function of a reference voltage generator is to produce a stable reference
voltage of which is independent of the supply voltage and the temperature variation. In
general a traditional bandgap voltage reference offers a good quality reference voltage at
about 1.25V. Fig.4-2 illustrates the core of bandgap reference circuit at the left-hand side
and a start-up circuit at the right-hand side.
VDD
MB1
MB2
MB9
MB3
MB4
MB10
MS1
MS3
MB5
MB6
MB7
MB8
X
MS4
Z
VREF
MS2
Y
R1
Q1
R2
Q2
Q3
VSS
Figure 4-2 Proposed Bandgap reference circuit
The cascade current mirror can made up the bias for the other use. The gate
voltages of transistor MB1, MB3, MB5 and MB7 are not sensitive to VDD supply variation.
The output impedance is higher than a traditional bandgap voltage reference. The
advantage is to reduce the power dissipation. On the other hand, in order to avoid that all
52
transistors are in the state of no current when start-up driving the start-up circuit is added
to prevent this situation [4]. In Fig.4-2, if zero current state occurs, MS2 is in OFF state.
The gate of MS1 is connected to the ground so that MS1 is always in ON state. Therefore,
the voltage of the node of Z will be increasing smoothly. Then, the transistors of MS3 and
MS4 will be driving to ON state. The current will flow through in the loop of the circuit
until MS2 into the saturation. After that the voltage of the node of Z will be gradually
pulling down. The function of the start-up circuit will be terminated. We can control the
zero TC in the room temperature [5]. Fig.5-1 and Fig.5-2 are the simulation results.
4.4 Bias, Error Amplifier and Pass Device Circuit Design
In Fig.4-3, MP1, MP2, MN3～MN6 and RX form the bias circuit. M1, M2, M3, M4 form
the first stage [11], the current buffer is formed by M3, M4 and Ccf and M5, M6, M7 and M8
form the second non-inverting gain stage. MP is the power PMOSFET forming the third
stage, and Cgd is its gate-drain parasitic capacitance. M1,M3 and M8 form the feed-forward
transconductance stage. Cm1 and Ccf are the required on-chip capacitance of the proposed
structure. RF1 and RF2 construct the feedback resistive network. RL and C3 model the
equivalent load resistance and load capacitance at the power line. Fig.4-3 also shows that
the bias current of the current buffer is, in fact, the bias current of the input stage. The
high-gain property of the amplifier enforces the bias current of M3 and M4 to be nearly
equal. Therefore, the proposed circuit implementation is simply and consumes less power.
Both M6 and M8 form such that the gate capacitance of the power PMOSFET can be
charged and discharge more effectively for fast load transient responses. Left hand side is
a bias circuit that gives very predictable and stable transistor transconductances [4].
53
VDD
MP1
MP2
MN 3
MN 4
MN 5
M1
M6
MP
M8
Cgd
M2
MN 6
VREF
M3
RX
M7
RF1
Ccf
RL
M5
M4
VOUT
Cm1
M9 RF2
Q-Reduction circuit
VSS
Figure 4-3 Proposed Bias, Error Amplifier, Pass Device and Feedback Network
4.5 Overall LDO structure
From Fig.4-4, we can get the loop gain frequency response in Eq.(4.1) [4]
Cml
Q-reduction circuit
gm1
－
vcf
Rcf
－
p
Cgd im2
gm3
．
．．
．． － ．．
gm2
gmcf
． ．．．
．C ．．C
vi
im1
v1
R1
+
v2
1
Ccf
vo
R2
C2
C3
R3
icf
VDD
v2
+
Cgd
gmfl
vo
Power PMOSFET
Figure 4-4 LDO structure (open loop)[4]
Cgd
CgdCcfRcf
Cm1gmf1
2 Cm1(Cgd + C2)
]}
) s[
+
-gm1gm2gm3{1+s(CcfRcf + g g
g
g
g
gm3
m3
m1 m2
m2 m3
≈
L(s)=
Vi(s) (1+sCm1gm2gm3R1R2R3)[1+s Cm1Cgd (gm3-gm2)+CcfC3 gm2+ Cm1Ccf gm2 gm3Rcf +s2 (Cgd+C2+Ccf) C3]
Cm1gm2gm3
gm2gm3
Vo(s)
( 4.1 )
54
The Q-reduction circuit is formed by Ccf and a current buffer. A feed-forward
transconductance stage gmf1 is used to generate a Left Half-Plane (LHP) zero to improve
both stability and slewing at MP.
From UGF=gm1 / Cm1 when lower UGF by a larger Cm1 can help to increase the
phase margin. A smaller gmcf and a larger Ccf can help to reduce Q. gmf1 can control the
position of z1 for positive phase shift. Based on the output current level, we can analyze
the loop gain according to the following 3 cases.
<Case 1> Moderate to maximum output current: gm3 > gm1 and gm2
We can get the following Eq. (4-2)
sC gmf1 )
-gm1gm2gm3R1R2R3 (1+ gm1
m2gm3
L(s)≈
(C +C )
2+Ccf) C3
(1+ sCm1gm2gm3R1R2R3) [1+ s gdg cf + s2 (Cgd+C
]
gm2gm3
m2
( 4.2 )
When the output current is high, gm3 is very large. There are three poles and one
zero such as
p1 = 1 / cm1gm2gm3R1R2R3
p2 = gm2 / (Cgd + Ccf)
p3 = [{Cgd + Ccf}gm3] / [(Cgd + C2 + Ccf) C3]
z1 = gm1gm2 / Cm1gmf1
1.
For a large gm3, p3 is at a high frequency and has no effect on stability.
2.
z1 is used to cancel p2 ( LDO is stable )
<Case 2> Low to moderate load current: gm3 >= gm1 and gm2
There is a pair of complex poles since the coefficients of Eq. (4.1) have the
following relationship when gm3 is not much larger than gm1 and gm2:
Cm1Cgd (gm3 -gm2)+CcfC3gm2+Cm1Ccfgm2gm3Rcf 2
[
]
Cm1gm2gm3
(Cgd+C2+Cc f )C3
<= 4
gm2gm3
( 4.3 )
By solving Eq. (4.1), there are one pole p1 = 1 / cm1gm2gm3R1R2R3, one pair of complex
poles, and one zero z1 = gm1gm2 / Cm1gmf1. The pole frequency of the complex poles is
55
given by
ωo ≈ √ [
gm2gm3
]
( 4.4 )
(Cgd+C2 )C3
And its Q is given by Eq. (4.5),
Q= √ [
α
Cm1gm2gm3
(Cgd+C2 )C3
]
][
gm2gm3
Cm1Cgd (gm3 -gm2)+CcfC3gm2+Cm1Ccfgm2gm3(1/ gmcf)
( 4.5 )
k1
k2+[Ccf (k3+ k4/gmcf)]
where k1, k2, k3 and k4 are constants dependent on load-current level. From Eq. (4.4), a
higher output current, hence a larger gm3, results in a higher ωo and the stability of the
LDO will be improved. From Eq. (4.5), the Q-reduction circuit decreases Q linearly by a
larger Ccf and a smaller gmcf of the current buffer. Therefore, the minimum output current
of the LDO can be reduced effectively by controlling Ccf and gmcf separately. The phase
margin (PM) of the LDO in this case can be evaluated by
PM=180o
=90o
UGF
UGF/ωo
-1 UGF
}
tan-1( p ) tan-1{
2 +tan ( z1 )
1
Q [1 (UGF/ωo) ]
UGF/ωo
tan-1{
Q [1
(UGF/ωo)
2
}+tan-1( UGF )
z1
]
( 4.6 )
where UGF = gm1 / Cm1. From Eq. (4.6), there are a few important implications for the
design. (1) The critical phase reduction is due to ωo. Therefore, a lower UGF by a larger
Cm1 can help to increase the phase margin. (2) A smaller gmcf and a larger Ccf help to
reduce Q, as shown in Eq. (4.5). This can help to reduce the negative phase shift for more
phase margin. (3) The parameter gmf1 is very useful to control the position of z1 for
positive phase shift. Since, according to Eq. (4.4), ωo is low when gm3 is low (or light
load). The position of z1, in terms of gmf1, should be designed in light-load condition.
<Case 3> Low to moderate load current: gm3 < gm1 and gm2
When the load current is very small, the small gm3 will result in an unstable LDO.
The boundary between stable and unstable regions of the LDO is address here. It is
56
well-known that right-half-plane (RHP) pole causes unstable negative feedback system.
From the denominator of Eq. (4.3), RHP poles can be avoided when the s term in the
second-order function is positive. Therefore, the necessary condition is given by
Cm1Cgd (gm3 -gm2)+CcfC3gm2+Cm1Ccfgm2gm3 Rcf > 0
The minimum gm3 is
( 4.7 )
Ccf +C3 g
) m2
Cm1+Cgd
gm3(min)=
C
1 ( C cf ) gm2Rcf
gd
(
( 4.8 )
Therefore, the minimum load current that the proposed LDO is stable can be found
indirectly from gm3(min). In general, it requires a current higher than the bias current of
the resistive feedback network that passing through the power PMOSFET [4].
Combining Fig.4-2 and Fig.4-3, we can get the schematic of the proposed LDO
as shown in Fig.4-5.
VDD
MB1
MB2
MB9
MB3
MB4
MB10
MS1
MN3
MS3 MS4
MB5
Mp2
Mp1
Z
M1
MN4
MN5
M2
M3
Cgd
VREF
M7
MB8
M4
M5
MP
VOUT
Cm1
MN6
MB6
MB7
X
M8
M6
RF1
Ccf
M9 RF2
MS2
Y
R2
R1
Q1
Q2
RX
Q3
VSS
MB1=
MB5=
MB9=
MS3=
MN3=
M 1=
M 5=
M 9=
R1=
RF2= Cgd=
6.16/ 6.16
2/0.6
32.55/7.7
0.4/0.4
15/16
2.5/6
1.2/12
16/8
10K
180.6K 6.4P
MB2=
MB6=
MB10=
MS4=
MN4=
M 2=
M 6=
MP=
R2=
RL=
CL=
6..34/ 6.34
2/0.6
32.55/7.7
0.4/0.4
15/16
10/4
1/0.4
20/0.4
33.3K
10K
100P
MB3=
MB7=
MS1=
Mp1=
MN5=
M 3=
M 7=
RX=
Cm1=
6.16/ 6.16
2/2
0.4/3
25/16
15/20
10/4
1/8
8K
5P
MB4=
MB8=
MS2=
Mp2=
MN6=
M 4=
M 8=
RF1= Ccf=
6..34/ 6.34
2/2
1/0.4
25/16
15/16
1.2/12
16/0.4
224K
Component size W/L (µm/µm) Figure 4-5
Schematic of the Proposed LDO
57
2P
RL
CL
CHAPTER 5
LDO SIMULATION RESULTS
In this chapter, the following sections present the simulation result of the proposed
LDO and the prototype of the whole chip layout.
5.1 Bandgap Reference
According to the bandgap reference circuit shown in Fig.4-2, we can get VREF
versus temperature as shown in Fig.5-1. With VDD =3.3V (corner: TT), we get VREF
=1.25V at room temperature.
Figure 5-1 VREF vs Temperature
VREF versus VDD is shown in Fig.5-2.With VDD from 3V to 5.5V, VREF is varied from
1.2340V to 1.256V, respectively.
58
Figure 5-2 VREF vs VDD
5.2 LDO
5.2.1 Open-loop gain
Fig.5-3 shows the frequency response without Q reduction circuit, where the Q
damping will appear. With VDD = 3.3V (corner: TT), the gain and the phase margin are
73.2dB and 70o, respectively.
Q damping
Figure 5-3 Gain and phase without Q reduction circuit
59
Fig.5-4 shows the frequency response with Q reduction circuit. The gain and the phase
margin are 73.2dB and 80o as shown in Fig.5-4. The phase margin has been improved.
Figure 5-4 Gain and phase with Q reduction circuit
Repeat the simulation again with VDD = 4V (corner: TT). Without Q reduction
circuit, the gain and the phase margin of the open-loop gain are 58.3dB and 70o as shown
in Fig.5-5.
Q damping
Figure 5-5 Gain and phase without Q reduction circuit
60
With Q reduction circuit, the gain and the phase margin are 58.3dB and 80o as shown in
Fig.5-6. Also, the phase margin is improved.
Figure 5-6 Gain and phase with Q reduction circuit
5.2.2 Start-up time
Fig.5-7 illustrates that the start-up time of LDO. The condition is set to VDD = 3.3V,
and when VREF is varied from 0.5V to 1.25V. The start-up time is around 2.9us when
VOUT=2.7994V.
Figure 5-7 Start-up time
61
5.2.3 Line regulation
Fig.5-8 to Fig.5-12 show that VOUT versus VDD with five corners. The simulation
condition is set at VDD = 3.3V and IOUT = 10mA.
Figure 5-8 VOUT vs VDD (corner: TT)
Figure 5-9 VOUT vs VDD (corner: SS)
62
Figure 5-10 VOUT vs VDD (corner: SF)
Figure 5-11 VOUT vs VDD (corner:FS)
63
Figure 5-12 VOUT vs VDD (corner:FF)
Therefore, we can summarize the results as shown in Table 5.1. The tolerance of VOUT is
within 2%.
Table 5.1 VOUT of five corners from TT to FF under Pre-layout simulation
0.35um technology
VDD = 3.3V @ IOUT = 10mA
CMOS 2P4M
Corner
TT
SS
SF
FS
FF
VOUT
2.8001V
2.7681V
2.7960V
2.7987V
2.8032V
64
5.2.4 LOAD TRANSIENT RESPONSE
The simulation condition is set to VDD = VOUT + 1V when IOUT is the light load from
0 to 100uA and then repeat again from 100uA to 0 with CL = 100pF. However, without Q
reduction circuit, the VOUT is under oscillation as shown in Fig.5-13.
Oscillation
Figure 5-13 Load Transient Response without Q reduction
Repeat the step again. With Q reduction circuit, the load regulation is around
0.000036%/uA as shown in Fig.5-14.
Note:
Figure 5-14 Load Transient Response with Q reduction
Load Regulation = [ ( (VOUT2 – VOUT1) / VOUT2) x 100%] / ( IOUT2 – IOUT1) [ %/uA]
65
For heavy load, the simulation condition is set to VDD = VOUT + 1V when IOUT is from 0
to 150mA and then repeat again from 150mA to 0 with off-chip COUT = 10uF and ESR =
0.3Ω. The load regulation is around 0.0032%/mA as shown in Fig.5-15. Fig.5-16 shows
the post-layout simulation result. The load regulation is around 0.0041%/mA.
Figure 5-15 Load Transient Response with heavy load
Note:
Figure 5-16 (Post-sim) Load Transient Response with heavy load
Load Regulation = [ ( (VOUT2 – VOUT1) / VOUT2) x 100%] / ( IOUT2 – IOUT1) [ %/mA]
66
5.2.5 LINE TRANSIENT RESPONSE
The simulation condition is set to VDD = VOUT + 1V to 5V when IOUT = 10mA with
CL = 100pF, and the line regulation is around 0.029%/V as shown in Fig.5-17. Fig.5-18
shows the post-layout simulation result. The line regulation is around 0.012%/V.
Figure 5-17 Line Transient Response
Note:
Figure 5-18 (Post-sim)Line Transient Response
Line Regulation = [( (VOUT2 – VOUT1) / VOUT1 ) x 100%] / [ 5V–( VIN =VOUT +1V)] [ % /V]
67
5.2.6 DROPOUT VOLTAGE
Ramp down VDD and then measure VOUT until a 2% change and the dropout voltage
is the differential voltage between VDD and VOUT. The dropout voltage is around 190.6mV
as shown in Fig.5-19. Fig.5-20 shows the post-layout simulation result. The dropout
voltage is around 185mV.
Figure 5-19 Dropout Voltage
Figure 5-20 (Post-sim)Dropout Voltage
68
5.2.7 QUIESCENT CURRENT
The simulation condition is set to VDD = 3.3V and IOUT = 0mA. The quiescent
current IQ is around 517.99uA as shown in Fig.5-21. Fig.5-22 shows the post-layout
simulation result. The quiescent current is around 518.88uA.
Figure 5-21 Quiescent Current
Figure 5-22 (Post-sim)Quiescent Current
69
5.3 PERFORMANCE SUMMARY OF THE PROPOSED LDO
Now we can summarize the overall results as shown in Table 5.2.
Table 5.2 Performance summary of the proposed LDO
Pre-layout sim.
Post-layout sim.
TSMC 0.35um
TSMC 0.35um
CMOS 2P4M
CMOS 2P4M (D35)
VIN
3.3V
3.3V
VOUT
2.8V
2.8V
Power Dissipation
1.7094m watts
1.7123m watts
IQ @ IOUT = 0mA
517.99uA
518.88uA
0.029 %/V
0.012 %/V
0.0032 %/mA
0.0041%/mA
Dropout Voltage @ IOUT = 150mA
190.6mV
185mV
Off-chip capacitance ( COUT)
10uF
10uF
IMAX
150mA
150mA
Chip size (mm2)
NA
0.1
Technology
Technology
Line Reg. @ VIN = VOUT +1V to 5V
( IOUT = 10mA)
Load Reg. @ IOUT = 0 to 150mA
with Heavy load ( COUT = 10uF)
70
A comparison is made with other output on-chip capacitor designs, shown in Table
5.3, illustrating the significance of the proposed external capacitor LDO regulator. Not
only does the proposed regulator consume low power, but also it provides a low dropout
voltage.
Table 5.3 Comparison of result
***[17] **This work
Parameter
*[7]
***[19]
***[5]
***[18]
Year
2004
2007
2009
2010
2010
2011
Technology
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
0.5um
0.35um
0.35um
0.35um
0.35um
0.35um
Vin [V]
5
3
3-5
1.8-4.5
2.5-5.5
3-5
Vout [V]
3.3
2.8
1.5
1.6
1.5-4.5
2.8
IQ [mA]
0.15
0.065
0.04
0.02
0.025
0.52
Line Reg. [%/V]
0.15
NA
0.025
NA
0.05
0.012
Load Reg. [%/mA]
0.00012
NA
0.0016
NA
0.001
0.0041
Dropout Voltage
350
200
280
200
150
185
CCOMP [F]
NA
20p
7p
7p
NA
7p
CL [F]
1u
100p
NA
100p
0.47u
100p
Imax [mA]
300
50
100
100
150
150
Chip Size [mm2]
NA
NA
0.14
0.145
NA
0.1
[mV]
Note: * represents that the data of the pre-simulation,
** represents that the data of the post-simulation and
*** represents that the measured data of the chip testing.
71
5.4 PROTOTYPE AND FLOOR-PLAN
The floor plan and completed layout of the proposed LDO are shown in Fig.5-23
and Fig.5-24, respectively. The chip size is 1058µm x 947µm without I/O PADs.
Bandgap
Error
Amplifier
Capacitor
Dummy
Resistor
Bandgap
PMOS
Dummy
Figure 5-23 The floor plan of the layout
BG
EA
Cap
Resistor
PMOS
BG
Figure 5-24 Whole chip layout
72
After the chip out, we may use the following test instruments to verify the LDO
chip function in the laboratory. A test setup used to measure the LDO chip is as shown in
Fig.5-25.
Figure 5-25 A test setup used to measure the LDO chip [20]
73
CHAPTER 6
CONCLUSIONS
6.1 Conclusions
In this thesis, we design a LDO with Q-reduction circuit. The Q-reduction circuit
enable a smaller chip area and lower output current requirement for future SOC with local
voltage regulations, and it reduces area and cost in the IC. In addition, its structure is easy
to design and it is more suitable for the power management nowadays.
6.2 Future Work
The protection circuit such as over-temperature protection (OTP), over-load current
protection (OCP), over-voltage protection (OVP), short circuit protection and also the
reverse battery protection are becoming more and more important in the power
management IC products. Therefore, the protection circuit must be incorporated in the
future work.
74
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