An Analytical Crosstalk Model with Application to ULSI Interconnect Scaling
Dennis Sylvester, O. Sam Nakagawa *, and Chenming Hu
Department of Electrical Engineering and Computer Sciences
University of California, Berkeley
* ULSI Laboratory, Hewlett-Packard Company, Palo Alto, CA
Cc
Ra
Abstract
A new analytical model is presented to accurately determine
crosstalk noise due to on-chip interconnections. This model takes
+
into account interconnect line resistance and driver strength,
which have not been adequately considered in previous crosstalk
+
Vdd
Cv Rv Vx
Ca
models. Our model can be used in conjunction with simple
Tr
analytical device timing expressions to provide close agreement
with SPICE simulations for peak crosstalk in 0.25 µm technology
generations and beyond. Furthermore, the model is applied to
future ULSI interconnect scaling scenarios to analyze their impact Fig. 1 Simplified circuit schematic described in the text. Aggressor
is modeled as a voltage source with ramp rate Vdd/Tr, and crosstalk is
on noise issues.
denoted as Vx. Rv is the sum of victim driver and line resistances.
Introduction
On-chip crosstalk is a major concern in ULSI circuits due to
scaling linewidths, increasing aspect ratios and larger die sizes.
Also, due to decreasing noise margins and larger ground bounce,
noise issues become even more important. There is a need for
accurate yet fast methods to analyze on-chip crosstalk.
Previously presented crosstalk models typically ignore wiring
resistance [1,2] or apply only to step inputs [3]. Our model is
simple, accurate and provides an excellent basis for a crosstalk
screening tool. We demonstrate its accuracy in future generation
logic gates, concentrating on inverters and NAND gates. The
model can be used in conjunction with timing macromodels or
other timing models, as driver rise time is an important parameter
in crosstalk calculation. We introduce one such timing model for
use in this paper. Finally, we use our model to analyze future
developments in ULSI interconnect and their impact on peak
crosstalk. Specifically, we focus on the move to low-k dielectrics
and copper wiring.
Model Derivation
Crosstalk is a complex form of electromagnetic coupling
between two or more conducting lines. In order to obtain a
tractable analytical expression for peak crosstalk noise, several
assumptions must be made. First, the aggressor gate is modeled
as a ramp voltage source with rise/fall time, Tr. This rise time can
be obtained by use of a circuit timing simulator or through use of
analytical expressions such as those presented in [4]. A new
timing macromodel is presented in the next section for this
purpose. A second assumption is that all interconnect and load
capacitances (including fan-out gates and drain junction
capacitances) are modeled as a lumped capacitance to ground,
excluding the coupling capacitance. Finally, the victim line
driver is modeled as an effective resistance. This resistance can
be found using the slope of a device’s Id-Vd curves at the origin
and need only be found once for a given technology as it scales
with device width.
The resulting equivalent circuit is shown in fig. 1. From circuit
analysis principles, the victim line voltage, Vx, can be found to
be:
Vx =
Vx =
R v Cc Vdd
τ0 Tr
 
R v Cc Vdd  1  −
e
τ0Tr τ1 


 
t
τ1
− e
−
−t
−t


τ1
τ2
e
e
τ
+
τ
−
τ
1
2
 0



1 −
−
 τ e

2 


(t − Tr 
)

τ1
t
τ2
− e
−





( t − Tr )
τ2
(1)






(2)
In these equations, Tr is the rise time at the output of the
aggressor driver and τ0, τ1 and τ2 represent different time
constants of the circuit. Definitions of these time constants are
contained in the appendix. Eqn. (1) is applicable during the
aggressor rise time, Tr, and (2) applies when t > Tr. The peak
value of crosstalk noise, Vmax, can be found by differentiating (2)
as this peak always occurs at t > Tr.
Vmax

 Y1
R v C c Vdd 
=
τ1 Y1 
Y
τ 0 Tr 
 2

τ2
 Y1
 τ1 − τ2

− τ 2 Y2 
Y

 2

τ1 
 τ1 − τ2 






(3)
Here Y1 = exp(-Tr / τ1) –1 and Y2 = exp(-Tr / τ2) –1. For slow rise
times (Tr >> τ2), (3) can be seen to approach a limiting value of
RvCcVdd / Tr. Also, the model presented in [3] is a special case of
(3) when Ra = Rv, Ca = Cv and the gate output is a step. Thus, the
model can be seen to have wider applicability than those
presented previously.
Deep submicron interconnect cannot be effectively modeled by
a lumped RC model. However, to derive a simple analytical
model, a lumped topology must be assumed. So, for our model to
accurately represent on-chip interconnect the capacitances must
be scaled to account for the distributed properties of an RC line.
Fig. 2 shows the representative cross-section of the 3-line system
utilized throughout this paper. Based on the Elmore delay model,
the ground capacitances Ca and Cv are scaled by a factor of 0.5
(for an N-step ladder, the factor (N+1) / 2N should be used) since
the distributed capacitances only see the upstream resistance,
rather than the total line resistance [5]. Coupling capacitance is
scaled by a different, larger which is technology independent and
given by:
α = (1 − χ)e
− Tr
τ0
+ χ
(4)
W
S
45
Cc
Cc
Ca
Cv
Ca
Ground Plane
Fig. 2 Cross-sectional representation of the 3-line conductor system
used in this paper. Worst-case crosstalk occurs when two aggressor
lines switch simultaneously, acting upon a single victim line.
The parameter χ is a simple expression accounting for the victim
driver resistance and is equal to 1 for shorter lines (devicedominated) and 0.5 for long lines (interconnect-dominated). As
mentioned earlier, our model can be used with ECAD tools that
provide gate output rise times to determine peak crosstalk. Fig. 3
demonstrates the accuracy of the model, including the capacitance
scaling scheme, when the aggressor gate rise time is known. In
this and all subsequent cases, a distributed RC network is used in
SPICE to simulate crosstalk using 0.25 µm device and
interconnect parameters unless otherwise specified.
All
interconnect parameters used in this paper are included in table 1,
and capacitance values were determined using 3-D simulations.
V max / V dd (%)
T
H
45
SPICE simulation
Timing level model
40
40
35
35
30
30
25
25
20
20
15
15
10
10
5
5
0
100
1000
0
10000
Line Length ( µm)
Fig. 3 This plot demonstrates the model’s accuracy when the
rise time is known (Tr = 250 ps). Maximum error is about 4
percent and is due to the lumped approximations of our model.
capacitances. In the case of a 0.25 µm inverter analyzed in this
work, tr2 constitutes 31% of the total rise time at a line length of 1
mm when the input rise time is 200 ps. Inaccurate modeling of
this term, or the assumption of a step input, will result in large
errors in rise time estimation.
Finally, capacitive loading comprises the largest portion of Tr.
A modified analytical model based on [6] results in the
expressions:
V − 0.1Vdd ( Vdd − Vt ) 19Vdd − 20Vt 
Transistor-level Model

t r 3 = 1.2λC L  t
ln 
+


This section will introduce a new timing macromodel for use
2I dsat
Vdd



 I dsat

with (3) and (4) above. The rise time of a gate driving an
4
(7)
interconnect can be broken into 3 distinct parts. First is the


R a,int


intrinsic rise time of the device with no load and a step input at
λ= 1 −
(8)

R
the gate. The value of this delay is proportional to the effective
 a, int + 3 R a,dev 
resistance of the device multiplied by the capacitance at the
In these expressions, λaccounts for the shielding of capacitance
output node.
(5) by line resistance, CL is the interconnect capacitive load (Ca + Cc
t r1 = 0.5R sat Cout
in fig. 2), and the factor of 1.2 accounts for short-circuit current.
where Rsat is calculated as Vdd / Idsat. This term is small, in the Ra,int and Ra,dev refer to the aggressor line resistance and the
range of 5-10 ps for inverters, and is independent of device width aggressor device resistance. Short-circuit current is overas the geometry dependencies of Rsat and Cout cancel. For older estimated for large line lengths but does not result in large errors
technologies or large gates (e.g. 4-input NAND), this term can be in Tr. Eqn. (8) is an empirical determination of resistive shielding
and could be optimized for individual technologies. By summing
sizable.
The second component of rise time is the input waveform tr1, tr2 and tr3, a simple expression for Tr is obtained. Results are
dependency. Since the input to any gate is not an ideal step, there shown in fig. 4 for 2 different gate topologies and loading
is less drive current supplied initially due to the fact that Vgs < conditions. Overestimation at long line lengths is due to the fact
Vdd. Simulations show this input waveform dependency to be that short-circuit current is nearly negligible when CL is very
linear, both in propagation delay and rise time. Thus, the large. However, the sensitivity of Vmax to Tr is very high for short
lines but drops dramatically for long line lengths. For example, at
following expression describes this dependency well:
a line length of 300 µm, a 15% increase in Tr results in a 13%
t r 2 = k i t in
(6) drop in V for a 0.25 µm inverter. At a line length of 4 mm, a
max
Here ki is a constant for a given technology and varies between 15% change in T yields less than a 0.5% difference in V . For
r
max
0.1 and 0.2, signifying that 10 to 20% of the input transition time this reason, overestimation for large loads is tolerable to obtain
is reflected in the output delay or rise time. This term can be very higher accuracy at short line lengths.
significant, especially for slow input signals and small load
Table 1. Nominal interconnect parameters used in this study, based loosely on SIA National Technology Roadmap [7]
Technology
W=S
T
H
Resistance
Cv
Ca
Generation
(µm)
(µm)
(µm)
(Ω / µm)
aF / µm
aF / µm
0.25 µm
0.45
0.6
0.8
0.1055
46.9
82
0.32
0.55
0.7
0.1620
40.9
77.4
0.18 µm
0.23
0.45
0.6
0.2755
36.1
74.1
0.13 µm
0.17
0.4
0.55
0.4193
31.1
70.4
0.10 µm
0.12
0.35
0.5
0.6789
26.2
67.1
0.07 µm
Cc
aF / µm
78.4
93.9
104
120
141.1
Output Rise Time (ps)
700
700
600
600
500
500
400
400
sizes are varied to obtain a large range of rise times. The timing
model is used to calculate Tr in each case and the crosstalk values
are still in very good agreement with SPICE. These results are
also shown in fig. 6 and verify that both the crosstalk model and
the timing model are valid over a wide range of parameters.
Interconnect Scaling
Several technological breakthroughs in the area of on-chip
interconnections loom in the near future. Foremost among these
SPICE NAND2
200
200
are the introduction of copper for ULSI wiring, and the use of
Model NAND2
SPICE inverter
100
100
new, low-k dielectrics in place of SiO2. Copper provides the dual
Model inverter
advantages of higher electromigration resistance and lower
0
0
resistivity over aluminum-based wiring. Low-k dielectrics will
0
2000
4000
6000
8000
10000
reduce the capacitive load on gates, allowing for faster switching
Line Length ( µm)
Fig. 4 Comparison of rise times for 3-input NAND’s and inverters times and clock speeds. While both these advancements have
faced processing difficulties, both copper wiring and low-k
with results from SPICE and the model presented.
dielectrics are expected to be incorporated into 0.18 µm
45
45
processes, if not earlier. By inspection of (3), reductions in line
Analytical Model, NAND3
40
40
resistance and coupling capacitance can be seen to have direct
SPICE Simulation, NAND3
impact on noise issues. This section aims to accurately assess the
Analytical
Model,
Inverter
35
35
SPICE Simulation, Inverter
impact of new interconnect materials on crosstalk using our new
30
30
analytical models.
25
25
The interconnect parameters in table 1 are calculated within the
20
20
traditional Al/SiO2 scenario. In this study, copper wiring is
estimated to yield 40% less resistance than Al and low-k
15
15
dielectrics exhibit a relative dielectric constant of 2.5 (compared
10
10
to 4.0 for SiO2). Several different scaling scenarios are
5
5
examined:
300
V max / V dd (%)
300
0
10000
0
1)
2)
Fig. 5 Crosstalk model fit when using timing macromodel to obtain 3)
Tr. Note the NAND gate has higher crosstalk due to a larger effective
4)
100
1000
Line Length ( µm)
victim resistance (3 NMOS in series).
Victim Driver Resistance ( Ω )
V max / V dd (%)
0
50
350
50
45
45
40
40
35
35
30
30
25
25
20
20
15
50
100
150
200
250
300
15
SPICE, Inverter
Model
SPICE, 3-input NAND
Model
10
5
10
5
0
0
0
200
400
600
800
1000
Rise Time at output of gate (ps)
Fig. 6 Peak crosstalk is plotted as a function of victim driver size in a
3-input NAND gate, and as a function of aggressor rise time for an
inverter topology. Fit is within 12% for all rise times and 7% for all
driver sizes. Line length in both cases is fixed at 2.5 mm.
Fig. 5 demonstrates the fit of the crosstalk model for a 3-input
NAND and inverter when using the above timing model to obtain
Tr. Error is less than 10% for all line lengths up to 1 cm and in
most cases is less than 5%. To demonstrate the wide applicability
of this model, the victim driver size is varied by an order of
magnitude in a 3-input NAND gate (Wn = 10 to 100 µm) and the
resulting crosstalk is plotted in fig. 6. Finally, aggressor driver
5)
6)
Nominal case: Al-alloy wiring, SiO2 dielectric
Copper case: Copper wiring, SiO2 dielectric
Low-k case: Al-alloy wiring, low-k replaces SiO2
Split low-k case: Al-alloy wiring, low-k used between wires
on same level, SiO2 between levels
Low-k + Copper
Split low-k + Copper
The split low-k case is a realistic compromise between an all
low-k approach and the current SiO2 processes. Due to
processing issues, such as the lack of low-k chemical-mechanical
polishing (CMP) processes, the stacking of low-k on SiO2 may be
necessary in future technologies, especially 0.18 µm.
A critical line length, Lcrit, is defined as the line length at which
crosstalk reaches 20% of Vdd. To analyze the impact of each
scaling scenario on crosstalk, Lcrit is plotted in fig. 7, focusing on
the next 12 years of CMOS technological evolution. Cases 4 and
6 are not shown for the sake of clarity, as these scenarios result in
nearly identical Lcrit values as cases 3 and 5 respectively. As
expected, cases 5 and 6 above offer the biggest gains in terms of
Lcrit increases. It is surprising to see that the split low-k case does
not offer significant advantages over the all low-k scenario. In its
most basic form, crosstalk is modeled as a simple capacitive
divider; Vmax = Vdd * Cc / Ctot. Since split low-k dielectrics lead to
larger reductions in Cc than Ctot, it is expected that this case will
yield the largest gains in crosstalk reduction. However, at short
line lengths (L < 1 mm) total capacitance is dominated by
junction capacitances and fan-out. Therefore, the reduction in
crosstalk is directly proportional to the reduction in coupling
capacitance. For this reason, the all low-k approach yields lower
crosstalk at short line lengths but approaches the nominal case
crosstalk for long lines. This point is better illustrated in fig. 8,
which demonstrates the reduction in crosstalk in comparison to
2000
2000
eqns. (7) and (8)) and it is the first effect that dominates, leading
to lower crosstalk
Finally, fig. 9 demonstrates the effectiveness of several novel
1600
1600
approaches to crosstalk reduction. Specifically, split low-k is
1400
1400
shown to have slightly worse noise margins than an all low-k
1200
1200
approach, as discussed above. Another approach is the use of
1000
1000
“flat” wires; copper wires with aspect ratio reduced by 30 to 40%
800
800
from current projections. This will yield line resistances
600
600
comparable to aluminum wiring at the original aspect ratio but
400
400
will cut coupling capacitance by > 25%. The “flat” wiring
approach was taken by IBM in designing the first 1 GHz
200
200
microprocessor [8]. In addition, we recommend the use of
0
0
0.05
0.10
0.15
0.20
0.25
asymmetric pitches, where spacing is somewhat larger than
Technology Generation ( µm)
linewidth, in noise-critical cases. Area penalties are minimized
Fig. 7 Critical line lengths for various interconnect scenarios. This while still obtaining substantial reduction in crosstalk noise.
Nominal
Copper
All low-k
All low-k + Copper
1800
Critical Line Length (
µm)
1800
plot spans the 0.25 to 0.07 µm generations.
Conclusions
This paper introduces a new analytical crosstalk model that is
accurate, simple, and more general than those presented in the
literature. In addition, a timing model is demonstrated for use
30
30
with our crosstalk model in providing fast estimations of noise in
deep submicron technologies. All model parameters are typically
available in an EDA environment, therefore the model is ideal for
20 Split low-k ( ε = 2.5)
20
rapid crosstalk estimation and signal integrity verification. The
impact of copper wiring and low-k dielectrics on crosstalk is
investigated. It is determined that even these processing
breakthroughs will not provide adequate crosstalk reduction at
10
10
long line lengths beyond the 0.25 µm generation. Designers will
Copper
need to make tradeoffs between noise and wiring density in these
cases. Both copper and low-k dielectrics have their maximum
0
0
10
100
1000
10000
impact on crosstalk in short lines (L < 1 mm). These two
Line Length ( µm)
conclusions make repeaters an attractive alternative to the use of
Fig. 8 Crosstalk reduction due to new materials is primarily achieved long interconnects.
40
0.18 µm inverter, C fan-out small
0.25 µm NAND3, C fan-out large
40
% reduction in peak crosstalk
All low-k ( ε = 2.5)
at short line lengths. Circuits with larger loads benefit more from
new materials according to the charge-sharing principle.
30
% drop in peak crosstalk
25
30
L = 2 mm
Cu + ε = 2.5
25
20
20
15
15
10
5
10
Low-k Stack
"Flat" Wiring
Asymmetric Pitch with 1.5X Spacing
Appendix
The time constants used in eqns. (1) – (4) are defined as follows:
1
2

R (C + C c )+ R v (C v + C c )] 
[
2
τ0 =  a a


− 4 R v R a (C v C c + C v C a + C c C a )

τ1 =
[2R v R a (CvCc + C vCa + CcCa )]
[R a (Ca + Cc )+ R v (Cv + Cc )+ τ0 ]
τ2 =
[2R v R a (C vCc + C v Ca + CcCa )]
[R a (Ca + Cc )+ R v (C v + Cc )− τ0 ]
5
0
0
-5
-5
-10
(A1)
(A2)
(A3)
-10
0.10
0.15
0.20
Technology Generation ( µm)
0.25
Fig. 9 Percentage drop in peak crosstalk at L=2 mm using novel
noise avoidance techniques. “Flat” wiring becomes more beneficial
with technology scaling.
the nominal case for scenarios 2-4 above. It should be noted that
the use of copper provides some degree of crosstalk reduction at
intermediate lengths but very little for long wires or large loads.
This is due to the fact that a lower line resistance for both the
aggressor and victim ultimately has a counteracting effect, with
the victim more tightly held to ground and the aggressor
switching more quickly. At short line lengths, the aggressor
transition time has very little dependency on line resistance (see
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