CMOS VLSI Design DC Transfer Characteristics and Switch –level RC delay Models DC Response DC Response: Vout vs. Vin for a gate Ex: Inverter – When Vin = 0 -> Vout = VDD – When Vin = VDD -> Vout = 0 VDD – In between, Vout depends on Idsp transistor size and current Vin Vout – By KCL, must settle such that Idsn Idsn = |Idsp| – We could solve equations – But graphical solution gives more insight CMOS VLSI Design Slide 2 1 Transistor Operation Current depends on region of transistor behavior For what Vin and Vout are nMOS and pMOS in – Cutoff? – Linear? – Saturation? CMOS VLSI Design Slide 3 nMOS Operation Cutoff Vgsn < Linear Vgsn > Saturated Vgsn > Vdsn < Vdsn > VDD Vin Idsp Vout Idsn CMOS VLSI Design Slide 4 2 nMOS Operation Cutoff Vgsn < Vtn Linear Vgsn > Vtn Saturated Vgsn > Vtn Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn VDD Idsp Vin Vout Idsn CMOS VLSI Design Slide 5 nMOS Operation Cutoff Vgsn < Vtn Linear Vgsn > Vtn Saturated Vgsn > Vtn Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn VDD Vgsn = Vin Vdsn = Vout CMOS VLSI Design Vin Idsp Vout Idsn Slide 6 3 nMOS Operation Cutoff Vgsn < Vtn Vin < Vtn Linear Vgsn > Vtn Vin > Vtn Vdsn < Vgsn – Vtn Vout < Vin - Vtn Saturated Vgsn > Vtn Vin > Vtn Vdsn > Vgsn – Vtn Vout > Vin - Vtn VDD Vgsn = Vin Idsp Vin Vdsn = Vout Vout Idsn CMOS VLSI Design Slide 7 pMOS Operation Cutoff Vgsp > Linear Vgsp < Saturated Vgsp < Vdsp > Vdsp < VDD Vin Idsp Vout Idsn CMOS VLSI Design Slide 8 4 pMOS Operation Cutoff Vgsp > Vtp Linear Vgsp < Vtp Saturated Vgsp < Vtp Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp VDD Idsp Vin Vout Idsn CMOS VLSI Design Slide 9 pMOS Operation Cutoff Vgsp > Vtp Linear Vgsp < Vtp Saturated Vgsp < Vtp Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp VDD Vgsp = Vin - VDD Vdsp = Vout - VDD CMOS VLSI Design Vtp < 0 Vin Idsp Vout Idsn Slide 10 5 pMOS Operation Cutoff Vgsp > Vtp Vin > VDD + Vtp Linear Vgsp < Vtp Vin < VDD + Vtp Vdsp > Vgsp – Vtp Vout > Vin - Vtp Saturated Vgsp < Vtp Vin < VDD + Vtp Vdsp < Vgsp – Vtp Vout < Vin - Vtp VDD Vgsp = Vin - VDD Vtp < 0 Idsp Vin Vdsp = Vout - VDD Vout Idsn CMOS VLSI Design Slide 11 I-V Characteristics Make pMOS is wider than nMOS such that βn = βp Vgsn5 Vgsn4 Idsn Vgsn3 -Vdsp Vgsp1 Vgsp2 -VDD 0 VDD Vdsn Vgsp3 Vgsp4 Vgsn2 Vgsn1 -Idsp Vgsp5 CMOS VLSI Design Slide 12 6 Current vs. Vout, Vin plot absolute value of pMOS CMOS VLSI Design Slide 13 Load Line Analysis For a given Vin: – Plot Idsn, Idsp vs. Vout – Vout must be where |currents| are equal in Idsn, |Idsp| Vin0 Vin5 Vin1 Vin4 Vin2 Vin3 Vin3 Vin4 Vin2 Vin1 Vout CMOS VLSI Design VDD Vin Idsp Vout Idsn VDD Slide 14 7 Load Line Analysis Vin = 0 Vin0 Idsn, |Idsp| Vin0 Vout VDD CMOS VLSI Design Slide 15 Load Line Analysis Vin = 0.2VDD Idsn, |Idsp| Vin1 Vin1 Vout CMOS VLSI Design VDD Slide 16 8 Load Line Analysis Vin = 0.4VDD Idsn, |Idsp| Vin2 Vin2 Vout VDD CMOS VLSI Design Slide 17 Load Line Analysis Vin = 0.6VDD Idsn, |Idsp| Vin3 Vin3 Vout CMOS VLSI Design VDD Slide 18 9 Load Line Analysis Vin = 0.8VDD Vin4 Idsn, |Idsp| Vin4 Vout VDD CMOS VLSI Design Slide 19 Load Line Analysis Vin = VDD Vin0 Idsn, |Idsp| Vin5 Vin1 Vin2 Vin3 Vin4 Vout CMOS VLSI Design VDD Slide 20 10 Load Line Summary Idsn, |Idsp| Vin0 Vin5 Vin1 Vin4 Vin2 Vin3 Vin3 Vin4 Vin2 Vin1 VDD Vout CMOS VLSI Design Slide 21 DC Transfer Curve Transcribe points onto Vin vs. Vout plot Vin0 Vin5 Vin1 Vin4 Vin2 Vin3 Vin3 Vin4 Vin2 Vin1 Vout CMOS VLSI Design VDD VDD A B Vout C D 0 Vtn VDD/2 E VDD+Vtp VDD Vin Slide 22 11 Operating Regions Revisit transistor operating regions Region nMOS pMOS VDD A A B Vout B C C D D 0 E Vtn VDD/2 E VDD+Vtp VDD Vin CMOS VLSI Design Slide 23 Operating Regions Revisit transistor operating regions Region nMOS pMOS A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff VDD A B Vout C D 0 Vtn VDD/2 E VDD+Vtp VDD Vin CMOS VLSI Design Slide 24 12 Beta Ratio If βp / βn ≠ 1, switching point will move from VDD/2 If βp / βn < 1, the inverter is LO-skewed If βp / βn > 1, the inverter is HI-skewed VDD βp = 10 βn Vout 2 1 0.5 βp = 0.1 βn 0 Vin VDD CMOS VLSI Design Slide 25 Noise Margins How much noise can a gate input see before it does not recognize the input? NMH= VOH-VIH Output Characteristics Logical High Output Range VDD Input Characteristics VIL Logical Low Output Range Logical High Input Range VOH NMH VIH NML VOL NML = VIL - VOL Indeterminate Region Logical Low Input Range GND CMOS VLSI Design Slide 26 13 Logic Levels To maximize noise margins, select logic levels at Vout VDD βp/β n > 1 Vin Vout Vin 0 VDD CMOS VLSI Design Slide 27 Logic Levels To maximize noise margins, select logic levels at – unity gain point of DC transfer characteristic Vout Unity Gain Points Slope = -1 VDD VOH βp/β n > 1 Vin VOL Vin 0 Vtn CMOS VLSI Design Vout VIL VIH VDD- VDD |Vtp| Slide 28 14 Pass Transistors We have assumed source is grounded What if source > 0? VDD – e.g. pass transistor passing VDD VDD CMOS VLSI Design Slide 29 Pass Transistors We have assumed source is grounded What if source > 0? VDD – e.g. pass transistor passing VDD VDD Vg = VDD – If Vs > VDD-Vt, Vgs < Vt – Hence transistor would turn itself off nMOS pass transistors pull no higher than VDD-Vtn – Called a degraded “1” – Approach degraded value slowly (low Ids) pMOS pass transistors pull no lower than Vtp CMOS VLSI Design Slide 30 15 Pass Transistor Ckts VDD VDD VDD VDD VDD VDD VDD VDD VSS CMOS VLSI Design Slide 31 Pass Transistor Ckts VDD VDD VDD VDD VDD VDD Vs = VDD-Vtn Vs = |Vtp| VDD-Vtn VDD-Vtn VDD VDD-Vtn VDD-Vtn VDD VDD-2Vtn VSS CMOS VLSI Design Slide 32 16 CMOS VLSI Design Slide 33 Tristate Inverter Why (d) is a bad design? If EN = 0, Y is supposed to be float, but if A changes, charge at internal node may disturb node Y. more in section 6.3.4) CMOS VLSI Design Slide 34 17 Effective Resistance Shockley models have limited value – Not accurate enough for modern transistors – Too complicated for much hand analysis Simplification: treat transistor as resistor – Replace Ids(Vds, Vgs) with effective resistance R • Ids = Vds/R – R averaged across switching of digital gate Too inaccurate to predict current at any given time – But good enough to predict RC delay CMOS VLSI Design Slide 35 CMOS VLSI Design Slide 36 18 RC Delay Model Use equivalent circuits for MOS transistors – Ideal switch + capacitance and ON resistance – Unit nMOS has resistance R, capacitance C – Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width d g d k s s kC kC R/k 2R/k g g kC kC d k s s CMOS VLSI Design kC g kC d Slide 37 A nMOS transistor of unit size: minimum length and minimum contacted diffusion width, size = 1 means that W = 4 λ, L = 2 λ, W/L = 2 A nMOS transistor size = k, W/L = 2k CMOS VLSI Design Slide 38 19 Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C CMOS VLSI Design Slide 39 RC Values Capacitance – C = Cg = Cs = Cd = 2 fF/μm of gate width – Values similar across many processes Resistance – R ≈ 6 KΩ*μm in 0.6um process – Improves with shorter channel lengths Unit transistors – May refer to minimum contacted device (4/2 λ) – Or maybe 1 μm wide device – Doesn’t matter as long as you are consistent CMOS VLSI Design Slide 40 20 Inverter Delay Estimate Estimate the delay of a fanout-of-1 inverter A 2 Y 2 1 1 CMOS VLSI Design Slide 41 Inverter Delay Estimate Estimate the delay of a fanout-of-1 inverter 2C R A 2 Y 2 1 1 2C 2C Y R C C C CMOS VLSI Design Slide 42 21 Inverter Delay Estimate Estimate the delay of a fanout-of-1 inverter 2C R A 2 Y 2 1 1 2C 2C 2C 2C Y R C R C C C C CMOS VLSI Design Slide 43 Inverter Delay Estimate Estimate the delay of a fanout-of-1 inverter 2C R A 2 Y 2 1 1 2C 2C 2C 2C Y R C R C C C C d = 6RC CMOS VLSI Design Slide 44 22