Features
• Low-Voltage and Standard-Voltage Operation
•
•
•
•
•
•
•
•
•
•
•
•
•
•
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
Low-Power Devices (ISB = 6 µA @ 5.5V) Available
Internally Organized 4096 x 8, 8192 x 8
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
400 kHz (1.8V, 2.5V, 2.7V, 5V) Compatibility
Write Protect Pin for Hardware Data Protection
32-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms Max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Automotive Devices Available
8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead Mini-MAP (MLP 2x3)
and 8-lead TSSOP Packages
Lead-free/Halogen-free
Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The AT24C32A/64A provides 32,768/65,536 bits of serial electrically erasable and
programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits
each. The device’s cascadable feature allows up to 8 devices to share a common twowire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C32A/64A is
available in space saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ
SOIC, 8-lead Mini-MAP (MLP 2x3) and 8-lead TSSOP packages and is accessed via
a 2-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V)
and 1.8V (1.8V to 5.5V) versions.
Two-wire
Serial EEPROM
32K (4096 x 8)
64K (8192 x 8)
AT24C32A(1)
AT24C64A(2)
Notes: 1. Not recommended for
new design; please
refer to AT24C32C.
2. Not recommended for
new design; please
refer to AT24C64C.
Table 1. Pin Configuration
Pin Name
Function
A0 – A2
Address Inputs
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
8-lead SOIC
A0
A1
A2
GND
1
2
3
4
8
7
6
5
8-lead Mini-MAP (MLP 2x3)
VCC
WP
SCL
SDA
8
7
6
5
VCC
WP
SCL
SDA
1
2
3
4
A0
A1
A2
GND
Bottom View
8-lead PDIP
8-lead TSSOP
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
3054T–SEEPR–1/07
1
Absolute Maximum Ratings*
Operating Temperature..................................–55°C to +125°C
Storage Temperature .....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................... –1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Figure 1. Block Diagram
2
AT24C32A/64A
3054T–SEEPR–1/07
AT24C32A/64A
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs
that are hardwired or left not connected for hardware compatibility with other AT24Cxx
devices. When the pins are hardwired, as many as eight 32K/64K devices may be
addressed on a single bus system (device addressing is discussed in detail under the
Device Addressing section). If the pins are left floating, the A2, A1 and A0 pins will be
internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is
<3 pF. If coupling is >3 pF, Atmel recommends connecting the address pins to GND.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected high to VCC, all write operations to the
memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down
to GND if the capacitive coupling to the circuit board VCC plane is <3 pF. If coupling is
>3 pF, Atmel recommends connecting the pin to GND. Switching WP to VCC prior to a
write operation creates a software write protect function.
Memory Organization
AT24C32A/64A, 32K/64K SERIAL EEPROM: The 32K/64K is internally organized as
128/256 pages of 32 bytes each. Random word addressing requires a 12/13-bit data
word address.
3
3054T–SEEPR–1/07
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V
Symbol
Test Condition
CI/O
CIN
Note:
Max
Units
Conditions
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
Input Capacitance (A0, A1, A2, SCL)
6
pF
VIN = 0V
1. This parameter is characterized and is not 100% tested.
Table 3. DC Characteristics
Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, VCC = +1.8V to +5.5V
(unless otherwise noted)
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Max
Units
1.8
5.5
V
Supply Voltage
2.5
5.5
V
VCC3
Supply Voltage
2.7
5.5
V
VCC4
Supply Voltage
4.5
5.5
V
ICC1
Supply Current
VCC = 5.0V
READ at 400 kHz
0.4
1.0
mA
ICC2
Supply Current
VCC = 5.0V
WRITE at 400 kHz
2.0
3.0
mA
ISB1
Standby Current
(1.8V option)
VCC = 1.8V
VIN = VCC or VSS
1.0
µA
ISB2
Standby Current
(2.5V option)
VCC = 2.5V
VIN = VCC or VSS
2.0
µA
ISB3
Standby Current
(2.7V option)
VCC = 2.7V
VIN = VCC or VSS
2.0
µA
ISB4
Standby Current
(5V option)
VCC = 4.5 - 5.5V
VIN = VCC or VSS
6.0
µA
ILI
Input Leakage
Current
VIN = VCC or VSS
0.10
3.0
µA
ILO
Output Leakage
Current
VOUT = VCC or VSS
0.05
3.0
µA
VIL(1)
VIH
(1)
Test Condition
Min
Typ
Input Low Level
–0.6
VCC x 0.3
V
Input High Level
VCC x 0.7
VCC + 0.5
V
VOL2
Output Low Level
VCC = 3.0V
IOL = 2.1 mA
0.4
V
VOL1
Output Low Level
VCC = 1.8V
IOL = 0.15 mA
0.2
V
Note:
4
1. VIL min and VIH max are reference only and are not tested.
AT24C32A/64A
3054T–SEEPR–1/07
AT24C32A/64A
Table 4. AC Characteristics
Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
1.8, 2.5, 2.7, 5.0-volt
Symbol
Parameter
fSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
tHIGH
Clock Pulse Width High
Min
Max
Units
400
kHz
1.2
µs
0.6
µs
(1)
tI
Noise Suppression Time
tAA
Clock Low to Data Out Valid
0.1
tBUF
Time the bus must be free
before a new transmission
can start(1)
1.2
µs
tHD.STA
Start Hold Time
0.6
µs
tSU.STA
Start Set-up Time
0.6
µs
tHD.DAT
Data In Hold Time
0
µs
tSU.DAT
Data In Set-up Time
100
ns
(1)
50
ns
0.9
µs
tR
Inputs Rise Time
0.3
µs
tF
Inputs Fall Time(1)
300
ns
tSU.STO
Stop Setup Time
0.6
µs
tDH
Data Out Hold Time
50
ns
tWR
Write Cycle Time
Endurance(1)
5.0V, 25°C, Page Mode
Note:
5
1M
ms
Write Cycles
1. This parameter is ensured by characterization only.
5
3054T–SEEPR–1/07
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C32A/64A features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the stop bit and the completion of
any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any
two-wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
6
AT24C32A/64A
3054T–SEEPR–1/07
AT24C32A/64A
Figure 2. Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Figure 3. Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT
ACK
WORDn
(1)
twr
STOP
CONDITION
Note:
START
CONDITION
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 4. Data Validity
7
3054T–SEEPR–1/07
Figure 5. Start and Stop Definition
Figure 6. Output Acknowledge
8
AT24C32A/64A
3054T–SEEPR–1/07
AT24C32A/64A
Device Addressing
The 32K/64K EEPROM requires an 8-bit device address word following a start condition
to enable the chip for a read or write operation (see Figure 7 on page 11). The device
address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all 2-wire EEPROM devices.
The 32K/64K uses the three device address bits A2, A1, A0 to allow as many as eight
devices on the same bus. These bits must compare to their corresponding hardwired
input pins. The A2, A1, and A0 pins use an internal proprietary circuit that biases them
to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is
not made, the device will return to standby state.
NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins prevent small noise spikes from activating the device.
DATA SECURITY: The AT24C32A/64A has a hardware data protection scheme that
allows the user to write protect the entire memory when the WP pin is at VCC.
Write Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8-bit data word. Following
receipt of the 8-bit data word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, t WR , to the
nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will
not respond until the write is complete (see Figure 8 on page 11).
PAGE WRITE: The 32K/64K EEPROM is capable of 32-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not
send a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to 31
more data words. The EEPROM will respond with a zero after each data word received.
The microcontroller must terminate the page write sequence with a stop condition (see
Figure 9 on page 11).
The data word address lower five bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than 32 data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero, allowing the read or write sequence to continue.
9
3054T–SEEPR–1/07
Read Operations
Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to one. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address “roll over” during read is from the last byte of the last memory page, to the first
byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page.
Once the device address with the read/write select bit set to one is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input zero but does generate a following
stop condition (see Figure 10 on page 11).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a zero but does generate a following stop condition (see Figure 11 on page 12).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the
microcontroller does not respond with a zero but does generate a following stop condition (see Figure 12 on page 12).
10
AT24C32A/64A
3054T–SEEPR–1/07
AT24C32A/64A
Figure 7. Device Address
Figure 8. Byte Write
Figure 9. Page Write
Notes:
1. * = DON’T CARE bits
2. † = DON’T CARE bits for the 32K
Figure 10. Current Address Read
11
3054T–SEEPR–1/07
Figure 11. Random Read
Note:
1. * = DON’T CARE bits
Figure 12. Sequential Read
12
AT24C32A/64A
3054T–SEEPR–1/07
AT24C32A/64A
AT24C32A Ordering Information(1)
Ordering Code
Package
AT24C32A-10PU-2.7(2)
AT24C32A-10PU-1.8(2)
AT24C32AN-10SU-2.7(2)
AT24C32AN-10SU-1.8(2)
AT24C32AW-10SU-2.7(2)
AT24C32AW-10SU-1.8(2)
AT24C32A-10TU-2.7(2)
AT24C32A-10TU-1.8(2)
AT24C32AY1-10YU-1.8(2) (Not recommended for new design)
AT24C32AY6-10YH-1.8(3)
8P3
8P3
8S1
8S1
8S2
8S2
8A2
8A2
8Y1
8Y6
AT24C32A-W1.8-11(4)
Die Sale
Notes:
Operation Range
Lead-free/Halogen-free/
Industrial Temperature
(–40°C to 85°C)
Industrial Temperature
(–40°C to 85°C)
1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics
tables.
2. “U” designates Green Package + RoHS compliant.
3. “H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish.
4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial EEPROM Marketing.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8S2
8-lead, 0.209" Body, Plastic Small Outline (EIAJ SOIC)
8A2
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8Y1
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8Y6
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3
mm)
Options
–2.7
Low Voltage (2.7V to 5.5V)
–1.8
Low Voltage (1.8V to 5.5V)
13
3054T–SEEPR–1/07
AT24C64A Ordering Information(1)
Ordering Code
Package
AT24C64A-10PU-2.7(2)
AT24C64A-10PU-1.8(2)
AT24C64AN-10SU-2.7(2)
AT24C64AN-10SU-1.8(2)
AT24C64AW-10SU-2.7(2)
AT24C64AW-10SU-1.8(2)
AT24C64A-10TU-2.7(2)
AT24C64A-10TU-1.8(2)
AT24C64AY1-10YU-1.8(2) (Not recommended for new design)
AT24C64AY6-10YH-1.8(3)
8P3
8P3
8S1
8S1
8S2
8S2
8A2
8A2
8Y1
8Y6
AT24C64A-W1.8-11(4)
Die Sale
Notes:
Operation Range
Lead-free/Halogen-free/
Industrial Temperature
(–40°C to 85°C)
Industrial Temperature
(–40°C to 85°C)
1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics
tables.
2. “U” designates Green Package + RoHS compliant.
3. “H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish.
4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial EEPROM Marketing.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8S2
8-lead, 0.209" Body, Plastic Small Outline (EIAJ SOIC)
8A2
8-lead, 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8Y1
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8Y6
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN)
Options
–2.7
Low Voltage (2.7V to 5.5V)
–1.8
Low Voltage (1.8V to 5.5V)
14
AT24C32A/64A
3054T–SEEPR–1/07
AT24C32A/64A
Package Drawings
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
b2
b3
b
4 PLCS
Side View
L
SYMBOL
NOM
MAX
NOTE
2
A
–
–
0.210
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
3
D1
0.005
–
–
3
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
e
0.100 BSC
eA
0.300 BSC
L
Notes:
MIN
0.115
0.130
4
0.150
2
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
15
3054T–SEEPR–1/07
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
Side View
SYMBOL
MIN
NOM
MAX
A
1.35
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.00
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
∅
0˚
–
8˚
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
R
16
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
8S1
REV.
B
AT24C32A/64A
3054T–SEEPR–1/07
AT24C32A/64A
8S2 – EIAJ SOIC
C
1
E
E1
L
N
Top View
∅
End View
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
A1
D
Side View
NOM
MAX
NOTE
A
1.70
2.16
A1
0.05
0.25
b
0.35
0.48
5
C
0.15
0.35
5
D
5.13
5.35
E1
5.18
5.40
E
7.70
8.26
L
0.51
0.85
∅
0°
8°
e
Notes: 1.
2.
3.
4.
5.
MIN
1.27 BSC
2, 3
4
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
Mismatch of the upper and lower dies and resin burrs are not included.
It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
Determines the true geometric position.
Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.
10/7/03
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
DRAWING NO.
8S2
REV.
C
17
3054T–SEEPR–1/07
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
b
D
MIN
NOM
MAX
NOTE
2.90
3.00
3.10
2, 5
3, 5
E
e
A2
D
6.40 BSC
E1
4.30
4.40
4.50
A
–
–
1.20
A2
0.80
1.00
1.05
b
0.19
–
0.30
e
Side View
L
0.65 BSC
0.45
L1
Notes:
0.60
0.75
1.00 REF
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
R
18
4
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
8A2
REV.
B
AT24C32A/64A
3054T–SEEPR–1/07
AT24C32A/64A
8Y1 – MAP
PIN 1 INDEX AREA
A
1
3
2
4
PIN 1 INDEX AREA
E1
D1
D
L
8
Bottom View
COMMON DIMENSIONS
(Unit of Measure = mm)
A
Side View
5
e
End View
Top View
6
b
A1
E
7
SYMBOL
MIN
NOM
MAX
A
–
–
0.90
A1
0.00
–
0.05
D
4.70
4.90
5.10
E
2.80
3.00
3.20
D1
0.85
1.00
1.15
E1
0.85
1.00
1.15
b
0.25
0.30
0.35
e
L
NOTE
0.65 TYP
0.50
0.60
0.70
2/28/03
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
(MAP) Y1
DRAWING NO.
REV.
8Y1
C
19
3054T–SEEPR–1/07
8Y6 - MAP
D2
A
b
(8X)
E
E2
Pin 1
Index
Area
Pin 1 ID
L (8X)
D
A2
e (6X)
A1
1.50 REF.
A3
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
D
E
D2
MAX
1.50
1.60
E2
-
-
1.40
A
-
-
0.60
A1
0.0
0.02
0.05
A2
-
-
0.55
L
0.20 REF
0.20
e
b
NOTE
3.00 BSC
1.40
A3
Notes:
NOM
2.00 BSC
0.30
0.40
0.50 BSC
0.20
0.25
0.30
2
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
8/26/05
R
20
2325 Orchard Parkway
San Jose, CA 95131
DRAWING NO.
TITLE
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,
8Y6
Dual No Lead Package (DFN), (MLP 2x3)
REV.
C
AT24C32A/64A
3054T–SEEPR–1/07
AT24C32A/64A
Revision History
Doc. Rev.
Date
Comments
3054T
1/2007
Implemented revision history.
Added Notes to Page 1 recommending new devices.
21
3054T–SEEPR–1/07
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3054T–SEEPR–1/07