Vol. 36, No. 1
Journal of Semiconductors
January 2015
A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless
communications
Zhao Yuanxin(赵远新), Gao Yuanpei(高源培), Li Wei(李巍)Ž , Li Ning(李宁),
and Ren Junyan(任俊彦)
State Key Laboratory of ASIC & System, Fudan University, Shanghai 201203, China
Abstract: A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications
is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.
Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is
as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the “pulse-swallowing” phenomenon so as to
significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the
loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary.
The measurement results show that the output frequency range of this frequency synthesizer is 0.8–4.2 GHz. The
locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances
have reached –100 dBc/Hz, and –125 dBc/Hz respectively. The lowest reference spur is –58 dBc.
Key words: fractional-N frequency synthesizer; all-digital phase-locked loop; phase noise; reference spur; CMOS
DOI: 10.1088/1674-4926/36/1/015001
EEACC: 2570
1. Introduction
Not long ago, all high-performance PLLs were based
on a charge-pump architecture, but when the semiconductor progress went into submicron CMOS, traditional analog
PLL faced many problems. To solve these problems, all digital phase-locked loops (ADPLL) have recently emerged as
an attractive alternative to the analog PLLŒ1 . The digital nature of ADPLL adds flexibility, reconfigurability and transferfunction precision to the loop, which exactly meets the diverse and strict requirements of advanced communication systemsŒ2 . Nowadays, ADPLL is used in the production of a large
world-wide fraction of new mobile phones.
With the rapid development of communication technology, various wireless communication based devices come into
our daily lives. In order to continuously improve the data
transfer rate and spectrum efficiency, more and more wireless communication protocols are proposed such as a global
system for mobile (GSM), the 1800 MHz digital cellular
system (DCS1800), wideband code division multiple access
(WCDMA), time division synchronous code division multiple access (TD-SCDMA), Bluetooth, and IEEE 802.11a/b/g. In
these wireless communication systems of different communication protocols, the frequency synthesizer is one of the key
modules, providing the local oscillator clock source for the
transceivers. In modern wireless communication systems, the
device supports more than one communication protocol and
it usually has a multi-mode operation state. Different communication protocols have different requirements in the performance of the frequency synthesizer, therefore, design of a
multi-mode frequency synthesizer, which can support multiple communication protocols, is extremely important for the
promotion of wireless communication systems. With the trend
of analog/RF circuits realized digitally, the research on multimode ADPLL frequency synthesizer architecture will have important practical significance.
In this paper, an ADPLL based frequency synthesizer for
cellular and short range multi-standard wireless receiver is realized as a step toward software-defined radio (SDR). Finally this
single-chip is fabricated in a TSMC 0.13 m CMOS process,
and its specifications such as phase noise, spur, settling time,
output frequency range, and resolution can fulfill the communication standards of GSM900, DCS1800, GPS, WCDMA, TDSCDMA, Bluetooth, 802.11b/g and DVB-S.
A series of novel methods are proposed in this paper. Two
band DCOs with high frequency resolution are proposed to
cover the frequency band of interest, which is as wide as 2.5
to 5 GHz. To fulfill the locking time requirement of these communication standards, we present an overflow counter to prevent the phenomenon of “pulse-swallowing” and to reduce the
locking time; consequently, the measurement result has proven
its effectiveness. In this paper, a NTW-clamp digital module is
also proposed to prevent the overflow of the loop control word.
The widely used programmable dividerŒ3 is not suitable for
the fractional-N programmable divider in this frequency synthesizer, so a modification is made to improve the operation at
the boundary of the division ratio in the fractional mode. With
the help of the improved division-ratio-variable integer divider,
this ADPLL architecture prevents the failure operation of the
programmable divider at the boundary, which often occurs in
the conventional architecture.
2. Architecture design
There are currently two types of ADPLL architectures
* Project supported by the National Natural Science Foundation of China (No. 61176029) and the National Twelve-Five Project (No. 513***).
† Corresponding author. Email: w-li@fudan.edu.cn
Received 23 June 2014, revised manuscript received 22 July 2014
© 2015 Chinese Institute of Electronics
015001-1
J. Semicond. 2015, 36(1)
Zhao Yuanxin et al.
Figure 1. The conventional fractional-N ADPLL block diagram with
feedback divider.
that are widely used for high performance fractional frequency synthesis: divider-in-loop architecture and divider-less
architectureŒ4; 5 . Figure 1 shows the divider-in-loop architecture ADPLL, which mirrors a traditional PLL component-forcomponent.
It consists of a time-to-digital converter (TDC), a digital
loop filter (DLF), a digitally controlled oscillator (DCO), and
a feedback divider. The TDC senses the phase difference between the reference clock and the DCO divided clock and converts it to a digital format. This result is then filtered by the DLF
and is used to control the DCO. As for a fractional-N PLL, a
multi-modulus divider which is driven by a † modulator is
also needed. In this architecture, the DLF or some other digital
modules with different loop control techniques are considered
as the brain of the PLL; with the innovation of these control
techniques, there can be more and more PLLs with different
kinds of improved specifications and applications.
Our frequency synthesizer is designed for zero-IF receiver
fitting for standards of GSM900, DCS1800, GPS, WCDMA,
TD-SCDMA, Bluetooth, 802.11b/g and DVB-S, which means
a wide frequency range covering 0.8 to 4.2 GHz is necessary.
The general architecture of the proposed ADPLL frequency
synthesizer in this paper is shown in Figure 2. We adopt two
different DCOs to cover a frequency range from 2.5 to 5 GHz
(high-band DCO covers from 2.5 to 3.7 GHz, low-band DCO
covers from 3.5 to 5 GHz) and then get the desired frequency
range from 0.8 to 4.2 GHz with the help of a divider-by-two
chain. Table 1 shows the output ways of different communication standards.
A higher resolution and higher reference clock frequency
result in a lower in-band phase noise. A 40 MHz clock is
used as the reference signal. When applied in our Type-II ADPLL, the TDC’s input time interval can be as large as nearly
25 ns. Due to the good performance of the gated ring oscillator
(GRO), such as a very large detectable rangeŒ6 and a higher effective resolution due to its noise shaping character, the GRO
TDC is applied in this paper to meet the requirement of the
detectable range and to get a lower in-band phase noise.
However, the GRO-structure TDC proposed in Reference
[6] results in the phenomenon of “pulse-swallowing”, which
greatly affects the locking of the ADPLL loop. In this paper,
an “overflow counter” module is proposed to solve this problem and to achieve a shorter locking time of the ADPLL loop.
The design of a high performance DCO is also important in this
architecture, and the DCO designs in this proposed ADPLL architecture have been published in References [7, 8]. When the
digital data is filtered by the DLF, the result has the overflow
risk. In order to prevent this risk, a “NTW-clamp” digital module is adopted and it improves the robustness of our proposed
design. The reference signal is produced by an off-chip crystal
oscillator at 40 MHz.
In order to analyze theoretically the phase noise performance of this ADPLL structure, this paper adopts a noise modeling method to realize the modeling of this ADPLL architecture according to Reference [1]. As is shown in Figure 3, the
noise sources of this ADPLL architecture include: the quantization noise of the TDC, the quantization noise of the DCO,
the † quantization noise of the DCO, the internal noise of the
DCO, and the † quantization noise of the divider. Because
of the digital nature of the digital algorithm module, it does not
introduce any noise to the loop.
The characteristics of the total noise power spectrum are
the combination of all these noise sources through the transfer
function of the loop.
Power spectrum of the various noise sources and their
transfer functions are summarized as follows (detailed analysis
is shown in Reference [1]):
Noise power spectrum of the TDC quantization noise:
2
Stdc
.f / D
2
.2/2 tres
;
12TR
(1)
where tres is the TDC effective resolution. TR is the cycle of
the reference clock.
Noise power spectrum of the DCO quantization noise:
2
Sdco-qua
.f
2
fres
/D
12fR
f
sinc
fR
2
;
(2)
where fR is the reference clock frequency, and fres is the minimum frequency resolution of DCO.
The total output of the quantization noise DCO noise:
A2dco-sdm .f
1
/D
12
fres
f
2
1
fdth
f
2 sin
fdth
6
;
(3)
where fdth is the clock frequency of † modulation of DCO.
The internal noise of the DCO and the reference noise of
the clock can be obtained from the testing results.
Noise power spectrum of the divider † quantization
noise:
.2/2
f 4 1
2
Sdiv-sdm .f / D
2 sin
:
(4)
12fdth
fdth
N2
The transfer function of the reference clock and the TDC
quantization noise are the same as:
Htdc D
NHol
;
1 C Hol
(5)
where Hol is the open-loop transfer function of the ADPLL
loop.
The transfer function of the DCO internal noise:
015001-2
Hdco-ini D
1
:
1 C Hol
(6)
J. Semicond. 2015, 36(1)
Zhao Yuanxin et al.
Figure 2. The proposed ADPLL based frequency synthesizer for wireless communications.
Figure 3. The modeling of this ADPLL architecture.
Standard
GSM900
GPS
DCS1800
WCDMA
TD-SCDMA
Bluetooth
802.11b/g
DVB-S
Table 1. Output ways of different communication standards.
Frequency range (MHz) Channel spacing (MHz) Output select
890–915 (Tx)
0.2
fout/8
935–960 (Rx)
fout/4
1575.42
2
fout/4
1710–1785 (Tx)
0.2
fout/4
1805–1875 (Rx)
fout/2
1920–1980 (Tx)
5
fout/2
1805–1875 (Rx)
1880–1920 (TRx)
1.6
fout/2
2010–2025 (TRx)
2400–2483.5
1
fout/2
2400–2483.5
25
fout/2
3700–4200
—
fout
The transfer function of the DCO quantization noise and
the DCO † quantization noise:
Hdco-qua
2
s
D
:
1 C Hol
The transfer function of the divider † quantization noise:
Hdiv-sdm D
(7)
015001-3
NHol
:
1 C Hol
The total output phase noise of the loop:
(8)
J. Semicond. 2015, 36(1)
Zhao Yuanxin et al.
Figure 4. GRO TDC structure.
2
2
2
Ltotal D 10 lgŒStdc
.f / mod.Htdc
/ C Sdco-qua
.f /
2
mod.Hdco-qua
/ C A2dco-sdm .f /
2
2
2
C Sdco-ini
.f / mod.Hdco-ini
/ C Sdiv-sdm
.f /
2
mod.Hdiv-sdm
/:
(9)
With this phase noise modeling method of the ADPLL
architecture, the phase noise performance of the loop can be
predicted in theory. In the section “measurement result”, the
testing result of the phase noise performance will be compared
with the result of this modeling method.
Figure 5. The 11-stages GRO structure.
3. Circuit implementation
In this section, we mainly investigate some key modules
in the proposed ADPLL frequency synthesizer.
3.1. Time-to-digital converter (TDC)
The structure of GRO TDC is shown in Figure 4. It is composed of a phase & frequency detector (PFD), an 11-stages
GRO, a multi-phase counter and evaluation logic.
The PFD senses the delay between REF and CKV, and
generates START as the GRO’s enable pulse and STOP as the
TDC’s reset pulse. The 11-stages GRO quantizes the phase error between START and STOP. The multi-phase counter reads
out the quantized delay of GRO. The outputs of the multi-phase
counter and PFD are converted to a 16-bit binary code by the
evaluation logic.
(1) Gated ring oscillator
The GRO structure is shown in Figure 5. It is composed
of 11 gated inverters. When the voltage level of START is
high, the GRO starts to oscillate, and the counting value accumulates. When STOP is high, the GRO is frozen by a falling
START.
As shown in Figure 6, between TDC’s measurement of input time interval, the GRO’s internal state is kept. When the
GRO is enabled in the next measurement, it picks up the kept
state where it left off. Thus the quantization error of the previous measurement is related to the quantization error of the
current measurement. The overall quantization error is:
eŒk D qŒk
qŒk
1:
(10)
Figure 6. Quantization error of GRO.
The 1st-order noise shaping is achieved with the GRO
structure by the 1st-order difference operation indicated by
Equation (10).
(2) Phase & frequency detector
The GRO’s quantization mechanism requires that START
always leads STOP. However, it is not possible to guarantee
that REF always leads CKV, since the CKV frequency and
phase are adjusted dynamically in PLL. The PFD shown in
Figure 7 uses a SR-latch as an arbiter, which generates a sign
signal controlling the two multiplexers to ensure that START
always leads STOP. The structure of the arbiter is shown in
Figure 8, where the sign also indicates a positive or negative
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Zhao Yuanxin et al.
Figure 8. Structure of the arbiter.
Figure 7. Structure of the phase-frequency detector.
Figure 9. Multi-phase counter structure.
Figure 10. Structure of the asynchronous reset TSPCR.
phase errorŒ9 .
(3) Multi-phase counter
The multi-phase counter counts the number of rising edges
generated by the GRO. It is composed of six single-pulse generators and six binary adder counters, as shown in Figure 9.
Each GRO stage generates a counting clock for the multi-phase
counter through a single-pulse generator.
Each time the TDC finishes a measurement, the multiphase counter should be reset. An asynchronous reset truesingle-phase-clock register (TSPCR) is designed to build the
binary adder counters in the multi-phase counter. The structure of the asynchronous reset TSPCR is shown in Figure 10.
When the voltage level of RST is high, node A is discharged
by NMOS M2, the asynchronous reset TSPCR’s output Q becomes “0”; when RST is low, the asynchronous reset TSPCR
works like a traditional TSPCR.
(4) Overflow counter
Figure 11 shows the phenomenon of “pulse-swallowing”
in the GRO-based TDC proposed in Reference [6]. When TDC
is comparing the phase error between two edges, there is an
operating mode signal generating a pulse until the comparing
operation is over. If a new rise-edge (it can belong to REF or
CKV) arrives before this operating mode pulse vanishes, the
TDC will miss this rise-edge, and the output phase error of this
TDC will vary a value of 2 pi from the right value. Besides,
the output phase error of TDC will not exceed 2 pi because
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Zhao Yuanxin et al.
single-pole IIR filter can be described in the time domain as:
yŒk D .1
/yŒk
1 C xŒk;
(11)
where xŒk is the input of number k, and yŒk is the output of
number k.
The transfer function of the single-pole IIR filter can be
described in the frequency domain as:
Figure 11. “Pulse-swallowing” phenomenon in GRO-based TDC.
H.s/ D
1 C s=fR
;
1 C s=fR
(12)
of pulse-swallowing, resulting in a limited measured range of
TDC, which means a longer locking time.
To solve this problem, we propose an “overflow counter”,
which is depicted in Figure 12. It consists of a “PFD-based detector” and a “mode-N counter”. The first stage of the “overflow counter” is called the “PFD-based detector”, which has
a similar circuit structure as the PFD in analog PLL. It detects the rise-edge of REF or CKV when the operating mode
pulse is active. If there is a rise-edge when the TDC is in calculating mode, TDC will ignore a pulse (pulse-swallowing) and
the “PFD-based detector” will generate a pulse indicating the
pulse-swallowing operation is happening. This pulse signal is
then put into a “mode-N counter”, which is the second stage
of the overflow counter. With the help of the mode-N counter,
how many rise-edges the TDC has swallowed will be counted.
The output of TDC, combined with the result of the overflow
counter, is then sent to the DLF.
where fR is the reference clock frequency generated by a crystal oscillator.
The proportion & integration module (PI) consists of a proportional branch and an integral branch. The input data is multiplied by a scale factor ˛ in the proportional branch. The integral branch multiplies the input data by a coefficient firstly,
and then continuously accumulates (just like an integrator) it in
the time domain. The final result of the PI module is the combination of the proportional branch and the integral branch. The
transfer function of the PI module can be described in the frequency domain as:
3.2. Digital loop filter
3.3. NTW-clamp circuit
The DLF is a key module in this ADPLL based synthesizer; it defines the procedure this architecture follows. With
the innovation of the DLF, the synthesizer can improve a variety of performances such as locking time, spur suppression,
phase noise and so on. The DLF structure in this ADPLL based
synthesizer is shown in Figure 13.
As shown in Figure 13, the DLF in this synthesizer architecture is composed of three parts, i.e., a multiply-by-K multiplier, a 4-stage IIR filter, and a proportion & integration module (PI). The function of each part will be discussed in the following.
In the actual work process of the circuit, TDC resolution
may have some deviation compared with the designed value,
and the DCO gain (Kdco / will change a lot when operating at
different frequencies, so the actual loop transfer function will
have a deviation compared with the designed value, causing a
large inconsistency between the actual bandwidth and the theoretical one. In order to calibrate this deviation, it is necessary to
introduce a loop gain multiplier so that the TDC output value
will be multiplied by a scaling factor K, the value of which
can be adjusted as we need. Then the output will be sent into
the loop filter of the next stage. In the frequency domain, the
transfer function of the K-multiplier is just the factor K.
Following the K-multiplier is a 4-stage IIR filter. The usage of the multi-stage IIIR filter is mainly for the suppression
of some phase noise. In this design, we adopt a 4-stage singlepole IIR filter connected in series. As the structure of the singlepole IIR filter shown in Figure 13, the transfer function of the
The calculation result of the PI module is a signed number of which the highest bit represents the positive or negative value of the result. However, the normalized DCO tuning
word (NTW) should be an unsigned number. Therefore, the
first function of the NTW-clamp circuit is the implementation
of transforming a signed number to an unsigned one. All the
data in the DLF have a length of 30 bits, so this function can
be realized by combining the PI result with a fixed value of
20000000’h.
Assuming the ADPLL is locked at a specific frequency.
The normalized tuning word (NTW) of the DCO is X at that
time. Then during the locking process of the ADPLL, the value
of the NTW will vibrate in the vicinity of the value X . If the
lock frequency is close to the upper or lower limits of the DCO
output frequency, the NTW of the DCO will vibrate around 0’h
or 3fffffff ’h (the length of the NTW is 30 bits), which means it
is very likely to fall below 0’h or above 3fffffff ’h, causing the
“overflow” phenomenon of the NTW. To solve this problem,
the NTW-clamp module extends the data length of the PI result
to 31 bits, in which one bit more data length than the PI result
will ensure that the internal data of the PI module can operate
correctly in a larger range, and the highest bit of the 31 bits data
can indicate the occurrence of the “overflow” phenomenon. If
the highest bit of the 31 bits is “1”, the “overflow” phenomenon
happens, and the NTW-clamp circuit will force the NTW of the
DCO to keep at the value of 0’h or 3fffffff’h. Because the internal data is 31 bits, the data in the NTW-clamp circuit can
still operate correctly although the output is clamped at 0’h
H.s/ D ˛ C
:
s
(13)
It means the integral branch can introduce a pole in the
frequency domain. Whether the integral branch is active or not,
we can switch the PLL type between type-I and type-II.
015001-6
J. Semicond. 2015, 36(1)
Zhao Yuanxin et al.
Figure 12. Structure of the proposed overflow counter.
Figure 13. Structure of the DLF.
or 3fffffff’h. The highest bit of the 31 bits data in the NTWclamp circuit will finally come to “0” because of the negativefeedback effect of the PLL. When this “overflow” phenomenon
disappears, the NTW-clamp circuit will revert the NTW of the
DCO to its real value.
Figure 14 shows the above operation of the NTW-clamp
circuit. With the help of the NTW-clamp circuit, the NTW of
the DCO avoids the ”overflow” phenomenon, enhancing the
robustness of the ADPLL system.
3.4. Programmable divider
A frequency divider plays an important role in both the
analog PLL and the divider-in-loop architecture ADPLL. With
the help of a frequency divider, the high frequency of the DCO
output will be converted into the same frequency as the reference frequency so that the TDC can complete the comparison
operation between them.
In this design, considering the covering requirements of
the PLL frequency output, a programmable fractional divider
is required. The conventional way to realize a fractional divider
is to use a † modulator to modulate a division-ratio-variable
integer divider. The division ratio of the integer divider is controlled by the output of the † modulator. It changes with
time, although the division ratio is always an integer at a time.
The average value of the division ratio is just the designed frac-
015001-7
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Figure 14. Operation of NTW-clamp circuit.
Figure 15. The conventional structure of the division-ratio-variable integer divider.
tional one over a long time.
The architecture of the † modulator in this design is a
MASH 1-1-1 structureŒ10 , which has been introduced by many
articles, so it will not be introduced here in detail. The fractional parts of the control word sent to the † modulator have
a length of 18 bits. The reference clock is produced by an offchip crystal oscillator at 40 MHz, so the frequency resolution
of the whole frequency synthesizer is about 40 MHz 2 18 152.6 Hz.
The division-ratio-variable integer divider is the other key
component in a wide-band fractional frequency divider besides
the † modulator. The conventional architecture is proposed
by Vaucher in 2000Œ3 and its structure is shown in Figure 15.
The division-ratio-variable integer divider is composed of
a number of divided-by 2/3 cells in a series. The input clock of
each cell is the output clock of the previous stage. Each cell has
a control mode output “mod”, which is fed back to the previous
stage. This “mod” signal is synchronized at the previous stage
by the corresponding input clock. Assuming that the control
word input P0–P6 is “1”, when the latter “mod” signal is transmitted to the previous stage, the divided-by 2/3 cells operate in
the divided-by 3 mode. Since the signal “mod” is active only
once in a cycle, so the divided-by 2/3 cell can experience up
to one divided-by 3 mode in the whole divider cycle and operates in divided-by 2 mode for the rest of the time. When the
divided-by 2/3 cell operates at the divided-by 3 mode, it equals
swallowing a pulse, so the relationship between the input frequency and the output frequency can be written as:
Fin D .P6 26 CP5 25 CP4 24 CP3 23 CP2 22 CP1 21 CP0 /Fout :
(14)
The range of the division ratio covers 25 to 27 –1.
However, this structure of the division-ratio-variable integer divider cannot be used directly in our ADPLL based frequency synthesizer, because it cannot operate in a fractional
mode at the boundary of the division ratio (26 in this design).
The reason is as follows. After the last divided-by 2/3 cell is
made inactive, the penultimate stage becomes the last stage of
these cells and the rising edge of each “mod” signal is also
mutated. The frequency of each “mod” signal does not change
while the phase of each “mod” signal undergoes a significant change, causing an operation failure in the corresponding instantaneous frequency division cycle. Because of these
instantaneous failures, this division-ratio-variable integer divider cannot operate in fractional mode at the boundary of the
divider ratio.
In order to solve this operation failure problem at the
boundary in the conventional structure, an improved structure
of the division-ratio-variable integer divider is proposed in this
paper, as shown in Figure 16.
Instead of the “mod” signal used as the final output of the
divider in this design, the improved structure directly utilizes
the final stage of the divided-by 2/3 cell as the final output.
When the division ratio is at the boundary, the final stage of
the divided-by 2/3 cell may be inactive, the penultimate stage
of the 2/3 cell is the ultimate output, so this design adopts a
2-to-1 data selector MUX to select the last two stages of
2/3 cells as the final output of the divider. This design optimizes the division-ratio-variable integer divider on the logical
structure of Vaucher’s structureŒ3 . It greatly reduces the use
of logic gates, needing only one inverter and a NAND gate
to complete the logic goal. The input frequency of the fractional divider in this ADPLL frequency synthesizer covers a
wide range of 1.8–3.7 GHz, so the first two stages of the 2/3
cells utilize a high-speed current mode logic (CML) structure,
while the rest of four stages of 2/3 cells utilize a true singlephase clock (TSPC) structure operating at lower frequency. As
the voltage output range of the CML structure is not in full
swing, while the TSPC structure is, a CML to CMOS converter
is adopted to realize the level shifting between them.
As the edge of the final stage of the 2/3 cell is not just
at the same time as the penultimate stage, there is a time delay between them. The length of delay time depends on the
015001-8
J. Semicond. 2015, 36(1)
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Figure 16. The improved structure of the division-ratio-variable integer divider proposed in this design.
Figure 18. The proposed dual-band DCO.
Figure 17. The circuit of delay-variable inverter chain.
logic structure of the final stage of the 2/3 cell. When the MUX
output switches between the last two stages, there will be a
fixed change in the phase, leading to an operation failure at
the boundary of the division ratio. So a delay-variable unit is
added behind the penultimate stage. The delay interval is exactly equal to the differential time of the last two stages of
2/3 cells. The use of the delay unit ensures that the edge of the
last two stages arrives at the same time. This phase calibration
method ensures the effectiveness of the fractional divider at the
boundary. The delay-variable inverter is shown in Figure 17.
The delay interval is variable by changing the sink current of
the inverter. With the help of this delay-variable inverter, the
differential time of the last two stages can be compensated for
and the improved fractional divider can operate at the boundary
of the division ratio.
3.5. Digitally controlled oscillator (DCO)
The digitally controlled oscillator (DCO) is a crucial module in ADPLL. In this paper, a LC-tank based oscillator structure tuned directly by the digital signal is used. According to the
frequency synthesizer architecture shown in Figure 2, the wideband DCO requires a frequency range of 2.5–5 GHz, meaning
a tuning range of 67%. Obviously one single LC-tank DCO is
difficult to achieve such a wide tuning range. This ADPLL architecture uses two sub LC-tank DCOs. With the help of this
dual-band structure, the 2.5–5 GHz frequency band is divided
into two sub-bands, i.e. a high-band DCO covers a frequency
range of 3.6–5 GHz while a low-band DCO covers a frequency
range of 2.5–3.7 GHz, thereby reducing the tuning ranges to
33% and 39% respectively. The dual-band DCO is shown in
Figure 18.
Figure 19. A simplified fine tuning bank using the proposed varactor.
Besides the frequency range, phase noise is another important characteristic in the design of DCO. Because of the finite
frequency resolution of the DCO, the quantization noise introduced by the DCO may degrade the performance of the ADPLL. In this paper, a novel varactor using a single PMOS is
proposed, which is as concise as an inversion-mode varactor.
The varactor utilizes the capacitance difference of one PMOS
between the saturation and linear regions. With the help of this
novel single PMOS varactor, a finer frequency resolution is realized without an extra fixed capacitance.
The fine tuning bank in LC DCO is usually unit-weighted
to reduce mismatch. A simplified capacitor tuning bank utilizing the proposed varactor is shown in Figure 19. The proposed
varactor unit consists of one PMOS, with its source and body
tied to the power supply. The tuning voltage VTUNE is applied
to the drain. The varactors in the bank are unit-weighted, and
each varactor is controlled by a digital bit (d0 , d1 , , dn /.
The C –V characteristic of the proposed varactor is illustrated in Figure 20.
The principle of the proposed varactor is to employ the capacitance difference of a single PMOS between the saturation
and linear regions. In Region I, the PMOS varactor works in
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Zhao Yuanxin et al.
Figure 20. The C –V characteristic of the proposed varactor.
the linear region, its capacitance can be expressed as:
Chigh_linear D W LCox C 2W Cov ;
(15)
Figure 21. The structure of the DCO in this ADPLL based frequency
synthesizer.
where W and L are the gate width and length of the PMOS varactor respectively, Cox represents the gate oxide capacitance
per unit area, and Cov stands for the overlap capacitance per
unit area. Also in Region I, when the tuning voltage is zero,
the PMOS varactor works in the saturation region, and its capacitance can be denoted as follows:
Chigh_satu D
2
W LCox C 2W Cov :
3
(16)
In Region II, the PMOS varactor is in depletion mode, its
capacitance remains low. Therefore, the capacitance step C
of the proposed varactor can be derived from Equations (15)
and (16), which is approximately:
C D
1
W LCox :
3
(17)
Figure 22. Microphotograph of the ADPLL based frequency synthesizer.
Obviously, it is much smaller than that of a conventional
inversion-mode MOS varactor.
The complete structure of the DCO adopted in this ADPLL architecture is shown in Figure 21. It consists of a crosscoupled NMOS and PMOS pair, a current bias, and an inductor. Besides, four capacitor tuning banks are included: a binaryweighted coarse tuning bank using switched MIM capacitors;
a binary-weighted moderate tuning bank using a conventional
inversion-mode PMOS (I-PMOS) varactor; a unit-weighted
fine tuning bank employing a minimum-sized inversion-mode
PMOS varactor; and a unit-weighted fine tuning bank employing the proposed varactors. Both the coarse, the moderate and
the fine banks are used to extend the total tuning range, while
the proposed varactor bank is designed to improve frequency
resolution.
4. Measurement results
Figure 23. Test PCB of the ADPLL chip in a COB package.
The proposed ADPLL based frequency synthesizer has
been implemented in a 0.13 m mixed-signal/RF CMOS process. The total area of the chip is about 2.65 1.4 mm2 . Figure 22 shows a microphotograph of the ADPLL frequency synthesizer.
The ADPLL frequency synthesizer is bonded to the PCB
with a chip-on-board (COB) package for the test, as illustrated
in Figure 23.
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Zhao Yuanxin et al.
Figure 24. Measurement of TDC when fCKV is 41.67 MHz.
Figure 26. Frequency tuning curve of high-band DCO.
Figure 25. Measurement of TDC when fCKV is 38.46 MHz.
Figure 27. Frequency tuning curve of low-band DCO.
4.1. Measurement results of the TDC
To test the TDC, we use two groups of test stimulus signals.
The first group is fREF D 40 MHz, fCKV D 41.67 MHz. The
second group is fREF D 40 MHz, fCKV D 38.46 MHz.
The measurement results are shown in Figures 24 and 25
respectively. From the results, we can see that, when the frequency of CKV is higher than REF’s, the TDC’s output is positive. Otherwise it is contrary. When fCKV is 40.17 MHz, CKV’s
period is 24 ns, the TDC’s input time interval increases 1ns after each measurement. Since the mean change of the TDC output is 7.8, we can get the TDC’s raw resolution as (1/7.8) ns D
128 ps, which means the delay time of the GRO’s delay-stage
pair is 128 ps.
Figure 28. Open-loop phase noise of the DCO at 3.2 GHz.
4.2. Open-loop measurement results of the DCO
To get the open-loop characteristics of the high-band DCO
and low-band DCO, the DCO input control words are controlled by the single-chip machine (SCM). Set the control
words of high-band DCO to the maximum and the minimum
value respectively, we can get 3.5–5.2 GHz output frequency
range of high-band DCO. Keeping the value of the moderate
tuning bank and the fine tuning bank constant, then changing
the tuning words of the coarse tuning bank, we can obtain the
high-band DCO frequency tuning curve shown in Figure 26.
The measured tuning range of the high-band DCO is 39%.
We can also obtain the frequency coverage of the low-band
DCO as 2.4–3.8 GHz in the same way. The frequency tuning
curve of the low-band DCO is shown in Figure 27. The measured tuning range of the low-band DCO is 45% .
Taking the low-band DCO operating at 3.2 GHz for example, the open-loop phase noise and the frequency spectrum of
the DCO output are shown in Figures 28 and 29, respectively.
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Zhao Yuanxin et al.
Figure 29. Open-loop frequency spectrum of the DCO at 3.2 GHz.
Figure 31. Transient locking curves with the overflow counter enabled
at 2.68 GHz.
Figure 30. Transient locking curves with the overflow counter bypassed at 2.68 GHz.
As can be seen, the DCO phase noise at 1 MHz offset from
the center frequency reaches –116 dBc/Hz, and the reference
spur at 40 MHz offset reaches 60 dBc.
The power consumption of the dual-band DCO at 3.2 GHz
is 3.9 mW. The FOM value of the oscillator can be calculated
byŒ11 :
FOM D
L .f / C 20 lg
fo
f
10 lg
PDC
;
1 mW
(18)
where L (f ) is the phase noise of the carrier at the offset
frequency of f , and PDC is the power consumption of the
oscillator expressed in the unit of mW. The FOM value of the
dual-band DCO at 3.2 GHz reaches 180.2 dBc/Hz.
4.3. Closed-loop measurement results of the ADPLL frequency synthesizer
An overflow counter is added to the ADPLL frequency
synthesizer in order to achieve a shorter locking time. It can
effectively increase the output range of TDC, making the ADPLL loop locked faster. When the low-band DCO is used in the
loop, Figures 30 and 31 show the measurement results of the
transient locking curves with the overflow counter bypassed
Figure 32. Measurement result of phase noise at 900 MHz.
and enabled, respectively. The locking frequency of the synthesizer is at 2.68 GHz here.
As can be seen, the locking time is approximately 363 s
with the overflow counter bypassed. But this number significantly reduces to 57 s when the overflow counter is used,
achieving a reduction of 84%. This measurement result indicates that the overflow counter module is very helpful to the
reduction of locking time.
The phase noise and the frequency spectrum are very important characteristics of the frequency synthesizer. Figures 32
to 37 demonstrate the complete performance of the ADPLL
based frequency synthesizer in the aspects of phase noise and
frequency spectrum. They show that this architecture of ADPLL can lock at a frequency range of 0.8–4.2 GHz. Let us take
two frequency points as examples to demonstrate these performances in detail.
When the locking frequency is at 900 MHz, the phase noise
and frequency spectrum curves are shown in Figures 32 and 33
respectively.
As can be seen at the center frequency of 900 MHz, the
in-band phase noise at 10 kHz offset from the center frequency
reaches –100 dBc/Hz, the out-band phase noise at 1 MHz offset
from the center frequency reaches –125 dBc/Hz. The reference
spur at 40 MHz offset reaches –53 dBc.
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Figure 33. Frequency spectrum at 900 MHz.
Figure 36. In-band and out-band PN at 10 kHz and 1 MHz offset from
0.8–4.2 GHz.
Figure 34. Measurement result of phase noise at 4.24 GHz.
Figure 37. The modeling result of the output phase noise at 2.08 GHz.
Figure 35. Frequency spectrum at 4.24 GHz.
When the locking frequency is at 4.24 GHz, the phase
noise and frequency spectrum curves are shown in Figures 34
and 35, respectively.
As can be seen at the center frequency of 4.24 GHz, the
in-band phase noise at 10 kHz offset from the center frequency
reaches –84 dBc/Hz, and the out-band phase noise at 1 MHz
offset from the center frequency reaches –104 dBc/Hz. The reference spur at 40 MHz offset reaches –58 dBc.
Figure 36 shows the characteristics of both in-band and
out-band phase noise (PN) at 10 kHz and 1 MHz offset respectively covering the whole frequency locking range from 0.8–
4.2 GHz.
As can be seen, the average in-band phase noise is approximately 90 dBc/Hz through the whole frequency range of 0.8–
4.2 GHz and the average out-band phase noise is approximately
–110 dBc/Hz.
Now the measurement results of output phase noise will be
compared with the noise modeling results. We take the output
frequency of 2.08 GHz as an example. The total output phase
noise curve of the loop is shown in Figure 37 using the matlab tool, where the black line is the total output phase noise of
the modeling result and the lines of other colours represent the
contribution of different noise sources to the total phase noise.
The actual measurement result is shown in Figure 38. We can
find a good agreement between these two results, indicating
that the previous noise modeling method is of high accuracy.
According to the in-band phase noise, we can calculate the
TDC effective resolution by Equation (19)Œ12 :
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J. Semicond. 2015, 36(1)
Parameter
Technology (nm)
Supply voltage (V)
Reference (MHz)
Frequency range (GHz)
In-band PN (dBc/Hz)
Out-band PN (dBc/Hz)
Ref. Spur
(dBc)
Area (mm2 )
Power consumption (mW)
Zhao Yuanxin et al.
Table 2. Performance summary and comparison.
This work
Reference [13]
Reference [14]
130 CMOS
65 CMOS
65 CMOS
1.2
1.8
1.8
40
40
25
0.84.2
2.94
33.6
–92
–101
–101
@ 3.68 GHz
@ 3.2 GHz
@ 3.5 GHz
–112
–121
–123
@ 1 MHz
@ 3 MHz
@ 3 MHz
–42
–42
–57
@ 3.68 GHz
@ 3.2 GHz
@ 3.5 GHz
3.6
0.2
0.4
88*
4.5
80
Reference [15]
40 CMOS
1.5
26
2.418
–90
@ 2.418 GHz
–109
@ 10 MHz
N/A
0.2
6.4
Reference [16]
65 CMOS
1.8
48
4.96.9
–97
@ 5.3 GHz
–114
@ 1 MHz
–45
@ 5.3 GHz
1.3
20
*: On-chip test circuit included
Figure 38. The measurement result of the output phase noise at 2.08
GHz.
Figure 40. Simulation results of the reference spur at (a) 2.4975 GHz,
(b) 3.03 GHz, and (c) 3.71 GHz.
Figure 39. Reference spur at 40 MHz offset from 0.8–4.2 GHz.
tTDC 2
1
;
S˚OUT D 2
TDCO
12fREF
(19)
where tTDC is the TDC effective resolution. fREF is the sampling frequency. TDCO is the cycle of DCO. Therefore, the TDC
effective resolution reaches 23–182 ps over the frequency band
of interest. Compared to the 128 ps TDC raw resolution, we can
see the benefit of GRO’s noise shaping.
Figure 39 shows the characteristic of the reference spur at
40 MHz offset through the whole frequency locking range of
0.8–4.2 GHz. The best reference spur is about –58 dBc.
Since the leakage of the reference spur is very complex, it
is very difficult to find an accurate and effective way of modeling the spur method to predict the output value of the reference
spur in the theoretical analysis. But we can adopt the reference spur simulation of the ADPLL loop in the circuit-level
under the environment of Cadence SpectreRF to simulate the
reference spur value in a different frequency point, then we can
summarize the trend of the reference spur values at the different frequency and compare the measurement results with the
simulation results so as to verify the validity of the measurement results of the reference spur.
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J. Semicond. 2015, 36(1)
Zhao Yuanxin et al.
Figures 40(a)–40(c) show the simulated reference spurs at
different frequencies within a wide locking range of the loop.
We can find that the reference spur values lay in a range between 55 to 50 dB stably. Figure 39 shows the characteristic of the reference spur at 40 MHz offset through the whole
frequency locking range of 0.8–4.2 GHz. By means of the
comparison between the simulation results and the measurement results, we can find that the actual reference spur values
are slightly worse than the simulation ones, which are mainly
caused by the nonlinear characteristic of TDC.
Finally, the performance comparison between the proposed ADPLL architecture and other published papers are summarized in Table 2. Obviously, our work has achieved a wider
frequency range with a competitive performance of the ADLL
based frequency synthesizer compared to the others, whatever
the in-band or out-band phase noise and the reference spur suppression. The locking time is not listed in Table 2, although its
performance is one of the highlights of this work, because there
is no such information in these published papers.
5. Conclusion
[5]
[6]
[7]
[8]
[9]
[10]
A 0.8–4.2 GHz monolithic all-digital PLL based frequency
synthesizer is successfully realized for wireless communications. A series of novel methods are proposed in this paper to
effectively solve the problems that are encountered in the design procedure. This chip is fabricated by the 130 nm CMOS
process and the complete measurements are carried out to
demonstrate its good performance. The locking time achieves
a reduction of 84% at 2.68 GHz. The best in-band and out-band
phase noises have reached –100 dBc/Hz, and –125 dBc/Hz, respectively. The lowest reference spur is 58 dBc.
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