Session 102
Curvaceous Circuits:
Encouraging Visualization in Mixed Series-Parallel Circuit Analysis1
Kevin C. Davis
Department of Electrical and Computer Engineering
Western Michigan University
Abstract
In this paper the author illustrates systematic circuit redrawings using breadth first search
starting at "half" the source, redrawing the visited electrical node wiring in a manner akin to
rail-road (computer language syntax) diagrams where the sidings arise from redrawn wiring
and the electrical components are where the tokens would be. Implied left to right
conventional current flow is terminated with the other "half" of the source. The resulting
curvaceous circuit drawing helps facilitate writing of the equivalent resistance (or impedance)
in terms of the series and parallel operators.
Further visualization is encouraged in the organization of intermediate equivalent resistances
in a manner that facilitates reuse for branch division and superposition. The introduction of
graph theory in the University of Chicago School Mathematics Project high school geometry
text 1 supports the further development and application by lower division college students of
an elementary graph algorithm in circuit visualization. Elementary graph theory also enhances
many traditional topics in lower division college courses (e.g. Management).
1. Introduction
In our Fundamentals of Electrical Circuits course we introduce DC and AC circuit analysis
without using nodal or mesh analysis power tools (although they are presented in Floyd's2
text). Visualization of sub-circuits that are parallel, series or combinations thereof is difficult
for some students  consider the equivalent circuits in Figures 1-4 and the curvaceous circuit
drawn in Figure 5. Given the lack of celerity in getting to the power tools this instructor has
the luxury of encouraging possibly helpful circuit redrawings by students. Often students fail
to redraw a circuit since they do not have any guidance in doing so. Hayt and Kemmerly3
(e.g., pp. 59, 65, 92, 98) take liberty to draw some example circuits with curves in addition to,
or instead, of lines.
1
The author appreciates the resource support given by Dr. Damon Miller and Mr. David Florida of WMU's ECE
Dept.
Figure 1. A mixed series-parallel circuit with inflection
Figure 2. Figure 1 circuit without inflection
Figure 3. Parallel biased drawing of Figure 1
Figure 4. Series biased drawing of Figure 1
Figure 5. Curvaceous circuit redrawn from Figure 1
2. Curvaceous Circuits
Floyd 2 (p. 303, Problem 13) presents an introductory circuit problem where the student is
asked to use Thevenin's theorem to solve for the current through the load. We solve this
problem without Thevenin (see Figure 6). BFS is applied to the nodes starting with node zero
adjoining the positive terminal of the source and proceeding clockwise yielding a curvaceous
rail diagram depicted in Figure 7. Variation from this figure is to be expected due to the order
of electrical node selection and due to either an alternating or opposite tendency in redrawing
wires.
Figure 6. Adapted from Floyd 2 problem 13
We adapt Even's4 [p. 12] exposition of Breadth First Search (BFS) as suggested by Moore for
finite graphs with a step intentionally omitted (If vertex t is labeled, stop.) and node
substituted for vertex:
At first no nodes of the graph are considered labeled.
1.
2.
3.
4.
5.
Label node s with 0.
i← 0
Find all unlabeled nodes adjacent to at least one node labeled i. If none are found, stop.
Label all the nodes found in (3) with i + 1.
i ← i + 1 and go to (3).
To our application of BFS we add the following rules already mentioned in
the abstract:
1. Node 0 adjoins the arrowhead side of a current source or the (+) side of a voltage source.
2. Implied left to right conventional current flow is terminated with the other "half" of the
source. (Chose the adjoining node last.)
The resulting curvaceous circuit drawing helps facilitate writing of the equivalent resistance
(or impedance) in terms of the series and parallel operators as drawn in Figure 7.
Figure 7. Curvaceous circuit for problem 13
Figure 8 starts with the equation for equivalent resistance with the right hand side expression
involving the parallel operator. In the vertical dimension we carefully express intermediate
equivalent resistances to facilitate reuse in the ensuing branch current analysis.
Figure 8. Careful layout of intermediate equivalent resistances
3. Regarding Planarity
In dealing with the topology of circuits for the first time we note that for awareness purposes
(the instructors not necessarily the students) a discussion of planarity testing from an upper
division or graduate text on graph algorithms:
"There are two known planarity testing algorithms which have been shown to be
realizable in a way which achieves linear time (O(|V|)). The idea in both is to follow
the decisions to be made during the planar construction of the graph, piece by piece, as
to the relative location of the various pieces. The drawing is not carried out explicitly
..." [Even4 , p. 171]
Such constructive algorithms further motivate in an analogous manner circuit redrawing as
adjunct to traditional algebraic manipulation for circuit analysis.
4. Possible Extended Work
1.
2.
3.
4.
5.
2
A variation in rail typesetting that includes the component symbols rather than names.
Depiction of non-series-parallel circuits (e.g. Wheatstone Bridge).
Depiction of non-planar circuits.
Subscripting and landmark conventions for superposition of currents.
Depiction a large complex circuit using rail non-terminals 2 for abstraction of subsystems.
N.B. we are not speaking of electrical terminals.
6. Degenerate subproblems  particularly the depiction of shorts and opens with respect to
circuit redrawings arising from superposition or Thevenin's Theorems.
7. Emanuensis  i.e., contrasting hand drawn curvacious circuits with rail diagrams.
8. Node labeling in the rail diagram.
5. Colophon
This exposition is somewhat rudimentary in that Microsoft WordT M was used to integrate
PostscriptT M components. The use of m4 LaTEX circuit macros for typesetting the traditional
circuit diagrams would facilitate the use of LaTEX for integration too. The rail (syntax)
diagrams were developed using Rooijakker's5 LaTEX macros and program. Rail diagrams are
used extensively in computer science and notably in Oracle T M programming language and
command documentation. Scaling and legible subscripts are a problem without LaTEX.
6. Conclusion
In this minimal introduction to curvaceous circuits we broke away from traditional
rudimentary topological circuit analysis and typesetting to present a companion tool that may
help some students with some mixed series-parallel circuit problems. This extends the
visualization of circuits out of the Manhattan block world into a realm that is isomorphic with
computer language syntax diagrams which are in turn isomorphic with equivalent resistance
expressions involving the parallel operator.
Bibliography
[1] Coxford, A., Zalman, U. and Hirschhorn, D., University of Chicago School Mathematics Project Geometry,
ScottForesman, 1991.
[2] Floyd, T. L., Principles of Electric Circuits: 6th ed., Prentice-Hall, NJ, 2000.
[3] Hayt, W. H. Jr. and Kemmerly, J. E., Engineering Circuit Analysis, McGraw-Hill, NY, 1971.
[4] Even, S., Graph Algorithms, Computer Science Press, Rockville, MD, 1979.
[5] Rooijakkers, L.W.J. and Barthelmann, K., "Rail: Syntax Diagrams For LaTEX"
http://ctan.tug.org/ctan/, 1998.
KEVIN DAVIS
B.S. Mathematics and the M.S. Computer Science degrees from Western Michigan University, Kalamazoo in
1978 and 1990 respectively. From 1978 to 1981 he was responsible for the communications network software
engineering of protocol gateways between WMU and the Merit network. Currently he is a consultant to industry
and an adjunct assistant professor of electrical and computer engineering at Western Michigan University.