App
plication Note
e MOS--010
D
December
r 2013
Paralleling Pow
wer MOS
SFETs in
n Switch
hing App
plication
ns
Abstract: This paper discu
usses issues involved in pa
aralleling MO
OSFETs in hig
gh-power, high-frequency switching
s
applications. It investigattes root causse problems such
s
as unba
alanced volta
age and curre
ent by taking a closer
examination of PCB layou
uts and importtant circuit de
esign parametters for driving paralleled MOSFETs.
M
1. Introdu
uction
MOSFETs with
w
low on-re
esistance and
d fast switch
hing characte
eristics are widely
w
used in
n switch-mod
de power
supplies and motor driverrs in e-bikes, electric-moto
or cars, powerr tools and electric lawn mowers.
m
In th
hese high
power appliccations, multip
ple MOSFETss used in parrallel are ofte
en necessary to increase current capab
bility and
improve efficiency.
Multiple facto
ors influence successful pa
aralleling of high-speed
h
po
ower MOSFE
ETs. Variancce in the actual device
parameters, asymmetric gate drivers, and poor layout of the PCB
P
can cau
use a numbe
er of problem
ms. First,
unbalanced current
c
flow in
i parallel MO
OSFETs can provoke ove
er-current con
nditions and damage one or more
MOSFETs. Second, the drain-to-sourcce voltage ap
pplied to each
h MOSFET can
c actually be
b different, potentially
reaching dam
maging levels
s on the drain
n of one of th
he devices. Finally, parassitic oscillatio
ons can appe
ear at the
gate of each
h MOSFET, causing
c
exce
essive gate-to
o-source voltage, potentia
ally damaging
g one or morre of the
MOSFETs byy exceeding its maximum
m rated VGS. This application note con
nducts a deta
ailed study off each of
these issues and provides
s recommended solutions.
2. Unbala
anced Currrent and Vo
oltage- in Parallel
P
MO
OSFET App
plications
Under steadyy-state condittions, paralleled MOSFETss work well, sharing
s
curren
nt with an equal amount of
o voltage
across each.. The on-res
sistance (RDSS(on)) of a MO
OSFET has a positive tem
mperature coe
efficient, meaning that
RDS(on) increa
ases with tem
mperature. This known phenomenon
n assists in paralleling MOSFETs
M
as it helps
balance the current among multiple MOSFETs.
M
Current flowss through the
e path of lea
ast resistance
e and as
current incre
eases in one MOSFET, power dissipation also increases, heatiing the devicce and increa
asing the
RDS(on). At that point, curre
ent will flow to
o one of the other
o
MOSFETs with a low
wer resistance
e, causing the
e inherent
current sharin
ng amongst the MOSFETss.
Under switch
hing condition
ns, the story iss very differe
ent. Generallyy speaking, a MOSFET be
ehaves like a voltagecontrolled sw
witch. During
g the dynam
mic process of
o switching, many factorrs can cause
e current and
d voltage
imbalances, especially at higher freque
encies. The characteristiccs of the MOS
SFET, includiing the gate threshold
t
voltage, its forward
f
trans
sconductance
e, total gate charge (Qg), RDS(on), the actual driverr circuit and parasitic
inductances in the PCB all
a factor in to current and voltage imba
alances. The
e MOSFET pa
arameters are
e fixed at
the time of de
evice producttion and cann
not be change
ed in the appllication, and screening
s
MO
OSFETs to ge
et exactly
matched para
ameters can be economica
ally challengin
ng. The bestt way to preve
ent these prob
blems is to usse proper
gate driver design
d
techniques that en
nsure that the
e current and
d voltage acrross the para
alleled MOSF
FETs are
properly bala
anced.
Rev. 1.0
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Page 1 of 8
Applicatio
on Note MOS-010
M
2.1. Current Unbalance Resulting
R
Fro
om MOSFET
T Parameters
s
Understandin
ng MOSFET parameters and
a how theyy affect curren
nt and voltage
e balancing in
n paralleled MOSFET
M
applications is
i an importan
nt first step to
o determining the right solu
ution to the prroblems that may
m arise.
Threshold Vo
oltage, Gate-tto-Sourec (VGS(TH)
): Parallleled MOSFE
ETs are norma
ally driven byy the same ga
ate driver
G
or gate driverr signal. A MOSFET with a lower gate-to-source thre
eshold voltag
ge (VGS(TH)) will turn on fastter than a
second MOS
SFET with a slightly
s
higherr VGS(TH). Thiss results in higher current flowing throu
ugh the MOSFET with
the lower VGSS(TH) and an unbalanced cu
urrent situation.
Forward Tran
nsconductanc
ce (gFS): In th
he saturation region betwe
een the cut-offf region whe
ere the MOSF
FET turns
off and the Ohmic
O
region where the MOSFET
M
is fu
ully on, the drain
d
current is
i controlled by the gate-tto-source
voltage, VGS. This region is governe
ed by the forrward transco
onductance (gFS) characte
eristics of the
e device.
Different gate
e-to-source voltages
v
will cause
c
curren
nt imbalancess during the transition
t
from
m on to off and
a
viceversa.
Gate Charge
e (Qg): Total gate charge, the total cha
arge required at the gate to
o turn-on the MOSFET an
nd enable
current flow from drain-to
o-source, will significantly affect
a
the sw
witching speed
d of the MOS
SFET. When
n multiple
h a lower Qg value, it will turn on faster than the re
est of the
MOSFETs arre paralleled, if one of the MOSFETs has
MOSFETs. This
T
faster tu
urn on causess that MOSFE
ET to handle the majority of
o the currentt during the trransition,
causing anotther unbalanc
ced current co
ondition.
2.2. The Effe
ect of the Gate Driver Res
sistance on Current Imba
alance
In the gate driver
d
circuit shown
s
in figu
ure 1, an intentional mismatch has bee
en created an
nd tested to show
s
the
impact of mismatched
m
gate
g
resistan
nces. As will
w be shown
n in section 3, the use of gate ressistors is
recommende
ed in high-freq
quency applications to avvoid additiona
al complicatio
ons, and it is critical to ensure that
these gate re
esistors are matched
m
as closely as posssible. In the gate
g
driver circuit shown in
n figure 1, Q1
1 and Q2
are paralleled
d. R1 is the driving
d
resisto
or connected in series with
h the gate of Q1.
Q R3 is con
nnected to R1
1 and the
gate of Q2. This
T
creates the
t gate drive
er mismatch.
Figure
F
1. Driving Circuit with the Gatte Resistor Mismatch
M
Rev. 1.0
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Applicatio
on Note MOS-010
M
Figure 2a. Turn-On Waveforms
Figu
ure 2b. Turn--Off Waveforrms
t gate-to-so
ource voltages during turn--on and turn-off that resultt from the gatte driving
Figures 2a and 2b show the
resistor mism
match. Chann
nel 1 shows the
t faster turn
n-on and turn
n-off times of Q1, the resu
ult of the sligh
htly lower
gate resistan
nce. These fa
aster switchin
ng times provo
oke higher cu
urrent flow thrrough Q1, compared to the current
flow through Q2. The higher current flo
ow through th
he parasitic in
nductance in the
t drain and
d source of Q1 causes
larger voltage
e peaks and ringing. The
e difference between
b
Q1 and
a
Q2 in fig
gures 2a and 2b shows th
hat Q1 is
handling larg
ger peak curre
ents during th
he transitions due to the mismatched
m
gate driver ressistors. It is important
to balance cu
urrent through
h each MOSF
FET during trransitions to avoid
a
excessiive stress on one of the MOSFETs
M
in a paralleled application,, and using matching
m
gate resistance is the key to acchieving the desired
d
perforrmance.
ect of the Gate Driver Cirrcuit Layout on
o Voltage Unbalance
U
2.3. The Effe
In high-powe
er, high-frequ
uency applica
ations, the pa
arasitic inducctance of the
e PCB can negatively
n
im
mpact the
overall syste
em. Excessiv
ve stray inductance in the
e drain may cause
c
the MOSFET to fa
ail if they are not well
controlled.
Figure 3 show
ws parasitic inductance in two parallele
ed MOSFETs, intentionallyy skewed to simulate
s
a poo
or layout.
In this circuit, the drain ind
ductance of Q1
Q is 40nH (L
L1) and the inductance of Q2
Q is 20nH (L
L2). AOT470 is a 75V
MOSFET tha
at was chosen
n for this simu
ulation.
Fig
gure 3. A Sim
mulating Circ
cuit with Diffferent Drain Inductance
I
Rev. 1.0
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Page 3 of 8
Applicatio
on Note MOS-010
M
Inducced by drain
inductance and
di/dt
Q1 VDS
D
Ringing
Q2 VDS
Q2 current
Q1 current
Figu
ure 4. Simulation Waveforms with Diff
fferent Drain Inductances
s
During turn-o
off a voltage will
w be added to the maxim
mum drain voltage as dete
ermined by the
e parasitic ind
ductance
and the chan
nging current (V = L* di/dt)). If the matcching circuits consist of the
e same di/dt characteristicc and the
parasitic inductance is optimized
o
for each MOSF
FET, the max drain volta
age seen by each device
e will be
approximately the same.
When the parasitic inducta
ances in the drains
d
are diffferent, the two
o excessive voltages
v
caussed by the V = L * di/dt
term will be unequal.
u
This
s difference, in
i turn, influen
nces the mag
gnitude of the
e di/dt and eve
entually will re
esult in a
higher drain voltage on Q1.
Q
Additiona
ally, since the
e drain inducctance of Q1 is larger, its ringing amplitude (as
shown in figu
ure 4) is also larger when L1 rings with
h the Coss of the AOT470 and the para
asitic resistan
nce in the
circuit. This combination
n of ringing and
a
the volta
age spike on the drain du
uring turn-off can easily make
m
the
MOSFET excceed its maxiimum rated drain-to-sourc
e voltage and
d
d cause failurre. By carefu
ully designing the gate
driver circuit as shown in section 2.2, and minimizing parasitic circuit
c
inducta
ance during PCB
P
layout, th
he circuit
designer can avoid these mismatches.
3. Managing Potenttial Oscillattions in Pa
aralleled MOSFET
M
Ap
pplications
s
Many design
ners tend to directly
d
conne
ect both gatess and both drains togethe
er when parallleling two MO
OSFETs.
However, thiss approach can
c easily cau
use an oscilla
ation on the gate.
g
Worst case,
c
the osccillation ampliitude can
even surpasss the maximum rated gate voltage and wind
w
up dama
aging the MO
OSFET.
Rev. 1.0
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Applicatio
on Note MOS-010
M
3.1. Example
es of Oscillation
s of Two MOSFETs Direc
ctly Paralleled
Figurre 5. Turn-Offf Waveforms
s of Two MOSFETs Parallleled with Se
eparate Driving Resistorrs
Figurre 6. Turn-Offf Waveforms
Figure 5 sho
ows a clear example
e
of an
a oscillation that can occcur when the two gates are
a directly co
onnected
together. Th
he high freque
ency oscillatio
on of ~150MH
Hz occurs during the turn--on and turn-o
off transitionss. These
oscillations often
o
have ve
ery high amp
plitudes and can easily exceed
e
the maximum
m
ratting of gate-tto-source
voltage or dra
ain-to-source voltage and damage the device.
d
Through the use of individ
dual gate drivving resistors, the oscillatio
on can easilyy be removed
d. Figure 6 sh
hows the
ding a single resistor in the gate of each
e
MOSFET. Both gatte and drain voltages are
e virtually
result of add
identical on the
t two MOSFETs, meaning that the cu
urrent through each device can be asssumed to be the
t same
when paralleled. This gre
eatly improvess the reliabilityy of the circuit.
ause Analysis
s of Gate Os
scillation
3.2. Root Ca
To understan
nd the cause
e of the high
h frequency oscillation att the gate off two MOSFETs that are
e directly
connected to
ogether, it is
s important to
o analyze th
he equivalentt circuit. Fig
gure 7 show
ws the two paralleled
p
MOSFETs with
w
the paras
sitic drain ind
ductances, gate capacitan
nces (Cgd), and gate ressistances all detailed.
These compo
onents form a low-impedan
nce loop and can be consiidered as a se
eries RLC equivalent circu
uit.
f0 
Resonan
nt frequency of
o a series RL
LC circuit ：
Q
Quality fa
actor of a seriies RLC circu
uit：
Rev. 1.0
0 L
R

1
2 LC
C
（1）
1
R 0 C
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（2）
Page 5 of 8
Applicatio
on Note MOS-010
M
Equations 1 and
a 2 determ
mine the reson
nant frequenccy of the serie
es equivalent circuit and th
he quality facttor (Q) at
that resonant frequency. The lower impedance th
he circuit hass, the higher the resulting Q factor. The
T
more
selective a circuit
c
behave
es in respond
ding to signals of a given
n frequency, the
t
higher th
he resulting oscillation
o
amplitude. In order to av
void this oscillation, equal gate resistors are recom
mmended in series
s
with ea
ach gate,
s the oscillatio
on when the loop impedan
nce is very low
w.
which will help to suppress
Figurre 7. Model of
o Paralleling
g of MOSFET
Ts
OT474 powerr MOSFETs are
a paralleled
d, the oscillatiion that results is due to th
he reduced Cgd value,
When two AO
which in turn
n increases th
he Q factor (Q
Q is inverselyy proportional to Cgd). The
e solution is to
t connect a separate
gate resistor of 10 to th
he gate of ea
ach MOSFET to reduce th
he Q factor and suppress the oscillatio
on on the
gates, as sho
own in figure 6.
6
The circuit simulation in figures 8a, 8b and 9 further demonstrate
es why seriess gate resista
ances are imp
portant to
suppressing oscillations. The parameters used in this model were obtained from the electrical specifiication of
e’s internal Rg is 2.8 and the Cgd is 36pF. Asssuming the parasitic
the AOT474 datasheet. The device
o 60nH in the loop, the new
n
equivalent circuit and
d the values of the equiva
alent impedances are
inductance of
show in figurre 8a. Figure
e 8b shows th
he impact of adding
a
a 10
 series gate resistor each MOSFET, in
ncreasing
the effective gate resistance from 5.6
 to 25.6.
Rev. 1.0
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Applicatio
on Note MOS-010
M
Figure 8a. RLC Circu
uit Model
with Internal Rg
R
Figurre 8b. RLC Circuit Model with a
10Ohm Resistor in Series
S
with the
t Gate
Small-signal analysis perfformed using the paramete
ers obtained from the AOT
T474 datashe
eet and the equivalent
circuit modells shown in figures
f
8a an
nd 8b yielded the results shown
s
in figu
ure 9. The red
r
curve obttained by
simulating th
he circuit in figure 8a shows the app
proximately 150MHz reso
onant frequen
ncy at high Q,
Q which
corresponds nicely to the waveform sh
hown in figure
e 5. The blue
e curve is the simulation re
esult for the equivalent
circuit in figurre 8b, showin
ng the impact of adding a 10
1
gate resistor to each MOSFET
M
gate
e. The Q factor of the
circuit is significantly reduc
ced, explainin
ng the result shown
s
in figure 6 of a veryy clean gate drive
d
waveform
m.
Figure 9. Simulation Wa
aveforms of a Series RLC
C Circuit
Rev. 1.0
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Applicatio
on Note MOS-010
M
4. Conclu
usion
For optimal current
c
sharing and voltage
e balance whe
en using para
alleled MOSF
FETs in switch
hing applicatio
ons, care
must be take
en while desig
gning the circcuit. Dedicatted gate resisstors for each
h MOSFET will
w help match
h turn-on
and turn-off times
t
while re
emoving the possibility
p
for high-frequen
ncy oscillation
ns. Proper ca
are during PC
CB layout
in order to minimize current loops while
e keeping trace lengths sh
hort, wide and
d matched to reduce the amount
a
of
parasitic indu
uctance in hig
gh current patths will help keep the voltages equal and within the design
d
specificcation.
Reference
es
1. Parallelin
ng of MOSFETs
J.B. Forssythe, IEEE-IA
AS Conferencce Record, Occtober 1981.
2. Analysis of Power MO
OSFET Perforrmance in Parrallel Operatio
on
QAIN Min
n, XU Ming-qiian, Min Zhi-n
nan (Institute of Mechanica
al Engineering
g, Tongji Univversity, Shang
ghai
201804, China,
C
2007.1
11
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emiconductor, Inc. All rights reserved.
r
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LAIMER
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ductor makes no representatio
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eness of
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n provided here
ein and takes no
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nces of use of such informatio
on or any product
described here
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o make change
es to such inforrmation at any time
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ocument does not constitute the
t grant of any intellectual property
p
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on of noninfringement of any third partty’s intellectual property rightss.
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