International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 3 (2016) pp 2007-2015
© Research India Publications. http://www.ripublication.com
Logic and Topology of Switchover Interlocks in Electrical Networks
Ilya Abramovich Golovinskii
National Research University of Electronic Technology (MIET),
Bld. 1, Shokin Square, Zelenograd, Moscow, 124498, Russia.
circuits including interlock circuits. However in the case of a
programmable interlock two its significant disadvantages
became clear: 1) the dependency of interlock algorithms on
the topology of the electrical network under control; 2) the
need to iterate trough a great number of possible combinations
of the states of the elements of a network.
Both these issues can be resolved by applying topological
methods to the analysis of the switching circuits of an
electrical network. First this was done using a query language
for graph databases similar to the language LSL [13] (Note 2).
But the semantics of a query language designed for databases
is not quite adequate to the nature of the problems of the
analysis of the switching circuits. The methods of the specific
graph algebra used in the present paper make the solution of
the problem easier.
Software interlocks significantly extend the capabilities of
automation of interlocks in electrical networks compared to
hardware interlocks (mechanical, electromechanical and
electromagnetic ones). Sometimes hardware interlocks are not
entirely suitable even for typical tasks due to the complexity
of implementation (Note 3). Complicated sets of hardware
interlocks are unreliable while they are themselves built to
provide the reliability of operation [26]. The practical value of
hardware interlocks is not important for computer modeling of
power engineering objects for system simulation and training
purposes. Computer modeling of interlocks is only possible on
the basis on their logical form in principle.
Together with the usage of hardware interlocks the rules for
making switchovers in electrical networks also contain such
interlock requirements which are too complex or too
expensive to be implemented in hardware. In the regulations
these requirements are attributed to the dispatching and
operating staff of power facilities. They are considered to be
logical interlocks and are performed manually as "live
interlocks". The automation of such manual operations is an
essential task. However interlocks are programmed in
controllers mainly using algorithms following the traditional
methods of relay switching circuits which are based on the
Boolean algebra and decision tables. These methods do not
make enough use of the capabilities of programming and are
not always suitable for the implementation of complicated
logical interlocks.
Despite the fundamental role of switchover interlocks in the
operation of an electrical network its theory has not been
completed. Attempts to describe an interlock as a finite state
machine have shown that the classical methods of the
automata theory are not sufficient for this [4], [5]. Now it is
more appropriate to apply the agent approach to an interlock
mechanism that is to consider it as a logical agent possessing
a model of the environment and making decisions to enable or
disable the interlock based on a set of logical rules [18].
Abstract
The problem of the design of programmable systems of
operational switchover interlocking in electrical networks is
considered. A solution based on the graph algebra extended by
special operations and the theory of logical inference is
proposed. The solution is invariant under the topology of the
switchgear of substations. The mathematical formalization of
specific and generic interlock rules is described. A technique
of an automatic conversion of generic rules into specific ones
and the application of generic rules the interlock conditions of
which are determined by the topology of the electrical circuit
and the state of the switchgear is demonstrated.
Keywords: Electrical Network, Operational Supervisory
Control Of Electrical Networks, Switchover, Interlock Rule,
Logical Interlock, Knowledge Base, Logical Inference,
Logical Agent, Electrical Circuit Topology Analysis,
Topology Processor, Breaker, Disconnector.
Introduction
Manual or automatic control actions interlocks are widely
applied in process control. It is used to prevent a violation of
the normal process workflow, damage to the process
equipment, damage to the health and safety of the staff,
material damage, a reduction of the process safety margin.
Historically the need for interlocking was caused by the
mechanization of technological processes. Actions performed
by a machine may or may not be acceptable depending on the
state of the process, environment and specific conditions. The
simplest type of interlocking is a "live interlock" done
manually by an operator. During the industrial revolution of
the XVIII – first third of the XIX centuries mechanical
interlocks were implemented. In the second half of the XIX
century electromechanical interlocks were introduced. In the
XX century the engineering of interlocks was dominated by
relay circuits. In the last quarter of the century their
replacement by automation techniques based on
programmable controllers begun.
Interlocks are irreplaceable in the operation of electrical
networks. Their wide use in the power engineering started in
the beginning of the XX century together with the
construction of power systems. In 1940 the power engineering
specialist V.A. Rosenberg from Leningrad addressed the
problem of the general theory of the logical design of
interlock devices [17], [12]. The technique of relay switching
proposed by him utilised the analogy of a set of serial and
parallel connections with the Boolean algebra (Note 1). In the
next few decades the Boolean algebra became the
mathematical basis for the logical design of relay switching
2007
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 3 (2016) pp 2007-2015
© Research India Publications. http://www.ripublication.com
The paper deals with the methods of formalization of the logic
of the behavior of program interlock agents and their
algorithmization for the implementation in software (Note 4).
Such interlock agents are supposed to be placed to
programmable controllers and computers and enable or
disable control commands to switching equipment depending
on the current conditions.
where "SwitchOn" is the command "switch on", "Discon" is
the device type "disconnector", Status("G1") is the status of
the device G1 and "Off" is the device status "open". The fact
that the disconnector D1 is adjacent (in this case directly
connected) with the grounding switch G1 is not reflected in
the rule (2). There is no need for this here as the specific
disconnector D1 is referenced.
A substation may have a few tens of such device pairs as a
grounding switch with the adjacent disconnector. In the area
of an electrical network managed from one control center their
amount may be hundreds and thousands. For all such pairs the
interlocks of the grounding switch and the disconnector are
given by similar rules in the form (2). In practice all these
similar rules are considered as specific cases of one generic
rule: "If the grounding switch is open then turning on the
adjacent disconnector is allowed".
The formalized form of this generic rule differs from the
specific rule (2) in that it contains a variable disconnector
identifier DevId rather than a constant one. The constant
grounding switch identifier G1 is replaced by the function
GrSwId (DevId) taking the disconnector identifier as an input
parameter and returning the identifier of the adjacent
grounding switch:
Methods of mathematical formalization of the rules
of switchover interlocks
Structure of the rules of switchover interlocks
If the interlock agent is considered as a finite state machine
then its input signals are commands to change the state of the
device protected. The reaction of the state machine to an input
signal is reduced to either let the command pass unchanged or
discard it. The decision whether a command is allowed or not
is made by the interlock agent depending on the environment
conditions. In the general case the rule to allow a command
Com to perform an operation Oper can be written as:
(Com == Oper)  Cond(Oper, EnvironState)  Enable(Com).(1)
Here the expression (Com == Oper) is a predicate determining
the applicability of the rule (1). It is equal to TRUE if the
command Com matches the operation Oper the lock for which
the rule (1) describes. Here and later the double equal sign
"==" denotes a comparison predicate, a single equal sign "="
denotes an assignment.
The predicate Cond(Oper,EnvironState) in the rule (1)
describes whether the operation Oper is allowed given the
current state of the environment EnvironState, Enable(Com) is
a predicate describing whether the command Com is allowed.
The environment is mainly understood as the system under
control in which the operation Oper is performed. The term
"environment state" may also include the state of the control
process (checks of device statuses, information exchange with
the staff and so on) and the readiness of the operational staff
(for instance making sure that safety glasses and gloves are
worn).
A real interlock agent acts on specific signals and protects
specific pieces of equipment. In this sense every such agent is
unique. Its behavior must be described by individual (or
instance) logical rules which take into account all the specific
factors influencing the decision on whether or not to allow the
operation given.
In the rule (1) the variable Oper is characterized by the
operation type OperType, device type DevType and the
specific device DevId:
Oper = (OperType, DevType, DevId),
where OperType can be "switch on", "switch off", "check for
failures", "unlock" and so on and DevType can be "breaker",
"disconnector", "grounding switch" and so on.
Here is a simple example of an individual rule for enabling a
switchover: "If the grounding switch G1 is off then turning on
the adjacent disconnector D1 is allowed". In the formalized
form (1) this rule can be written as:
(Com == ("SwitchOn","Discon","D1")) 
(Status("G1") == "Off") Enable (Com),
(Com == ("SwitchOn", "Discon", DevId) 
(Status (GrSwId(DevId)) == "Off")  Enable(Com) . (3)
To apply the generic rule (3) it must be first converted to the
instantiated rule of the type (2) using the given parameters of
the command Com = (ComType, DevType, DevId) where
ComType is the command type having the same values
domain as the parameter OperType. The interlock agent
calculates the function GrSwId(DevId) using its own
topological model of the electrical network.
Generic interlock rules are listed first of all in the general
interlock instruction on switchovers in electrical networks of
the Russian Federation [10]. They also follow from the
requirements of other technical regulations on operational
supervisory control of electrical networks [8], [11]. In
addition to this if a scheduled switchover is preceded by a
change of settings of protection units then the corresponding
requirements must be given as generic interlock rules too.
In the rule (1) in the general case the condition for operation
permit Cond(Oper,EnvironState) is a logical combination of
elementary predicates of the state of the environment of the
form Val(Param)  Dom(Param) where Val(Param) is the
actual value of the parameter Param of the state of the
environment before the execution of the operation Oper or its
expected value after the completion of the operation,
Dom(Param) is the acceptable region of Param. The expected
values are determined by the simulation of the operation in the
model of the system under control. In particular the
elementary predicate can have the form of comparison
Val(Param) == Const(Param) or Val (Param) < Const(Param)
where Const(Param) is a pre-defined reference value of
Param. The composite condition Cond(Oper,EnvironState) is
obtained by the combination of such elementary predicates by
logical operators "and", "or" and "not".
To formalize the process of logical inference it is convenient
to move the disjunction operations in the predicate
(2)
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© Research India Publications. http://www.ripublication.com
Cond(Oper,EnvironState) from the structure of the rule to the
structure of the relations between the rules. This should be
done both for specific and for generic rules. Consequently
instead of one rule for enabling an operation there are several
rules for the operation connected to each other disjunctively
while each rule does not contain disjunction operations itself.
To do this the predicate Cond(Oper,EnvironState) produced
by a combination of Boolean operations is written in the
normal disjunctive form:
Cond (Oper, EnvironState) = C  C  …  CK ,
Instantiation means that the current values characterizing the
system state must be determined by querying the database and
performing calculations for their comparison with each other
or corresponding reference values.
Data structures and the operations of the switching circuit
analysis
Generic elementary locks are mostly expressed by switching
circuit topological predicates. This name is applied to
predicates which compare the topology parameters of a circuit
with constants or with each other. A topology parameter is a
function of an element or a group of related elements of a
circuit determined by the topology of the circuit and the state
of the switches ("closed/open"). An example of a topology
predicate is a comparison predicate (Status(GrSwId(DevId))
== "Off"). Some topology parameters of a substation are by
themselves important for the monitoring of the state of an
electrical network. They are also referenced in the rules of
switchover interlocks. Methods of their calculation are
presented in [7]. Together with them the rules of switchover
interlocks contain such topology parameters that are needed
for the rules only.
Methods of the calculation of topology parameters and
switching circuit topological predicates are referred to as the
switching circuit analysis. The calculations are based on a
special set of operations on graphs – graph connectivity
algebra. Its basis consists of six binary operations on
undirected graphs:
AB – union of graphs A and B;
A & B – intersection of graphs A and B;
A B – difference of graphs A and B;
A B – increment of graph A through graph B;
(7)
A ^ B – simple closure of graph A through graph B;
A || B – biconnected closure of graph A through graph B.
(4)
where the predicates C, C, …, CK contain only negation and
conjunction operations. These predicates depend on the same
arguments Oper and EnvironState as the predicate Cond. The
arguments are omitted in the expression (4).
If all the terms but one are in turn removed from the
expression (4) then instead of one rule (1) a set of K rules is
obtained:
(Com == Oper) C(Oper, EnvironState)  Enable(Com) ,
(Com == Oper)  C(Oper, EnvironState)  Enable(Com) ,
…………………………………………………………… (5)
(Com == Oper) CK(Oper, EnvironState)  Enable(Com) .
Each of these rules contains only negation and conjunction
operations. The combination of the rules (5) is interpreted
disjunctively. After the calculation of the right parts of these
rules the disjunction of the results is calculated.
So we assume that in each of the rules (5) the condition
Ck(Oper,EnvironState) is a conjunction of simpler conditions.
Let us express these simpler conditions through their
negations, and so we obtain:
Ck(Oper, EnvironState) = ┐Lk,1  ┐Lk,2  …  ┐Lk,nk.
The first three operations – union, intersection and difference
– are well known in the graph theory. The operations of
increment, simple closure and biconnected closure are
specially introduced for the analysis of the graph topology.
The increment AB of the graph A in the graph B is a union
of A with only those edges (where the edge is considered as a
graph itself) of B at least one end of which belongs to A. The
simple closure A^B of the graph A by the graph B is a union
of A with those connected components of B which have a
non-empty intersection with A. A method of software
implementation of these operations is pointed out in [7].
The biconnected closure A||B of the graph A by the graph B is
a union of A with those biconnected components of AB
which have a common edge with A. This is equivalent to the
union of A with all simple circuits of AB which have a
common edge with A. The classical method of the analysis of
biconnectivity of undirected graphs is presented in a number
of graph reference manuals [16], [1], [19], [14]. In [6], [25] an
efficient algorithm of the calculation of blocks of a graph by
using a fundamental set of circuits is proposed.
The symbol  denotes an empty graph. The expression G > 
means that the graph G is not empty. The operations (7)
together with some graph transformation operations represent
the operational basis of the Unified topology processor – a
(6)
The arguments of the predicates Lk,1, Lk,2, …, Lk,nk are Oper
and EnvironState.
In the equality (6) the predicates Lk,1, Lk,2, …, Lk,nk can be
interpreted as elementary logical locks of the command Com.
The particular lock affects the device DevId if the
corresponding predicate Lk,j is equal to TRUE, j [1…nk]. For
example the elementary logical lock in the rule (3) is the
predicate ┐ (State(GrSwId(DevId)) == "Off"). It means that
the grounding switch adjacent to the disconnector DevId is not
open (that is closed if it is working properly).
If at least one lock Lk,1, Lk,2, …, Lk,nk is active then the
corresponding predicate ┐Lk,j is equal to FALSE and the
resulting conjunction (6) is equal to FALSE. This means that
the k-th rule in the set of rules (5) does not enable the
command Com. However the command is overall locked only
if there is no alternative clearance in any of rules (5).
The elementary logical locks can be defined such that they do
not depend on each other. In specialized instance rules the
elementary locks are expressed by instantiated predicates. In
generic rules the elementary locks are predicates with variable
arguments and must be instantiated before their application.
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software agent providing the solution of graph tasks for the
operational supervisory control of electrical networks [24].
The data for the switching circuit analysis come from the
description of the topology of the connections of devices in
the database of the software interlock agent. The most
complete topological model of an electrical network is given
by the standard CIM (Common Information Model) (IEC
61968; IEC 61970). The present paper uses a less detailed
model which is still sufficient for the demonstration of the
methods of the switching circuit analysis. It is the graph
stellar model of an electrical network or stellar graph. In this
graph each power equipment device is represented by an
undirected starred graph. The central vertex of the star
represents the device itself while the outer vertices are its
connections with other devices. A star has as many edges as
there are connections of the device concerned with the
neighboring devices.The central vertex of the star is later
referred to as the device node, the outer vertices – connection
nodes.
For example a breaker or a disconnector is represented by a
double-edge star, a grounding switch – by a single-edge star,
with the central vertex corresponding to the ground, a double
pole transformer – by a double-edge star, a triple pole
transformer – by a triple-edge star. A bus section is
represented by a star having as many edges as there are
attachments to that bus section. A power line without spurs is
represented by a double-edge star and so on.
In the text below the stellar graph of the entire electrical
network under consideration is denoted by Net, the set of the
nodes of all power lines within the electrical network is
denoted by LinesSet, a subgraph of Net representing a single
power facility (substation or power plant) is denoted by
ObjNet. When evaluating many switching circuit topological
predicates it is sufficient to limit the switching circuit analysis
to one power facility only that is to ObjNet.
The switching circuit analysis calculates various subgraphs of
Net. The initial data for the calculation are the certain subsets
of the vertices of Net. They are obtained from the database by
appropriate queries. If the database is a relational one then
SQL queries can be used. Table 1 lists the designations of the
subsets used in the examples considered later in the paper. All
of them are subsets of the vertices of ObjNet.
Application of the rules of switchover interlocks
Examples of the calculation of the switching circuit
topological predicates of the elementary locks
Below the application of the switching circuit analysis for
instantiating generic lock rules is demonstrated in three
examples.
Example 1. The lock of a switchover of a disconnector if the
adjacent breaker is closed
A generic condition for a switchover of a disconnector is the
lock to operate it if the adjacent breaker is closed. There are
exceptions to this rule but it is considered to be basic.
Technologically it follows from that a load current can flow
through the serial connection of the closed disconnector and
the closed breaker and then a switchover of the disconnector
is generally speaking unacceptable. In the 35 kV electrical
networks and above the load current can be commutated by
breakers but cannot be commutated by disconnectors which
do not have a shunt circuit (see Example 3).
Mechanical and electromechanical lock systems are widely
used as interlocks for disconnectors with the adjacent breakers
[10]. The general logic-topology model of an interlock for a
disconnector with the adjacent closed breaker is considered
below.
Let DiscId be the central vertex of the double-edge star of the
disconnector which is scheduled for a switchover and
AdjClosedBrSet(DiscId) be the set of the closed breakers
adjacent to the disconnector. The switchover lock condition is
expressed by the statement that this set is not empty:
AdjClosedBrSet (DiscId) > .
The set AdjClosedBrSet(DiscId) has to be found. The
disconnector DiscId has two poles as the connection nodes.
Let us denote this set consisting of two elements by
DiscPoles. In the stellar model it is expressed by the formula
DiscPoles = DiscIdObjNet – DiscId .
The breakers adjacent to the diconnector DiscId are connected
to it via the poles given by the set DiscPoles. The set of these
breakers is expressed by the formula
(DiscPolesObjNet) & BrSet.
Mostly this set contains a single element. From the last
formula AdjClosedBrSet(DiscId) can be found:
AdjClosedBrSet(DiscId) = (DiscPolesObjNet) & BrSet &
SwOnSet.
Table 1: Designations of the initial sets for the switching
circuit analysis within a single power facility
Designation Definition
EquipSet Nodes of the main power devices (power
transformers, bus sections, power line entry
points, reactors)
BusSet
Nodes of the bus sections
SwSet
DiscSet
SwOnSet
SwOffSet
Nodes of the switches
Nodes of the disconnectors
Nodes of the switches which are on
Nodes of the switches which are off
GenSet
Nodes of all generators in a power plant
Example 2: The lock of switching on a grounding switch
without a visible break.
One of the generic conditions for the authorization to switch
on a grounding switch is that it must have a "visible break"
that is a ring of open disconnectors isolating the area of the
network scheduled for grounding from the live network. A
visible break is necessary to ensure a fault-free closure
operation of the grounding switch and to provide the safety of
the operational staff. Without a visible break a connection of
power sources to the ground may occur if the breaker which
isolates the grounded area of the circuit is switched on
unintended or by mistake.
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ClosedDiscSet (Node) = (Node ^ (ObjNet (DiscSetNode)))
&SwOnSet .
(11)
Let us consider a subgraph g of an undirected graph G. A set
of such vertices of G that do not belong to g and are connected
by at least one edge of G to a vertex of g is called an outer
vertex boundary of the subgraph g in G. From the definition it
follows that the outer vertex boundary of a subgraph g in a
graph G is given by the formula g*Gg.
Let Node be any vertex of the graph ObjNet. The "visible
break" for Node is an outer vertex boundary B of a subgraph g
of the graph ObjNet in this graph if g contains Node and does
not contain power sources and the boundary B consists only
of the central vertices of the stars of open disconnectors.
Within g there may be open or closed breakers and grounding
switches as well as closed disconnectors.
Let us consider the least graph IsolSite(Node) within ObjNet
such that it contains Node and has a ring of open
disconnectors as its outer boundary. This graph is given by the
formula
This formula gives the least possible graph containing Node
and having the boundary of open disconnectors after all
disconnectors in ClosedDiscSet(Node) have been switched
off. However a visible break may enclose a graph which is not
the least possible and contains closed disconnectors.
Switching them off may result in a smaller graph having a
visible break. In contrast to the formula (11) the formula (8) in
the general case does not give the least possible graph which
can be obtained by producing a visible break. It gives the least
graph from those ones containing Node which are already
enclosed by visible breaks if such graphs exist.
A visible break for a grounding switch is defined as the
presence of a visible break of the connection of its connection
node to neighboring devices. Let us denote the central vertex
of the single-edge star of the grounding switch by GrSwId.
The connection node Node of this grounding switch to
neighboring devices is given by the formula Node =
GrSwIdObjNet–GrSwId.
Let us first assume that the grounding switch GrSwId is not
one of a power line. Then the presence of its visible break is
checked only within the power facility where it is located. The
presence or absence of a visible break for GrSwId can be
obtained from the formulas (8), (9) and (10). If a visible break
is absent then the set of disconnectors which have to be open
to produce the visible break required can be found from the
formula (11).
If GrSwId is a grounding switch of a power line without spurs
then it must have visible breaks both within its substation and
on the other end of the power line. A grounding switch of a
power line with spurs must have visible breaks within all
substations connected to the power line and its spurs. For the
calculation of the visible breaks in these cases the formulas
(8) – (11) can be used. The graph ObjNet has to be replaced
by the graph Net covering that area of the electrical network
which contains all the power facilities connected to the power
line and its spurs. If the formulas (8) – (11) are applied to a
grounding switch of a power
line the sets
UpstreamLineEntries, SwOnSet, SwOffSet and DiscSet have
to extend to that area too.
IsolSite(Node) = Node ^ (ObjNet  ((SwOffSet & DiscSet) 
Node)) .
(8)
Let us denote by UpstreamLineEntries the set of the entry
points of the power lines supplying a substation. The elements
of this set can be seen as power sources for the substation
which the set is calculated for. The set is determined by the
connections of the substation to power sources within the
entire electrical network containing a multitude of power
facilities. As UpstreamLineEntries depends on the current
state of the switches in the entire electrical network it has to
be updated on every switchover in the network. In [7] a
method referred to as the substation zone method to minimize
the calculation of UpstreamLineEntries upon a switchover is
presented. Its idea is to represent each substation zone by a
separate node where a substation zone is a part of the
substation equipment within which devices are electrically
connected but isolated from devices in other similar parts. The
nodes representing zones of different substations are
connected to each other by arms corresponding to power lines.
The substation zone graph obtained in this way fully defines
the set UpstreamLineEntries for each substation. Due to such
a representation it is not necessary to recalculate the full
substation zone graph each time when a single or multiple (in
the case of a fault) switchover occurs in the network. It is
sufficient to update the representation of only those zones
which are affected by the switchovers. This results in only a
small number of vertices being merged or split in the zone
graph.
Let us denote the set of the power sources within the graph
IsolSite(Node) by SS(Node). For substations it is given by the
formula
SS(Node) = IsolSite (Node) & UpstreamLineEntries . (9)
A visible break for the node Node exists when SS(Node) is
empty. For power plants SS(Node) is given by the formula
Example 3. The lock of switching over a disconnector under
the load_with the operational availability of the shunting
breaker.
An important generic condition for the authorization of a
switchover of a disconnector under the load is that the
disconnector must have a shunt circuit. It is a closed circuit
with a low resistance connecting the poles of the disconnector
but excluding the disconnector itself. It mainly consists of
closed breakers and disconnectors as well as bus sections.
Such a circuit prevents the occurrence of an arc if the
disconnector is switched on or off under the load. The
elements in the shunt circuit must be switched on in such a
reliable way that it is impossible to switch them off
accidentally during the execution of an operation. This is
achieved by a prior disconnection of the power supply circuits
of the drives of the switching devices in the shunt circuit.
SS(Node) = IsolSite(Node) &(GenSetUpstreamLineEntries).
(10)
If Node does not have a visible break then the set of closed
disconnectors which have to be open to produce the visible
break required is given by the formula
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This interlock rule is mainly applied in the Russian electrical
networks when an attachment with a single breaker to a
switchgearis switched over from one bus bar to another one in
switchgears with a tie breaker (see Fig. 1). Normally in such a
circuit each attachment is electrically connected to one of the
two busbars by a disconnector. Switchovers are performed
without an interruption of the power supply to the customers.
For example to switch the line L2 from the bus BB1 to the bus
BB2 the disconnector BD22 has to be closed and then the
disconnector BD21 opened. These switchovers are performed
when the both disconnectors are under the load. Therefore
each disconnector must have a shunt circuit during the
execution of the switchover operation. In Fig. 1 the shunt
circuit for BD22 consists of the bus disconnector BD21, bus
sections BB1_sec1, BB1_sec2, BB2_sec2 and BB2_sec1,
sectionalizing breakers SBr1 and SBr2 and their disconnectors
as well as the tie breaker TBr and its disconnectors TBrD1
and TBrD2. During the switchover of the disconnector BD22
all the switching devices in this circuit must be closed and the
power supply circuits of their drives disconnected.
Let us note that switching every attachment results in a
switchover of two disconnectors under the load when the
adjacent breaker is closed. This contradicts to the rule from
the Example 1 if the disconnectors being switched do not have
shunt circuits. That is why in this case the requirement of
interlocking the disconnector being switched and its adjacent
closed breaker is temporarily cancelled. If there are hardware
interlocks for this rule they are temporarily overridden. The
reduction of the reliability of the operations caused by this
cancellation is compensated by the introduction of an
additional reliability mechanism that is the shunt circuit
consisting of reliably closed switching devices. The shunt
circuit prevents the occurrence of the technological fault – that
is the occurrence of an arc in the disconnectors being switched
– which the temporarily disabled basic rule from the Example
1 is aimed at.
refinements of the interlock rules are introduced on the
principle of "exceptions from exceptions" (Note 5).
To write the generic interlock rule of the current example in
the mathematical form the operation of biconnected closure of
graphs has to be used. Let us denote by ShuntGraph(Switch)
the union of all closed circuits (considered as graphs) which
shunt a device with the device node Switch and has a
sufficiently low resistance. The double-edge star representing
this device is expressed by the formula SwitchObjNet. The
graph ShuntGraph(Switch) is given by the formula
ShuntGraph (Switch) = ((SwitchObjNet) || (ObjNet –
(EquipSet–BusSet–SwOnSet))) – Switch.
(12)
As mentioned above the symbol "||" denotes the operation of
the biconnected closure of graphs. Both edges of the star
representing the device with the device node Switch do not
belong to the graph (12). The set of the switching devices
shunting Switch is given by the formula
ShuntGraph (Switch) & SwSet.
After the evaluation of this set it should be checked that every
device in it is not ready for operation that is that the power
supply circuit of the device drive is disconnected. Therefore it
is necessary to make this information available to the interlock
agent.
The knowledge base of the interlock agent
Specialized instance interlock rules do not contain language
elements which are beyond the competence of an ordinary
power engineering specialist. These rules can be created and
edited by such a person. For this an editor program can be
developed which allows one to build instance interlock rules
by selecting their elements from menu lists or pointing to
them on the circuit.
Generic interlock rules have a more complex semantic
structure because these rules need to contain formalized
definitions of the devices determining whether or not a
switchover command is allowed. In the current state of the
development of the systems of programmable interlocking
formalization of such definitions by a power engineering
specialist without a software developer is not possible.
However the number of generic interlock rules originating
from technical regulations is less than 100-150. That is why
now generic rules are implemented as program procedures
while the user is given a possibility to modify the rules by
adding exceptions. To add an exception to a generic rule the
user selects this rule in the knowledge base and specifies a
device (pointing to it on the circuit or selecting from the
menu) and the operation type for which the rule selected
should be ignored.
The examples given above demonstrate the technique of
making specialized instance rules from generic ones by means
of the switching circuit analysis. Using the basic graph
operations (7) many other generic interlock rules can be
transformed to instance ones.
If an interlock agent protects a fixed set of devices then
generic interlock rules can be transformed to instance ones
only once when the agent is initialized. However if an agent
protects a large number of devices with various connection
circuits then storing a large number of instance rules in its
memory may be inefficient. Then the transformation of
generic rules to instance ones should be done just before their
Figure 1: The circuit of a switch gear with a tie breaker TBr
prior to switchovers. The breakers depicted by solid squares
are closed.
Effectively the basic rule from the example 1 is refined in the
following way: it should be applied only if the disconnector
being switched does not have a shunt circuit with a
sufficiently low resistance. If a proper shunt circuit exists an
exception from the basic rule can be made. Successive
2012
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 3 (2016) pp 2007-2015
© Research India Publications. http://www.ripublication.com
application. Such an agent can be referred to as adaptive.
Electromagnetic interlocks built using relay switching circuits
protect one or several switching devices in a switchgear. It is
advisable to limit the switching devices protected by a
adaptive agent to the devices within one switchgear only. But
in the general case the agent has to take into account the status
of equipment outside the switchgear. The agent inner database
has to contain the part of the network model necessary for that
including its topology.
After the instantiation generic rules an agent holds a variety of
instance interlock rules covering the interlock requirements
for the devices protected by it. The agent applies these rules to
the collection of facts describing the structure and the state of
the system under control. This is done by logical inference
using the rules of logical inference and a solver program.
Q  ┐Lk,1  ┐Lk,2  …  ┐Lk,nk = FALSE .
In this case the implication (13) is true both if E is true and if
E is false. Therefore it is impossible to decide whether or not
to enable the command based only on the rule (13) for given
k. The solver program has to apply other rules from the set
(5). If any of the rules results in E = TRUE, then the
command can be allowed as all the interlock implications with
the same consequent are interpreted disjunctively.
If after the evaluation of all rules in (5) the result is
undetermined then the command Com should be considered
as disallowed. This result follows from the adoption of the
Closed-World Assumption [9], [3], [18]. It asserts that those
and only those statements (implications and facts) are true in a
model (problem domain) described by a knowledge base K
that are either present in K or can be deduced from K by the
rules of logical inference. All other statements about the
problem domain concerned are considered to be false. Thus if
none of the rules (5) produces E = TRUE then the command
Com should be rejected.
Logical inference of switchover locks
The scheme of logical inference for the application of instance
interlock rules is relatively simple. It is shown above that the
clearance conditions of the command Com =
(ComType,DevType,DevId) are formalized in the form of a
set of alternative rules (5) having the same consequent
Enable(Com). This set of rules is interpreted disjunctively
which corresponds to the generally accepted disjunctive
interpretation of the rules with the same consequent in
knowledge bases [18].
Let us assume that the rules of the set (5) are instantiated.
Instantiating the predicate Enable(Com) consists in the
substitution of the values of the parameters ComType,
DevType and DevId into it. Let us denote the instantiated
predicates (Com == Oper) and Enable(Com) by Q and E
respectively. Then the k-th rule in (5) can be written as
(Q  ┐Lk,1  ┐Lk,2  …  ┐Lk,nk)  E,
Discussion and conclusion
The paper describes the algorithms of such switchover
interlocks in electrical networks which can be referred to as
switching or topological. They are determined by the circuit
topology and the states of switching devices. Another
important class of switchover interlocks in electrical networks
is formed by a set of interlocking conditions depending on
power flow (power flow interlocks). They are determined by
conditions of the form V < C or V > C where V is the current
value of a continuous power flow parameter and C is a limit
value of this parameter. Voltage, frequency, current, active
and reactive power flow and so on in various points of an
electrical network can all be such continuous parameters for
monitoring. The values are obtained by an automatic state
estimation (approximation) of the power flow using the
current measurements. Methods of implementation of power
flow interlocks have specific features and are beyond the
scope of the present paper.
The application of graph connectivity algebra for
algorithmization of generic switchover interlock rules
significantly simplifies the logic of the implementation of
interlocks. To verify this it is sufficient to compare the circuits
of relay switching interlocks of switching devices [10] with
the interlock algorithms expressed in terms of the graph
algebra. Examples of such algorithms are given in the paper.
Logic module is the most unreliable component of relay
switching interlock circuits [26]. In addition to this an
individual relay switching interlock circuit has to be built for
every switchgear scheme while interlock algorithms in terms
of the graph algebra are generic for a wide class of switchgear
schemes and invariant under their topology.
In [26] it is proposed to resolve the issue of the complexity of
the logical design of the logic modules of relay switching
interlock devices by automating the design for the circuits of
switchgears given. The method of the transformation of
generic interlock rules to instance ones by the switching
circuit analysis presented in the paper is equivalent to the
automation required. A combination of instance interlock
(13)
where the predicates Lk,1,Lk,2,…,Lk,nk are assumed to be
instantiated too.
According to the definition of implication operation if the
implication is true and its antecedent is true then its
consequent can be only true. The latter statement is essentially
the rule of logical inference Modus Ponens – "the rule of
Implication Elimination":
X Y, X .
Y
As the implication (13) is stored in the knowledge base it is
assumed to be true. If the value of each instantiated predicate
Q,┐Lk,1,┐Lk,2,…,┐Lk,nk is equal to TRUE then their
conjunction is also equal to TRUE. That means that the
antecedent of the rule (13) is true. Then according to the
inference rule Modus Ponens the consequent of the rule (13)
is equal to TRUE and the command Com is allowed.
The TRUE value of all predicates ┐Lk,1,┐Lk,2,…,┐Lk,nk means
that all predicates Lk,1, Lk,2, …, Lk,nk are false. The latter
means that none of the elementary logical locks is active in
the current state of the circuit. If any of the locks is equal to
TRUE, i.e. if Lk,i = TRUE for any i  [1…nk], then ┐Lk,i =
FALSE. So we get
2013
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 3 (2016) pp 2007-2015
© Research India Publications. http://www.ripublication.com
rules for one or more devices provides exactly the same
logical function as the corresponding relay switching circuit.
The switching circuit analysis based on the graph connectivity
algebra allows one to automate the application of logically
more complex interlocks requirements essential for the
technology of switchovers but not implemented in hardware
so far due to the complexity of the logic. The accent in the
implementation of interlocks moves from methods of
hardware implementations to formalization of the reaction
logic of interlock units to control commands. The task of the
logical design of generic interlocks is reduced to logical
formalization of the conditions of their action and the
expression of topological dependencies of device states in the
language of the graph algebra.
The graph connectivity algebra is superior to the Boolean
algebra in other applications as well. In [7] algorithms based
on the graph algebra to calculate the topological parameters of
an operational substation state invariant under the topology of
the switchgear are presented. An extension of the graph
connectivity algebra to directed graphs has made an efficient
method of modelling and analysis of relay switching circuits
possible [2]. It is based on the combination of the circuit
topology analysis and the rules of the action of relay to
contacts. This method allows one to simulate interlocks based
on relay switching circuits on computers or programmable
controllers too. Their computer simulation is necessary in the
modelling of electrical installations and may be useful for the
exchange of hardware interlocks to programmable ones.
These and others applications of the graph connectivity
algebra are an evidence that it is a promising basis of the
Unified topology processor.
contains the results of the research work performed within the
project «The development of an adaptive and coordinating
device for the operating control of switchovers in a smart
electric grid», project No. RFMEFI57514X0077, in the
National Research University of Electronic Technology
(MIET).
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Notes
Note 1.Thework of Rosenberg (Rosenberg, 1940) was the first
publication in Russian where the Boolean algebra was applied
to the logical design of contact circuits. The fundamental
results in this subject which were presented in V.I.
Shestakov's PhD thesis defended in 1938 were published only
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Stanković, et al., n.d.).
Note 2.The definition of the LSL language is presented in
(Tsichritzis, 1976; Ozkarahan, 1986).
Note 3.For example the interlock of switching on a grounding
switch of a power line when the disconnectors on the other
end of the line are closed is not implemented in hardware due
to its complexity (Guidelines, 1979).
Note 4. The paper takes into account S.V. Kartashov's
comments (Executive Committee of the Electricity
Coordinating Council of the Commonwealth of Independent
States, Moscow, Russia).
Note 5. The principle of an addition of "exceptions from
exceptions" or "interpretation of interpretations" is widely
applied in the development of such normative systems as
codes of laws, technical regulations and even religious rules.
Acknowledgments
This work was financially supported by the Ministry of
Education and Science of the Russian Federation. The paper
2014
International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 3 (2016) pp 2007-2015
© Research India Publications. http://www.ripublication.com
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