LOW COST ALTERNATING CURRENT AUTOMATED
CHARACTERIZATION SYSTEM FOR
OPERATIONAL AMPLIFIERS
by
SCOTT MATTHEW GULAS, B.S.E.E.
A THESIS
IN
ELECTRICAL ENGINEERING
Submitted to the Graduate Faculty
of Texas Tech University in
Partial Fulfillment of
the Requirements for
the Degree of
MASTER OF SCIENCE
IN
ELECTRICAL ENGINEERING
Approved
Micheal Parten
Chairperson of the Committee
Ronald Cox
Accepted
John Borrelli
Dean of the Graduate School
May, 2005
ACKNOWLEDGEMENTS
I would like to first thank Mark Irwin and company at Texas Instruments, Tucson,
AZ, for affording me the opportunity to work on this project. It was with Mark’s help
that I was able to find a thesis project that could both benefit Texas Instruments, and keep
my interest for almost one year. I have really enjoyed applying the knowledge I’ve
learned at the University of Florida, Texas Tech University, and while interning with TITucson.
I would also like to thank Dr. Michael Parten and Dr. Ron Cox for their support
and guidance, not only in regards to this thesis project, but also with my professional life
in general. Of course, none of this would be possible without God’s grace and the love
and support of my family and friends. It has been their kind words of encouragement,
along with a lot of work and a little luck, that have brought me success and the
opportunity to earn my Masters Degree in Electrical Engineering.
ii
TABLE OF CONTENTS
ACKNOWLEDGEMENTS................................................................................................ ii
ABSTRACT........................................................................................................................ v
LIST OF TABLES............................................................................................................. vi
LIST OF FIGURES .......................................................................................................... vii
CHAPTER
I.
INTRODUCTION ........................................................................................................ 1
1.1 The Operational Amplifier’s Origin ................................................................... 1
1.2 Chapters summary .............................................................................................. 2
II. THE OPERATIONAL AMPLIFIER ........................................................................... 4
2.1 Definition of the problem.................................................................................... 4
2.2 Automated test solutions..................................................................................... 4
2.3 Definition of the operational amplifier ............................................................... 7
2.3.1 The ideal operational amplifier.................................................................. 9
2.3.2 The real operational amplifier.................................................................... 9
2.4 Testing AC parameters ..................................................................................... 11
2.4.1 Technique for measuring slew rate .......................................................... 12
2.4.2 Technique for measuring bandwidth ....................................................... 13
2.4.3 Technique for measuring overload recovery time ................................... 17
2.4.4 Technique for measuring settling time .................................................... 18
2.4.5 Technique for measuring channel separation .......................................... 19
2.4.6 More about AC testing............................................................................. 20
2.5 Solution to the problem..................................................................................... 20
III. TEST HARDWARE.................................................................................................. 22
3.1 Hardware overview........................................................................................... 22
3.2 Frequency Synthesizer Board ........................................................................... 22
3.3 Test and Measurement Board ........................................................................... 25
3.4 RC Configuration Card ..................................................................................... 37
iii
IV. TEST SOFTWARE ................................................................................................... 39
4.1 Software overview ............................................................................................ 39
4.2 Program flow .................................................................................................... 39
4.3 Microcontroller software .................................................................................. 40
4.4 FPGA software.................................................................................................. 44
4.5 PC software....................................................................................................... 51
V. DATA ANALYSIS FOR REPEATABILITY AND CORRELATION .................... 57
5.1 Frequency Synthesizer Board results................................................................ 57
5.2 Test and Measurement Board results................................................................ 63
5.3 RC Configuration Card results.......................................................................... 66
5.4 Analysis of OPA347 test results ....................................................................... 66
5.5 Analysis of OPA277 test results ....................................................................... 70
5.6 Test time............................................................................................................ 75
VI. CONCLUSIONS ....................................................................................................... 76
6.1 Comparison of test results................................................................................. 76
6.2 Limitations of the system.................................................................................. 78
6.3 Cost savings ...................................................................................................... 79
6.4 Future work....................................................................................................... 79
REFERENCES ................................................................................................................. 81
APPENDICES
A. EXAMPLE MICROCONTROLLER TEST PROGRAMS.................................. 82
B. FPGA SUBSYSTEMS........................................................................................ 103
C. FPGA MAIN GRAPHICAL DESIGN FILES........................................... In Pocket
D. HARDWARE SCHEMATICS .................................................................. In Pocket
iv
ABSTRACT
The purpose of this thesis project was to develop a low-cost automated bench test
solution capable of measuring AC (alternating-current) parameters on single and dual
packaged voltage-feedback operational amplifiers (op-amps). Electrical properties of the
device under test (DUT) are described, along with the methodology used to test these
parameters. The design and implementation of the test hardware is covered. A detailed
explanation of the test software developed is also included. Finally, a statistical analysis
is used to verify that the system is repeatable and accurate in relationship to data taken
manually in a bench setup.
v
LIST OF TABLES
2.1
Comparison of parameters of various TI op-amps ................................................. 11
2.2
Specifications of the TI OPA637 op-amp............................................................... 11
3.1
Gain chart for TI THS7001 PGA .......................................................................... 27
3.2
Specifications for Altera FPGA ............................................................................ 32
4.1
Reserved memory locations for test results ........................................................... 42
4.2
Developed op-codes for onboard communication ................................................. 42
5.1
Recorded frequency and amplitude data for various sine waves........................... 62
5.2
Component values changed on Test and Measurement Board .............................. 64
5.3
RC Configuration Card setup for OPA347............................................................ 66
5.4
OPA347 error and repeatability data of rising-edge slew rate............................... 67
5.5
OPA347 error and repeatability data of falling-edge slew rate ............................. 68
5.6
OPA347 error and repeatability data of overload recovery time (Vcc)................. 68
5.7
OPA347 error and repeatability data of overload recovery time (Vee)................. 69
5.8
OPA347 error and repeatability data for gain bandwidth product......................... 70
5.9
RC Configuration Card setup for OPA277............................................................ 71
5.10 OPA277 error and repeatability data of rising-edge slew rate............................... 72
5.11 OPA277 error and repeatability data of falling-edge slew rate ............................. 72
5.12 OPA277 error and repeatability data of overload recovery time (Vcc)................. 73
5.13 OPA277 error and repeatability data of overload recovery time (Vee)................. 73
5.14 OPA277 error and repeatability data for gain bandwidth product......................... 74
5.15
Average test time for the OPA347 and OPA277 ................................................... 75
6.1
Comparison of automated test results for the OPA347 and OPA277.................... 76
vi
LIST OF FIGURES
2.1
Teradyne Catalyst automated test solution .............................................................. 5
2.2
National Instruments PXI automated test solution .................................................. 6
2.3
Terminal definitions of the op-amp ......................................................................... 7
2.4
Simple three stage model of a typical op-amp ........................................................ 8
2.5
Slew-rate limiting of the op-amp ........................................................................... 10
2.6
Simplified circuitry for AC testing of op-amps ..................................................... 12
2.7
Slew-rate effects on op-amps................................................................................. 13
2.8
Typical amplitude attenuation versus frequency ................................................... 14
2.9
Bandwidth effects on output amplitude ................................................................. 14
2.10
Determining maximum signal amplitude when testing GBW............................... 15
2.11 Slew-rate limiting of large sinusoidal outputs ....................................................... 16
2.12
Overload recovery time effects on op-amps .......................................................... 17
2.13
Settling-time effects on op-amps ........................................................................... 18
2.14
Dual op-amp configuration for testing channel separation.................................... 19
3.1
Block diagram of Frequency Synthesizer Board ................................................... 23
3.2
Layout of the Frequency Synthesizer Board.......................................................... 24
3.3
Layer stack-up of the Frequency Synthesizer Board ............................................. 25
3.4
Layer stack-up of the Test and Measurement Board ............................................. 25
3.5
Block diagram of the Test and Measurement Board ............................................. 26
3.6
Low-pass filter and buffer amp.............................................................................. 27
3.7
Motorola microcontroller and peripherals ............................................................. 28
3.8
Cascade amplifier chain for testing channel separation......................................... 29
3.9
TI LM211 comparator configuration ..................................................................... 30
3.10
Positive peak detector circuit ................................................................................. 31
3.11 Negative peak detector circuit ............................................................................... 31
3.12
Altera FPGA and peripherals................................................................................. 32
3.13 In-circuit programming hardware for the Altera FPGA ........................................ 33
vii
3.14
Altera EPC2 configuration device ......................................................................... 34
3.15
Generation of +2.5VREF and -2.5VREF from +5V................................................... 34
3.16
Relay configuration for supplying the DUT with V+ and V-................................ 35
3.17
DUT socket configuration...................................................................................... 36
3.18
Circuit board layout of the Test and Measurement Board..................................... 37
3.19
Generic RC plug-in card ........................................................................................ 38
3.20
Circuit board layout of generic RC plug in card.................................................... 38
4.1
Memory map of Motorola microcontroller............................................................ 41
4.2
Overview of program flow on Test and Measurement Board ............................... 43
4.3
Subsystems located within the Altera FPGA......................................................... 46
4.4
Overview of program flow in RUNTESTS subsystem.......................................... 47
4.5
Program flow for rising and falling edge slew rate tests ....................................... 48
4.6
Program flow for Vcc and Vee overload recovery time tests .................................. 48
4.7
Program flow for Vcc and Vee settling time tests ................................................... 49
4.8
Program flow for gain-bandwidth product test...................................................... 50
4.9
Program flow for channel separation test .............................................................. 51
4.10
MGTEK’s MiniIDE development environment .................................................... 51
4.11 Settings for the connected PC’s serial communication port .................................. 52
4.12 Monitor splash screen shown upon reset ............................................................... 53
4.13
Results of the HELP command being executed..................................................... 53
4.14 Results of the LOAD command being executed.................................................... 54
4.15
Results of the MD command being executed ........................................................ 54
4.16
Results of the FILL command being executed ...................................................... 55
4.17
Results of the GO command being executed......................................................... 56
4.18
Results of an invalid command request ................................................................. 56
5.1
2kHz square wave output (minimal persistence) ................................................... 58
5.2
2kHz square wave output (infinite persistence)..................................................... 59
5.3
2kHz square wave output (infinite persistence, zoomed in) .................................. 59
5.4
Rising and falling slew rate measurements of 2kHz square wave output.............. 60
viii
5.5
Frequency spectrum of 2kHz square wave output................................................. 61
5.6
Output signal and frequency spectrum of 2MHz sine wave output....................... 61
5.7
Signal characteristics of various sine waves.......................................................... 63
5.8
Rising and falling slew rates of the OPA347......................................................... 67
5.9
Overload recovery times (Vcc and Vee) of the OPA347 ...................................... 68
5.10
Measuring bandwidth of the OPA347 ................................................................... 69
5.11
Rising and falling slew rates of the OPA277......................................................... 71
5.12
Overload recovery times (Vcc and Vee) of the OPA277 ...................................... 72
5.13
Measuring bandwidth of the OPA277 ................................................................... 74
6.1
Knee in output when testing rising edge slew rate of the OPA277 ....................... 77
6.2
Slew rate limiting while testing for gain-bandwidth product ................................ 77
ix
CHAPTER I
INTRODUCTION
1.1 The Operational Amplifier’s Origin
In the early 1930’s, Harry Black worked as an engineer for Bell Labs in New
Jersey. Black, along with other engineers of his time, was faced with the ever-growing
issues of expanding the national telephone infrastructure. The existing vacuum tube
amplifiers used to transmit telephone signals had varying gains due to temperature and
power supply regulation. This resulted in poor volume and distortion on the other end of
a phone line. This issue was well understood, but what could be done about it?
It was well known that passive components (resistors, capacitors, and inductors)
had much better drift characteristics than active components (vacuum tubes, and later
integrated circuits). One morning in 1934, while riding a fairy to work, Harry Black
came about the idea of building an amplifier whose gain was dependent on external
passive components, rather than the active device itself. To achieve this, the amplifier
would need a gain much greater than the desired gain, and a portion of the output would
need to be fed back to the input for gain adjustment. This idea would end up being the
future of feedback theory, and the beginning of what is today known as the operational
amplifier (op-amp).
While Black’s application of negative feedback was a good start, it certainly was
not perfect. An amplifier with such a high gain tends to be unstable when feedback is
applied. By the 1940’s, this phenomenon was pretty well understood, and the solution to
this high gain amplifier would be frequency compensation. Calculations soon proved
difficult, and solutions seemed to be understood only by the best analog engineers. In
1945, H.W. Bode presented a graphical method of analyzing the stability of feedback
systems. With this new found knowledge, electrical engineers across the world were
soon implementing operational amplifiers in a variety of control systems and analog
computers.
1
Op-amps were big and bulky, until Fairchild introduced the transistor-based opamp in the 1960’s. This device, the uA709, became the first commercially successful
integrated circuit op-amp. The major drawback of the device was its need for external
frequency compensation. Most competent engineers could use the device effectively, but
to expand the op-amp’s place in the world it still needed to be made simpler. Soon the
first internally compensated op-amp, the uA741, was released. This device was much
more forgiving than the uA709, and became a major player in the growth of the
semiconductor industry in the coming years. Still today, the uA741 is studied in many
university classrooms, and variants of the device are still used in some consumer
electronics.
There have been thousands of op-amp models released since the introduction of
the uA741, each offering an improvement in performance, stability, reliability, and/or
usability. The latest generation of op-amps covers an entire spectrum of performance,
many tailored to specific areas of application. The op-amp has truly become the
universal analog integrated circuit, and can be found in many, if not most, analog circuits
today [3].
1.2 Chapters summary
Further technical background needed to understand the rest of this thesis project is
covered in Chapter 2. This includes defining the purpose of having an automated test
solution, an explanation of the ideal and non-ideal characteristics of the op-amp, and the
methodology and simplified circuitry used to test the AC parameters of an op-amp.
Chapter 3 examines in detail the hardware chosen to implement the described
tests. The hardware designed consists of a Frequency Synthesizer Card, an RC
Configuration Card, and a main DUT board that will be referred to as the Test and
Measurement board. This board is responsible for the communication interface to the
personal computer, configuring the DUT for each of the tests, and taking the actual
frequency and timing measurements. The DUT itself will be inserted into an 8-pin dualin-line package (DIP) socket. The DIP format was chosen because there are socket
2
adapters available that make the conversion from just about all possible op-amp packages
to a DIP configuration. The Frequency Synthesizer Card replaces the need for an
external function generator, and is interfaced as a plug-in card. The RC Configuration
Card is also interfaced as a plug-in card, and was made for convenience in switching
between different op-amps that require different configurations.
Chapter 4 examines the test software developed. This includes VHDL code
implemented within an FPGA on the Test and Measurement board. It also includes
assembly code run on a Motorola MC68HC12 microcontroller on the Test and
Measurement board. Lastly, it includes an overview of the PC software used on the
connected computer that acts as the interface to the system.
Chapter 5 examines the quantitative results of the fabricated system. A statistical
analysis is performed to support the conclusion that the automated bench solution is
repeatable and accurate in relationship to measurements taken manually in a bench setup.
Chapter 6 gives the conclusion of the thesis by providing the difficulties found
and their solutions, the ways to improve the developed test hardware and software, and
the limitations of the system. This chapter also gives rise to how this system could be
modified to improve measurements and/or test other parameters on op-amps.
The appendices provide software source code and a detailed view of board
schematics.
3
CHAPTER II
THE OPERATIONAL AMPLIFIER
2.1 Definition of the problem
Typically the DC (direct-current) parameters of a precision op-amp are
guaranteed by specifications in the datasheet, while AC (alternating-current) parameters
are merely given as typical values. Therefore, it is commonplace in the semiconductor
industry to only test the DC parameters of an op-amp before selling the part to a
customer. A byproduct of this action is that some customers are bound to receive parts
that meet all DC specifications, but have poor performance in the AC realm of operation.
Although semiconductor manufacturers do not normally guarantee the AC performance
of precision op-amps, it is in the best interest of the company to not only replace poorly
performing parts, but also resolve the issues causing these problems.
2.2 Automated test solutions
In industry, automated test equipment is used to verify the operation of integrated
circuits before being sold to the customer. Automated test equipment tends to be very
large and expensive, but is usually extremely efficient. It could be argued that a manual
bench setup will often yield more accurate test results. However, a well designed
automated system can come close to the accuracy of a manual setup, with greater
precision and repeatability. Having an automated solution also helps remove the factor of
human error. In industry, engineers often take manual bench data, or at least setup the
system for measurements. However, it is commonplace for lesser-trained technicians to
setup ATE solutions and make the required measurements.
4
Figure 2.1 Teradyne Catalyst automated test solution [1].
It is also common for engineers to design automated test bench solutions. Bench
solutions tend to be much less expensive and much smaller than commercial automated
test equipment. However, they typically are not as efficient or accurate. Though not
typically as fast as expensive ATE testers built by manufacturers such as Teradyne, an
automated bench setup can easily return results in a matter of seconds. For example,
automated testing of the DC parameters of a TI OPA2347 op-amp using an SZ Piranha
3610 [ATE] solution takes less than one second. To test the same parameters on a
National Instruments PXI automated bench solution takes less than ten seconds; and to
test an OPA2347 using a manual bench setup can easily take over five minutes. This
illustration shows a great time advantage when compared to a manual bench setup, but
the true value occurs when many parts are in need of testing. It becomes quite expensive
for a company to pay technicians and/or engineers to manually test 1000 parts, for
instance.
The task of designing, manufacturing, debugging, and validating an automated
bench solution is itself a cumbersome task for a test engineer. However, the fruits from
the labor can easily and quickly be realized if the solution is regularly used within the
5
company. The designer of such a system must be well versed in both hardware design
and software development.
Figure 2.2 National Instruments PXI automated test solution [2].
The first step in designing an automated bench solution is to determine what type
of devices will be tested using the system. This will determine the required resolution of
the tester, possibly including voltage, current, frequency, and timing measurements.
Once these specifications are known, a system architecture can be chosen that will
provide such measurement resolutions. The DUT board must then be designed with
suitable components. Functional simulations should be done to minimize design error.
Though some errors can easily be fixed with jumper wires and solder, major errors may
force a revision of the board which will often delay the project completion date. Care
should be taken during board layout, to ensure that parasitic resistances, inductances, and
capacitances are kept to a minimum. Unwanted parasitics can introduce additional error
into the measurements being taken. Additional simulations can be performed to help
insure the integrity of signals within the system.
Another consideration that must be made is how to interface the user to the
system. One option is to include a visual display and keyboard into the design.
However, this usually provides the least flexibility in controlling and upgrading the
system. This also requires the test engineer to run a full-scale operating system of sorts
on the tester. Another option is to interface the system to a personal computer or
6
workstation. This option usually provides the most flexibility. It also allows for simpler
software development within the system, because tools such as Terminal are available for
easy communication between the computer and the tester. Nonetheless, a large amount
of software will need to be written during the development of a robust automated bench
tester. Lots of behind-the-scenes software will need to be developed in order to run the
actual tests and manage data transfers. The test program itself will also need to be
created. The test program should be edited by the user in order to control the hardware as
desired. It is common for there to be many versions of a test program, each customized
to a particular part. It is advantageous to share the same test program if multiple parts
can be grouped by their characteristics. In the case of operational amplifiers, parts can
often be grouped by power supply levels and load (resistive and capacitive) profiles.
2.3 Definition of the operational amplifier
When connected in a negative feedback configuration, the operational amplifier
itself is a very high gain differential amplifier. However, when paired with the correct
passive elements, it becomes an integrated circuit that can be used to perform many
different mathematical functions. The op-amp can be used to add, subtract, integrate, or
differentiate signals. It is also used in many signal conditioning applications, such as
active filters and level shifters. While passive elements such as resistors, capacitors and
inductors only absorb energy, the op-amp is known as an active element because it can
provide AC energy by converting the DC energy of its power supplies [3].
Figure 2.3 Terminal definitions of the op-amp [4].
7
Op-amps have two differential inputs (Vin+ and Vin-), one single-ended output
(Vout), and two DC power supply inputs (V+ and V-). A simple model for a voltagefeedback op-amp consists of three main stages. The first stage consists of a voltage
controlled current source. This stage should ideally amplify only the difference between
Vin+ and Vin-, and reject any signal common to the two terminals. The second stage of
the op-amp is a very high gain (ideally negative infinity) single ended amplifier. A
capacitor is usually placed between the input and output of this stage for frequency
compensation. This capacitive filtering method protects the device from oscillation by
reducing the open-loop gain at high frequencies. Though not all op-amps employ internal
frequency compensation, it aids the IC designer in assuring the device is unity-gain
stable. The output stage of the op-amp acts as an isolation stage, providing a low output
impedance while disconnecting the load from the high-gain stage of the amplifier [5].
Figure 2.4 Simple three stage model of a typical op-amp [5].
General commercial op-amps are most often fabricated on silicon wafers, but
other materials are sometimes used for more application specific parts. Op-amps are
fabricated using either bipolar or CMOS technology. Some expensive op-amps are built
on BiCMOS processes, meaning both bipolar and MOS transistors are fabricated on the
same wafer.
8
2.3.1 The ideal operational amplifier
The ideal operational amplifier acts as a differential amplifier with near-infinite
gain. The device should completely reject any signal common to the two input terminals,
and should only amplify the difference between them. Both of its input terminals have
infinite input resistance, and the output resistance is equal to zero. The output and input
signals should be able to move anywhere between the two power supply rails with perfect
linearity. The device has infinite bandwidth, meaning it would treat a high frequency [i.e.
1 GHz] sinusoidal signal the same as it does a DC signal. The output also has infinite
drive strength, meaning the voltage and current at the output can change instantaneously.
There should be no delay at the output with respect to changes at the inputs. The ideal
op-amp should also introduce no added error or signal distortion.
2.3.2 The real operational amplifier
Different fabrication technologies have led to the development of devices that
come very close to the characteristics of the ideal op-amp, but never quite meet them.
The current into or out of the input terminals (Ib) is rarely zero. Some BJT technologies
may experience Ib’s of more than 1uA, while some CMOS topologies may have Ib’s of
less than 1pA.
Due to the fact that the op-amp has extremely high differential gain, the voltage
difference between the two inputs should be extremely low (ideally zero) when any
voltage exists at the output of the device. Likewise, when the two input terminals of the
op-amp are tied together, the output should ideally be zero volts. However, this is also
impossible to achieve with today’s fabrication technologies. This non-zero voltage
developed between the two inputs is known as the input offset voltage (Vos). Typical
values of Vos range from less than 10uV, to more than 10mV.
Real op-amps also cannot keep up with very fast input signals. As far as small
signal response is concerned, the part’s bandwidth (BW) usually limits the output
amplitude of a high frequency signal. The -3dB point (frequency at which the output
amplitude is 0.707 of the ideal amplitude) for a precision op-amp could be as low as
9
100kHz, or as high as 100MHz. These values often depend on the capacitances internal
to the design. In the case of large signal response, slew rate (SR) limiting usually occurs
when a sharp change in the signal is expected at the output of the device. Because of the
dynamics of the amplifier, its output cannot change in zero time. Therefore, almost
immediately after the input is applied, almost the entire value of the step input will appear
as a differential signal between the two input terminals. Modeling the second stage of the
op-amp as an ideal integrator, the output will slew at approximately vo(t) = (2*I/C)*t,
where I is the current through the first stage, responsible for charging or discharging the
compensation capacitance C [5]. This is one of the reasons that low power parts are
generally slower than their high power counterparts. A general observation of op-amp
design is that as one characteristic is optimized, another parameter is marred.
Figure 2.5 Slew-rate limiting of the op-amp [5].
Other non-ideal characteristics contribute to the op-amp’s non-zero distortion and
noise. It is very hard to design one op-amp that can be very close to ideal for all DC and
AC characteristics. However, optimizing an op-amp for one characteristic is fairly easy
to do. Below is a table showing some parameters (typical) of different Texas Instruments
(TI) op-amps. It can be seen that different models optimize one particular condition, such
as Vos, Ib, or frequency response, but are very non-ideal in other categories.
10
Table 2.1 Comparison of parameters of various TI op-amps [6][7][8].
Vos
Ib
BW
SR
OPA277
10uV
0.5nA
1MHz
0.8V/us
OPA347
2mV
0.5pA
350kHz
0.17V/us
OPA37
0.1mV
15nA
63MHz
11.9V/us
All of the op-amps above can be purchased for under $2 each in large quantities.
With some very complex fabrication technologies, multiple values can be optimized such
as in the TI OPA637.
Table 2.2 Specifications of the TI OPA637 op-amp [9].
OPA637
Vos
Ib
BW
SR
40uV
1pA
80MHz
135V/us
The downside to this excellent op-amp is the cost. This special purpose Difet
industrial op-amp costs over $12 each in large quantities.
2.4 Testing AC parameters
Testing the AC parameters of an op-amp is not an easy task, but a reasonable
circuit can be used to measure most AC parameters [besides noise and distortion]. The
major components needed are an analog-to-digital converter (ADC), digital-to-analog
converter (DAC), buffer, comparators, and a field programmable gate array (FPGA).
A function generator is needed to supply sharp square waves and low-distortion
sine waves. The device under test (DUT) should be configurable – different loads and
different feedback configurations. This can be achieved with high-quality reed relays.
The buffer (i.e. TI BUF634) is used to isolate the DUT from the loading of the measuring
devices. A 4-channel DAC (i.e. TI DAC7644) is used to set various DC voltages as
trigger levels for the comparators. The comparators (i.e. TI LM211) should compare the
DC reference from the DAC and the AC wave from the buffer, and toggle their outputs
(TTL compatible) when the AC wave crosses the DC reference. The FPGA is used to
11
monitor the trigger events and calculate the timing between these events. It can also be
used to talk to the DAC and ADC in the system. The 4-channel ADC (i.e. TI ADS8342)
is available to sample the voltage at the DUT input, DUT output, and BUFFER output. It
is also wise to tie one channel of the DAC directly to one channel of the ADC, in order to
calibrate measurements.
Figure 2.6 Simplified circuitry for AC testing of op-amps.
Some methods of measuring AC parameters are given below. Different test
conditions are specified for different op-amps, so the product datasheet (PDS) and test
plan should be reviewed for any given device prior to testing it.
2.4.1 Technique for measuring slew rate
Typical values to be measured: 0.05V/us – 20V/us
For a DUT powered with ±2.5V, the test plan likely will specify a slow input
square wave of 2Vpp, centered around ground. Therefore, using the 10/90 rule, a
measurement of how long it takes for the DUT output to go from -0.8V to 0.8V would
need to be made. Two channels of the DAC would be programmed to these voltages, and
12
two timing measurements would be taken – the first as the negative voltage comparator
triggers high, and the second as the positive voltage comparator triggers high.
Figure 2.7 Slew-rate effects on op-amps.
The difference in these times is used to calculate the rising-edge slew rate. The
rising-edge slew rate would be specified as ∆V/∆t, and is usually normalized to V/us.
Similarly, the falling-edge slew rate is usually taken, and the device is specified by the
worse of the two values. It should be noted that most datasheets will specify the part to
be configured with unity gain. It is generally possible to test the slew rate of a part over a
smaller voltage range (i.e. -0.5V to 0.5V), as long as the part exhibits slew rate linearity
over its larger specified range.
2.4.2 Technique for measuring bandwidth
Typical values to be measured: 100kHz – 10MHz
The bandwidth test specifies the frequency in which the output amplitude is no
longer within a 3dB error-band of the input while gain configured to +1V/V. Generally, as
the input frequency increases, the output amplitude decreases.
13
Figure 2.8 Typical amplitude attenuation versus frequency [5].
Ignoring the phenomenon known as peaking, the frequency at which the output’s
amplitude is at -3dB, or 0.707 of its input (while gain configured to +1V/V) needs to be
measured. In order to do this, a baseline voltage value must be determined (i.e.
200mVpp). The frequency generator should be programmed to supply a slow (i.e. 1kHz)
200mVpp sine wave to the DUT. VH (i.e. 0.1V) and VL (i.e. -0.1V) should each then be
multiplied by 0.707, and these values should be programmed to two channels of the
DAC. The two corresponding comparator triggers should therefore be toggling as the
sine wave passes above and below these predetermined DC voltages.
Figure 2.9 Bandwidth effects on output amplitude.
A successive-iteration method is then used to find the -3dB point. The input
frequency is first stepped in large increments, and then small increments to determine the
-3dB frequency. Depending on the resolution desired – in this case 10kHz – different
size steps could be used. The input frequency is first set to the lower limit of the system.
14
It is then increased by 100kHz, and the comparators are monitored to see whether they
are triggering. If they are triggering, the -3dB frequency has not been reached. As the
frequency is increased in 100kHz increments and the triggers are monitored, “f ceiling
100kHz” is eventually found. Next, the input frequency is decreased by 100kHz. The
process is then repeated using 10kHz steps. Once either comparator stops triggering, “f
ceiling 10kHz” has been found. This value is decreased by 5kHz (better estimate) and
will be considered the -3dB frequency.
It is important to note that bandwidth is related to small-signal response, while
slew-rate is related to large-signal response. From this note, it should be clear that a
smaller output wave should be used when testing bandwidth than when testing slew-rate.
A simple equation can be used to estimate the maximum peak-to-peak waveform that
theoretically should be used.
Figure 2.10
Determining maximum signal amplitude when testing GBW.
Though this serves as a good estimate, it would be wise to place an oscilloscope at
the DUT’s output to assure the device is not being slew rate limited at the measured
bandwidth. When a sine wave is slew rate limited it generally appears distorted, almost
to the point that it looks like a triangle waveform.
15
Figure 2.11 Slew-rate limiting of large sinusoidal outputs [5].
The small-signal bandwidth of an op-amp is generally defined as a gainbandwidth product (GBW). If the device is tested while configured to provide a gain of
+1V/V, then the GBW is simply the bandwidth measured during testing. However, at a
smaller gain (i.e. +0.5V/V) the measured bandwidth will increase, while at a larger gain
(i.e. +2V/V) the measured bandwidth will decrease. Because of this, the GBW is defined
as the product: GBW = G * BWmeasured.
This inherent property of op-amps is quite useful when testing high-bandwidth
parts. Generally, if the bandwidth of the DUT is greater than the capabilities of the
system, the part can be configured to a gain of +2V/V, and this halved-bandwidth may be
within the limits of the tester. This idea can be extended beyond a gain of +2 V/V,
however special care should be taken at gains larger than +1V/V to assure the part is not
slew rate limited. Reducing the magnitude of the input signal may aid in this situation.
It should be noted that an op-amp configured to provide a gain of -1V/V, will not
result in the same measured bandwidth as when gain configured to +1V/V. The inverting
configuration yields half the bandwidth as the non-inverting configuration. This property
can also be used to our advantage when testing higher bandwidth parts. Most op-amp
datasheets specify the GBW of a device while operating in a non-inverting configuration.
16
2.4.3 Technique for measuring overload recovery time
Typical values to be measured: 0.5us – 50us
The overload-recovery time test measures the amount of time it takes for an opamp to recover from being overdriven to a supply rail. This test more so applies to
bipolar op-amps, however CMOS parts also exhibit this behavior to a certain extent. For
a DUT powered with ±2.5V, the test plan likely will specify a slow input square wave of
5Vpp, centered around ground. Generally, a smaller input square wave, i.e. 1Vpp is also
allowed given that the DUT is gain configured to push the output to the rail. In general,
Vspp = Vipp * G
is needed to satisfy this condition. Care should be taken to assure that the input
waveform does not significantly (>0.5V) go beyond either rail, as this would most likely
turn on ESD protection diodes (if equipped). However, providing slightly more gain than
needed (i.e. +5%) will help ensure that the output is being driven to the rail.
In a bipolar op-amp the output cannot swing to either rail and will likely saturate
1 to 1.5 volts from ±Vs. In the case of CMOS parts, the output will reach a voltage much
closer to the rail.
Figure 2.12 Overload recovery time effects on op-amps.
The ADC should be used to measure the highest voltage at which the output stage
saturates. This value should be attenuated slightly (i.e. 50mV), and passed to two DAC
channels – one monitoring the DUT input and one monitoring the BUFFER output. Two
17
timing measurements are then taken – the first as the DUT input voltage comparator
triggers low, and the second as the BUFFER output comparator triggers low. The
difference in these times is called the Vcc recovery time. Similarly, the Vee overload
recovery time is usually taken, and the device is specified by the worse of the two values.
At a small attenuation such as 50mV, slew rate effects at the output can generally be
ignored. If a significantly larger margin is chosen, an error factor should be subtracted
from the result in order to remove the DUT’s slewing effects from this measurement.
2.4.4 Technique for measuring settling time
Typical values to be measured: 0.5us – 20us
The settling-time test measures the amount of time it takes for an op-amp’s output
to stabilize within a certain guard-band of the ideal output. For a DUT powered with
±2.5V, the test plan likely will specify a slow input square wave of 2Vpp, centered around
ground, with a guard-band of 0.1%. As the input is stepped from -1V to 1V, the output
may experience some ringing or Vdd/Vss bounce. The goal is to measure the time when
the output first enters the guard-band of ±1mV (0.1%), and measure the time when the
output last enters the guard-band. This is usually done by first using the ADC to measure
the DC level of the output once it is settled. This value is then multiplied by 0.999 and
1.001 and those values are written to two DAC channels.
Figure 2.13 Settling-time effects on op-amps.
18
The corresponding comparator triggers are then monitored for both rising and
falling-edge triggers, and the time of the last trigger is recorded. The difference between
these two timing measurements is the 0.1% error band settling-time. Similarly, the test is
usually repeated for the case when the output is stepped from 1V to -1V, and the device is
specified by the worse of the two values. For this test, it is important that the system’s
DAC and ADC are calibrated properly. Various voltage values should be programmed to
the DAC, and the ADC should measure these voltages. The error between these two
readings should be much less than the 1mV guard-band that is under measurement. Also,
it is very important that the comparators used for triggering exhibit a very low offset,
significantly less than the guard-band under measurement.
2.4.5 Technique for measuring channel separation
Typical value to be measured: 120dB attenuation (1 uV/V)
The channel separation test only applies to dual packaged op-amps. Whenever
there is more than one op-amp in a single package, a certain amount of crosstalk will be
present. When a signal is applied to one op-amp channel, a small amount of this signal
will be present in the neighboring channel(s).
Figure 2.14 Dual op-amp configuration for testing channel separation.
To best see this crosstalk, one op-amp channel is fed a large sinusoidal input
signal at a relatively low frequency (for a ±2.5V op-amp for instance, a ±2Vpp 15kHz
sinusoidal voltage signal may be applied). If a large input signal is not available, it is
generally acceptable to apply a small input and gain-configure the output to be a large
19
signal. The other op-amp channel, configured to buffer ground, is then monitored for this
AC signal. This output will typically be gained using an instrumentation amplifier, in an
attempt to separate the crosstalk from the inherent noise. The amount of crosstalk may be
found by either rapidly sampling the output using an ADC, or by adding a peak detector
circuit to the design. A peak detector circuit simply remembers the most positive and
negative magnitudes of an applied AC signal. The circuit’s outputs are two DC voltages.
The channel separation test is a very difficult test to perform in an automated
tester. The small voltages being considered are often no larger than the noise inherent to
the circuit. However, this is exactly what a semiconductor manufacturer is hoping for.
The inability to measure such small crosstalk can be, in essence, a good thing.
2.4.6 More about AC testing
Many other methods of measuring AC parameters have been developed, and some
are more accurate and/or faster. However, the methods introduced present a great priceperformance ratio. Reasonably priced equipment can be used, along with few PCB
components. The great price-performance ratio allows for each test and/or product
engineering group to have their own automated bench tester, rather than using ATE or
manual bench equipment for measurements such as this. Attaining ATE time can prove
to be both cumbersome and costly (as much as $100/hour). Of course, whenever testing
a new type of device, it is necessary to test some sample parts on both the automated
bench tester and a high-speed oscilloscope in order to correlate the measurements, and
assure the tester is accurate and repeatable.
2.5 Solution to the problem
Currently, AC characterization is done by engineers and technicians in a manual
bench setup. This requires the use and setup of external equipment such as function
generators and expensive oscilloscopes. This is both time consuming and cumbersome.
After talking to many engineers and managers, it was evident that an AC automated
bench solution was in need of development.
20
A low-cost system was developed to quickly and accurately characterize the AC
performance of a variety of op-amps. The system will not only be used to characterize
and debug parts returned by customers, but can also be used to characterize new parts as
they come back from the fabrication or packaging facilities. It is desirable that the
system be able to test both CMOS and bipolar parts in the low to medium bandwidth
product portfolio. The system should also be able to test both single and dual packaged
op-amps using a wide range of power supply levels ranging from ±2.5V to ±15V.
Selecting an adequate architecture, designing test boards, and writing test software are all
part of this solution. The final system must be much cheaper than automated test
equipment (ATE) and easily hardware and software configurable.
21
CHAPTER III
TEST HARDWARE
3.1 Hardware overview
The architecture chosen to perform the tests led to the decision of creating three
separate printed circuit boards (PCB). It was decided that a main board, the Test and
Measurement Board, would serve as the backbone of the system. This board consists of
the devices responsible for testing the device, along with the hardware and software
responsible for effective communication with the PC. It also sockets the op-amp that is
under test. The Frequency Synthesizer Board, responsible for generating square and
sinusoidal voltage waveforms, was designed in the form of a plug-in card. Since
different op-amps require different resistive and capacitive loads and feedback elements,
it was decided that a configuration card should be used in the design. A simple RC
Configuration Card was developed to hold all of the required passive elements for each
device or family of devices. Many copies of this board were purchased so that a card
could be dedicated to each device, however only one Frequency Synthesizer Board and
one Test and Measurement Board are needed to build a system. All three PCB’s were
designed using Altium’s Protel DXP software package.
3.2 Frequency Synthesizer Board
All of the tests to be performed require the use of either square or sinusoidal
voltage input waveforms. There are various ways to generate these signals, and a good
amount of research was done to find a cost effective yet accurate method of developing
these waveforms. The MAX038, developed by Maxim, serves as the backbone of the
Frequency Synthesizer Board. It was chosen due to its ability to produce accurate, highfrequency sine and square waves with a minimum of external components. The IC also
generates a SYNC signal, helpful in synchronizing the rest of the AC testing equipment
to the waveform. The MAX038 datasheet contains an application note in which the chip
22
is used in the design of a crystal-controlled, digitally programmable frequency
synthesizer. It claims the circuit is capable of creating sine and square waves from 8kHz
to 16MHz, with 1kHz of resolution [10]. This fits the needs of the AC tester well; a wide
bandwidth capable of testing medium-bandwidth op-amps, with greater resolution than is
desired in the system. A schematic diagram of this application note can be found at
http://www.maxim-ic.com.
Modifications were made to this circuit, including the replacement of some opamps with higher performing precision parts from Texas Instruments. The output filter
scheme was also modified from a hybrid-pi topology to a second-order LRC lowpass
filter. A schematic diagram of the Frequency Synthesizer Board can also be found in
Appendix D.
Figure 3.1 Block diagram of Frequency Synthesizer Board.
The inputs to the system are a 14-bit data bus and one control signal. The 14-bit
data bus contains the desired signal frequency (in kHz) in standard binary format. The
single control signal determines if the desired waveform is a square or sine wave. It
should be noted that the MAX038 is capable of generating high-fidelity square waves
only at relatively low frequencies. At high frequencies it suffers from many of the same
problems as an op-amp, such as limited slew rate and increased ringing. Sine waves
produced by the MAX038 exhibit an acceptable amount of distortion over its entire
frequency range. Whether a square or sine wave is chosen, a built-in automatic gain
23
controller is responsible for generating Vout as a 2Vpp waveform, centered around ground.
The datasheet guarantees the output to be a minimum of 1.9Vpp and a maximum of
2.1Vpp, or 5% maximum error. The resistance of the output driver is guaranteed to be
less than 0.2 ohms, which should yield good results with the output filtering method
chosen. Lastly, the output is specified to have a typical peak-to-peak symmetry of
±4mV.
The SYNC output signal is a TTL compatible logic signal whose rising edge
coincides with the output rising sine wave as it crosses through 0V. When a square wave
is selected as the output, the rising edge of SYNC occurs in the middle of the negative
half of the output square wave, effectively 90° ahead of the output. The SYNC signal has
a 50% duty signal, regardless of the output frequency chosen. Both Vout and SYNC will
be fed to the Test and Measurement Board to aid in testing the DUT. The Vout signal will
be used as the input to the DUT, while the SYNC signal will be fed to the FPGA for
synchronization.
Figure 3.2 Layout of the Frequency Synthesizer Board.
24
The PCB measures 3.40” x 3.38” and was designed using a 4-layer construction:
two signal layers and two power planes. The board uses two power rails, +5V and -5V,
which are both delivered from the Test and Measurement Board via a 3-pin header.
Additional pads were placed in order to do filtering onboard, but these are not used in the
system because all filtering is done on the Test and Measurement Board.
Figure 3.3 Layer stack-up of the Frequency Synthesizer Board.
3.3 Test and Measurement Board
The Test and Measurement Board acts as the backbone of the system, socketing
the DUT itself. The responsibilities of this board include taking in the user’s test
program from the PC, configuring the DUT, programming the Frequency Synthesizer
Board, testing the AC parameters of the op-amp, and returning the values to the user.
The PCB measures 10.03” x 7.52” and was designed using a 4-layer construction: two
signal layers and two power planes.
Figure 3.4 Layer stack-up of the Test and Measurement Board.
Unlike the Frequency Synthesizer Board, the Test and Measurement Board does
not have a dedicated layer for +5V. Instead, the corresponding split layer is used to
25
deliver both +5V and -15V. The Test and Measurement Board needs to be fed +5V,
+15V, and -15V by an external power supply in order to operate. Onboard circuitry
derives the -5V supply, and +2.5VREF and -2.5VREF reference levels that were also
needed. Controlled with the test program, the DUT can be operated at ±5V or ±15V. An
extra power port was added so that the DUT could be operated at any voltage level
desired by the user. This will be particularly useful when testing CMOS parts that
operate at ±2.5V, or while testing the AC characteristics of an op-amp over varying
supply ranges.
Figure 3.5 Block diagram of the Test and Measurement Board.
When testing op-amps powered with different voltage supply levels, the
magnitude of the input voltage waveform will need to be adjustable. For that reason, a
programmable gain amplifier (PGA) was added to the circuit board, and is software
configurable by the user. Three digital inputs [from the microcontroller] tell the PGA to
discretely increase or decrease the magnitude [6dB steps] of the sine or square wave
being fed to the DUT. When a 2Vpp waveform is desired, a software configurable relay
can be used to bypass the PGA. The Texas Instruments THS7001 PGA was chosen for
26
its excellent AC characteristics: low noise, high slew rate, high bandwidth, and fast
settling time.
Table 3.1 Gain chart for TI THS7001 PGA [11].
Before entering the PGA, the signal from the Frequency Synthesizer Board is
conditioned and buffered. A second-order LRC low-pass filter (bandwidth ~ 40MHz)
was used to remove high frequency components from the waveforms. The response time
of the circuit is still fast enough to pass low frequency square and high frequency sine
waves with reasonable fidelity. The Texas Instruments BUF634 was chosen as the
isolation buffer due to its excellent AC characteristics.
Figure 3.6 Low-pass filter and buffer amp.
27
A Motorola MC68HC12 microcontroller (uC) is responsible for configuring the
DUT for each test to be performed. Mechanical relays are used to connect and
disconnect load and feedback elements to the op-amp. These elements can be resistors
and/or capacitors, depending on the device being tested. The DUT can also utilize
different feedback methods, including inverting and non-inverting closed loop
configurations. All relays are driven by Darlington-pair relay drivers controlled by
memory-mapped I/O ports. External EEPROM holds a ‘Monitor’ program, which acts as
an operating system for the microcontroller. This interface allows the user to
communicate between the system and a connected computer. It also serves as a
debugging interface during development of the system.
Figure 3.7 Motorola microcontroller and peripherals.
Since the 16-bit DAC and ADC in the system operate in the range of -2.5VREF to
+2.5VREF, the output signal from the buffer must not exceed these values. When testing
5V CMOS parts, no output scaling should be needed. However, when testing higher
voltage parts, the voltage divider circuit present should be used to ensure that the
maximum possible peak output voltages do not exceed these levels. The voltage divider
circuit is simply two high impedance resistors placed in series, and center tapped for
28
measurement. These resistors were placed in parallel to the load, and should have little to
no resistive loading effects on the DUT.
A relay allows the user to choose this output for measurement under normal
conditions, or switch to another portion of the circuit when testing for channel separation.
During the channel separation test, a null output (buffering ground), is fed to a Texas
Instruments INA111. This low-noise three op-amp instrumentation amplifier is
configured to provide a gain of 501V/V. A TI OPA228, high-precision op-amp, is then
used to further gain this signal by -20V/V. This cascade configuration provides for a
combined gain of about ~|10000V/V|. This high gain should allow for a signal nominally
in the range of uV’s, to be amplified to an easily measurable signal. Though
instrumentation amplifiers are very good at removing noise from measurements, it is
possible that the admitted noise will be amplified as much as the desired channel
separation signal.
Figure 3.8 Cascade amplifier chain for testing channel separation.
The TI LM211 comparators chosen compare two analog voltages, and output a
digital TTL compatible logic signal. This particular comparator was chosen because of
its fast response time (115ns typical) and reasonable input offset voltage (±3mV).
Certain tests, such as settling time, enforce a much smaller guard-band than ±3mV, so
offset-nulling resistors were added to the circuit to “zero-out” the parts’ offsets.
Potentiometers are used to source or sink current, as specified in the datasheet. The four
comparators will be calibrated once upon board assembly, but may need to be adjusted
periodically if the potentiometers or parts themselves drift with age. In a low production
29
environment, the comparators could be screened prior to board assembly, in order to find
parts that exhibit virtually zero Vos.
Figure 3.9 TI LM211 comparator configuration.
The peak detection circuits used also take advantage of the excellent AC
characteristics of the LM211. With minimal external components, a positive peak
detector and negative peak detector can be built. This concept was taken from an
application note within the LM211 datasheet. Passive elements, such as 10uF capacitors,
were chosen to provide for a reasonable time constant for resetting the circuit. TI
OPA132 op-amps were used as buffer amps because of their excellent DC characteristics,
namely a typical Ib specification of 5pA. This provides the capacitors a very high
impedance leakage path, which is ideal. By switching the single-pole dual-throw relays,
the output values can be ‘reset’. The amount of time it takes to discharge these capacitors
can be estimated as
t ~ 5*τ = 5*R*C = (5)(10)(10x10-6) = 0.5ms.
Similarly, even when the circuit is not being ‘reset’, there is a leakage path that is
always slowing discharging the capacitors. The amount of time it takes for these
capacitors to discharge from leakage currents can be estimated as
t ~ 5*τ = 5*R*C = (5)(1x106)(10x10-6) = 50s.
The input impedance of the OPA132 is specified as 1013 ohms, which can be
neglected when connected in parallel to a resistance of 106 ohms. The outputs of the two
30
peak detector circuits are simply two DC voltages. The two voltages can be sampled by
the ADC in the system, provided they are between the +2.5V and -2.5V input limits.
Figure 3.10 Positive peak detector circuit.
Figure 3.11 Negative peak detector circuit.
The field programmable gate array (FPGA) provides the ‘glue’ of the system,
tying most of the digital interfaces together. These signals include the DAC interface,
ADC interface, trigger signals from the comparators, and the digital control signals for
the Frequency Synthesizer Card. The FPGA also takes all timing measurements within
the system, by keeping track of how many high-frequency system clocks occur between
two triggers. A serial peripheral interface (SPI) bus is also present between the
microcontroller and FPGA. This interface provides for 8-bit data exchanges serially
between the two devices. The FPGA is configured as the slave in this relationship, while
the microcontroller is configured as the master.
31
Figure 3.12 Altera FPGA and peripherals.
The FPGA chosen was the Altera EPF10K20RC208-3, which allows for unique
system-on-a-programmable-chip integration. This particular device was chosen because
of its large memory size, respectable speed, high number of input/output pins, and 5V
logic interface.
Table 3.2 Specifications for Altera FPGA [12].
Using VHDL, along with Altera’s MaxPlusII© software, the chip can provide
almost any digital function a programmer asks of it. Logic was added to the board to
allow for in-system programmability of the FPGA. Any PC or laptop equipped with a
standard parallel port is able to reprogram the device on the board.
32
Figure 3.13 In-circuit programming hardware for the Altera FPGA.
During the debug phase of program development, the code is directly imported
into the FPGA. However, FPGAs have large embedded SRAMs that lose their memory
when power is removed. Therefore, an Altera configuration device was also added to the
system. Once the programmer is satisfied with the performance of the code being
imported to the FPGA, four 3-pin jumpers on the board are repositioned, and the code is
instead programmed into the on-board Altera EPC2 configuration device. The PC can
then be disconnected from the system, and the configuration device will reprogram the
FPGA each time power is applied to the Test and Measurement Board.
33
Figure 3.14 Altera EPC2 configuration device.
Both the ADC and DAC are controlled by the FPGA. Both parts were chosen
because of their high linearity, 5V logic interface, ±2.5 bilateral input limits, and 16-bit
resolution. Four channel parts were chosen in order to save board space and minimize
pin count. It was decided that both parts would share the same voltage references in
order to minimize the offset between the devices. A high precision reference diode is
used to create +2.5VREF, and a TI OPA277 op-amp configured for a gain of -1V/V
generates -2.5VREF. The OPA277 precision op-amp was chosen for its extremely low
offset; guaranteed to be less than 20uV.
Figure 3.15 Generation of +2.5VREF and -2.5VREF from +5V.
34
The -5V rail is easily generated from the -15V supply with a low-dropout linear
regulator. This voltage was primarily generated for the Frequency Synthesizer Board, but
can also be fed to the DUT for power. This will prove helpful when testing 10V CMOS
parts, where ±5V rails are present. The ±EXTSUP rails can be fed directly to the DUT
using software configurable relays.
Figure 3.16 Relay configuration for supplying the DUT with V+ and V-.
A 24-pin DIP socket was chosen as the DUT interface. The 24-pin socket acts as
three separate 8-pin DIP sockets. When testing a single op-amp, the DUT is placed in the
top 8 positions of the socket. When testing Channel A on a dual op-amp, the DUT is
placed in the middle 8 positions of the socket. Lastly, when testing Channel B on a dual
op-amp, the DUT is placed in the bottom 8 positions. This method was chosen in order
to simplify the hardware and software, and to minimize the number of relays on the
board.
35
Figure 3.17 DUT socket configuration.
The DIP socket itself was chosen because it is considered the standard in the opamp business. Op-amps are available in many different packages (i.e. SOIC, SC70,
WCSP), but adapters have been created to convert from these packages to a DIP form
factor. When a user is testing a device that is not in a PDIP package, they will simply
socket the device in one of these adapters and insert the adapter into the Test and
Measurement Board DUT socket.
A complete schematic diagram of the Test and Measurement Board can be found
in Appendix D. Special care must be taken in the PCB layout to assure low noise and low
impedance paths between the various IC’s. Decoupling capacitors should be placed near
each and every IC in order to minimize power supply noise injected into the device.
36
Figure 3.18 Circuit board layout of the Test and Measurement Board.
3.4 RC Configuration Card
The Test and Measurement Board allows for nine resistors and/or capacitors to be
inserted in order to configure the device. The RC Configuration Card instead interfaces
to the Test and Measurement Board with two 9-pin headers, and the resistors and/or
capacitors are placed on the plug-in card. The design allows for surface mount (size
1206) or through-hole parts to be placed on the card.
37
Figure 3.19 Generic RC plug-in card.
In an attempt to be economical, the generic RC card was designed to hold 90
resistors and/or capacitors. The entire RC card measures 1.19” x 10.63”. Once ordered,
the board can be sawn into ten useable RC Configuration Cards, each measuring 1.19” x
0.90”.
Figure 3.20 Circuit board layout of generic RC plug in card.
On the top and bottom of the board, there are white silk-screened areas for writing
values and part numbers with a marker. With simple 1-layer construction, these boards
are very inexpensive. The jumpers connected to the edge of the daughter board are
spaced 100mils apart in the x-direction, and 1000mils apart in the y-direction.
38
CHAPTER IV
TEST SOFTWARE
4.1 Software overview
The system designed yielded the need for two pieces of software to be developed.
First, software was in needed to run the Motorola microcontroller and accompanying
peripherals. This software is considered the device’s test program, and the user is
responsible for creating this assembly language program. The basic commands for the
‘Monitor’ operating system are also given as an introduction to this free software
developed by the University of Florida’s Electrical and Computer Engineering
Department. Secondly, VHDL code was developed to be run within the Altera FPGA.
This was developed as ‘behind-the-scenes’ software that should not often need to be
edited by the user. This code is responsible for much of the digital interfaces and
protocols used by other chips such as the ADC and DAC. Lastly, an overview of the
Terminal software (on the connected PC) used as the interface to the system is also
discussed.
4.2 Program flow
The chosen design requires the integration of many different pieces of hardware.
The software is responsible for tying these subsystems together into a coherent system.
The VHDL code was developed with simplicity in mind, allowing the user to have as
much control as possible in their test program. The code was written with a 'black-box'
mentality, meaning that the user requests a certain function, and the FPGA simply returns
a value to the user. The FPGA is responsible for effective communication with the ADC,
DAC, Frequency Synthesizer Card, and comparators, removing the user from the details
of protocols and timing. Instead, the user is allowed to focus on the testing of the DUT,
rather than the details of the system.
39
4.3 Microcontroller software
The microcontroller software is created using a text editor on a PC, and
downloaded to the Test and Measurement Board via a standard RS-232 serial cable. All
code is written in Motorola’s proprietary assembly language, and compiled using their
free compiler. Though the system’s user need not be an expert in the Motorola 68HC12
family of microcontrollers, basic knowledge of the architecture and instruction set will
prove helpful and is expected in this discussion. The microcontroller itself is a very
complex integrated circuit, complete with both on-chip and external peripherals. The
software is responsible for managing data transfers, performing calculations, and
communicating with the user.
One important concept that ties the microcontroller software and hardware
together is the memory map of the device. The Motorola microcontroller chosen uses a
64k address structure, utilizing a 16-bit address bus A[15..0]. Each address points to 8bits of data, referred to as D[7..0]. The memory map below details the different areas of
memory that are mapped to the various functions of the processor. For instance,
addresses $0000-$03FF are reserved for internal functions of the device. External
EEPROM, containing the ‘Monitor’ operating system, resides at addresses $C000-FFFF.
This code also uses the internal volatile RAM at address $0800-$08FF for real-time data
manipulation. Volatile RAM from addresses $0900-$0BFF is available to the user for the
test program itself. Internal EEPROM from addresses $0D00-$0FFF is also available to
the user to store data (i.e. constants and subroutines) that will not need to be modified
during the test program’s execution. The three relay drivers U23/U25/U27 are memory
mapped to addresses $8000/$9000/$A000, respectively. Writing an 8-bit word to any of
these relay drivers will result in the corresponding relays switching states.
40
Figure 4.1
Memory map of Motorola microcontroller.
Within the volatile RAM reserved for the user, 16 bytes of memory are reserved
to store the results of the tests performed. These eight test results are each stored as two
8-bit words organized in Big-Endian format, covering addresses $0900-$090F. For
instance, the concatenated words at $090C:$090D represent the measured 16-bit result
after testing the bandwidth of a device.
41
Table 4.1 Reserved memory locations for test results.
The user’s test program originates at address $0911 and will be compiled in
successive fashion. The user’s compiled test program must not extend beyond address
$0BFF, and therefore must not be larger than 752 bytes.
Table 4.2 Developed op-codes for onboard communication.
A basic instruction set was needed for communicated between the FPGA and
microcontroller, and a simple 8-bit op-code format was chosen. These op-codes are sent
from the microcontroller to the FPGA by an SPI data exchange. The INIT command is
42
used to synchronize the two devices and assure the FPGA is at the correct starting point
in its program.
Figure 4.2 Overview of program flow on Test and Measurement Board.
43
The microcontroller configures the DUT, and the desired test’s start op-code is
sent to the FPGA. Upon receipt, the FPGA carries out its corresponding measurements
and sets a flag when done. Once the microcontroller recognized that the flag has been
set, an SPI data exchange is initiated to retrieve the first 8-bits of the result. Once
retrieved, the microcontroller initiates another data exchange to get the remaining 8-bits.
The microcontroller then stores the result in the predefined memory locations mentioned
earlier.
Accessing the received data is made possible by the Monitor operating system
which resides in the connected EEPROM. The Monitor program is loaded onto an
EEPROM using a memory programmer, and once loaded it cannot be modified within the
system. The Monitor program allows the user to control the microcontroller by using a
Terminal application on a PC. It allows the user to download code to the device, set
breakpoints, execute code, view memory contents, and manually modify registers. Under
normal circumstances, a prompt will appear at the terminal window, allowing the user to
execute these commands with simple and easy to use nomenclature.
Sample test programs are included in Appendix A. This source code sheds light
on some typical routines that may be executed by a user. This code also includes
initialization routines that need not be edited by the user, but included for the code to
compile and run correctly. Many subroutines have been written for clarity, and can be
used repeatedly within a test program while minimizing the amount of RAM needed to
run the program.
4.4 FPGA software
The FPGA software was built with modularity in mind. Simple building blocks
were designed, each written using VHDL. These building blocks were connected using
MaxPlusII’s graphical wiring interface. This was done for ease of understanding the
hierarchal nature of the design.
•
The HCA12ADDRDEC subsystem provides a logical partial address decoder
responsible for generating the timing and permission signals needed by the
44
microcontroller’s peripherals (i.e. EEPROM, memory-mapped I/O ports). This
subsystem is independent from all others within the FPGA.
•
The SPI subsystem is responsible for implementing the protocol for successful
bidirectional communication between the FPGA and microcontroller. The SPI
subsystem is configured as a slave device, meaning it is synchronized by the
microcontroller’s SPI clock.
•
The COUNTER subsystem acts as reset capable 16-bit free running counter,
clocked by the high-speed external system clock. All timing measurements are
taken in reference to this counter.
•
The CLKDIV subsystem provides lower frequency clocks to other peripherals. It
generates these clocks by dividing the high frequency system clock.
•
The DACCONTROL subsystem is responsible for implementing the digital
protocol of the onboard TI DAC7644. A write to this subsystem translates to a
protocol in which the appropriate channel of the onboard DAC7644 is
programmed.
•
The ADCCONTROL subsystem is responsible for implementing the digital
protocol of the TI ADS8342. A read from this subsystem translates to the
complex protocol of the TI ADS8342, allowing sampling of various onboard
analog signals.
•
The NOTTRIBUS subsystem conditions the frequency logic signal so that the
FPGA can correctly interface to the Frequency Synthesizer Card.
•
The FINDEVENTS subsystem monitors two trigger input signals for rising and/or
falling edge trigger events. This subsystem is used when testing for gainbandwidth product.
•
The TRIGGERGATES subsystem debounces the four input trigger signals to
lessen false triggers caused by noise. The subsystem also provides hysteresis to
the trigger signals.
•
The RUNTESTS subsystem acts as the main controller within the FPGA. This
state machine is responsible for the program flow, reacting to various test
45
conditions, and controlling many of the other subsystems. The DACCONTROL
and ADCCONTROL subsystems are both called from this file much like
subroutines. Also, the SPI, COUNTER, and FINDEVENTS subsystems could be
considered supporting units for the RUNTESTS system.
Figure 4.3
Subsystems located within the Altera FPGA.
The main point of interest within the FPGA software is the state machine present
in the RUNTESTS subsystem. At the heart of this state machine there is an if, elsif, else
statement, which decides the code that should be run according to the test being
implemented. Once the measurement has been taken and the 16-bit result is available, all
test sequences use the same code for returning the data to the microprocessor.
46
Figure 4.4 Overview of program flow in RUNTESTS subsystem.
Both the rising edge and falling edge slew rate tests follow a similar program
flow. For the most part, they are inversions of one another. Both tests share some
common code, and branch to their individual code when needed. Similarly, the Vcc and
Vee overload recovery time tests follow a similar program flow. Both the Vcc and Vee
settling time tests also share common code, and are very similar to one another.
47
Figure 4.5 Program flow for rising and falling edge slew rate tests.
Figure 4.6 Program flow for Vcc and Vee overload recovery time tests.
48
Figure 4.7 Program flow for Vcc and Vee settling time tests.
The gain-bandwidth test uses an iterative method for estimating the bandwidth of
a device. The system is programmed to find the bandwidth of the DUT with a resolution
of 10kHz. The gain-bandwidth test takes the most time of any test implemented within
the system. The channel separation test utilizes the simplest software of all the tests
performed.
49
Figure 4.8 Program flow for gain-bandwidth product test.
50
Figure 4.9 Program flow for channel separation test.
4.5 PC software
The test program itself can be created and modified using a simple text editor.
However, as when writing any program, an IDE can prove useful during software
development. The IDE chosen was MiniIDE, developed and distributed by MGTEK.
This free software includes the Asm12.exe assembler needed to compile the assembly
language code into machine language understood by the Motorola microcontroller.
Figure 4.10 MGTEK’s MiniIDE development environment.
51
The test program is written and saved in a filename.asm format. Once saved,
the user builds the program, creating a debug (filename.lst) file and a compiled test
program (filename.s19). The debug file acts as an intermediary between the test
program written and the compiled machine code. It shows line by line compilation of the
program, including references to memory addresses and data. If there are errors (invalid
instruction formats, etc.) in the user’s test program, the assembler will not create the
output files and will warn the user of the errors. Once corrected and compiled, the s19
file is downloaded to the board and run as the test program for the DUT.
A simple terminal program, such as Microsoft’s HyperTerminal, is used to
communicate with the microcontroller. Using a standard RS-232 based serial port
(usually COM1 or COM2 on a PC), bidirectional communication is established when the
PC is configured to match the needs of the system. This requires the serial port to be
configured to operate at 9600bps, use an 8/N/1 data format, and have an unregulated data
flow.
Figure 4.11 Settings for the connected PC’s serial communication port.
52
Once connected correctly and communication is established, the microcontroller’s
operating system should display a prompt immediately after a hardware reset. A splash
screen should appear, notifying the user that the Monitor V2.0 software is being used.
Figure 4.12 Monitor splash screen shown upon reset.
At this prompt, a variety of commands can be executed. A list of basic
commands, along with their formats, can be seen by typing HELP<>.
Figure 4.13 Results of the HELP command being executed.
The Monitor operating system allows the user to both view and edit the memory
available in the system. Monitor allows the user to download a compiled test program,
and run it from the command line. It also allows the user to add breakpoints, and view
the contents of common registers after a software interrupt (SWI).
To download a test program, the user types LOAD<> at the command line prompt,
and Monitor then replies with “Waiting for S19 download…”. The user then
53
selects Transfer / Send text file…, and chooses the s19 file for download. Upon
completion, Monitor replies with “done!”. The user must then reset the microcontroller
in order to regain controller of the Monitor operating system.
Figure 4.14 Results of the LOAD command being executed.
To assure that the data was correctly loaded into the microcontroller’s RAM, a
MD<> command can be performed to display the memory contents. The format for this
command is: MD <start address> <end address>. The contents are memory are
displayed in a line by line format with each line containing 16 bytes of memory, $XXX0$XXXF. The contents of memory are displayed in hexadecimal format.
Figure 4.15
Results of the MD command being executed.
54
The data present in any writable memory element or mapped port can be modified
using the MM<> command. The format for this command is: MM <address> <data>.
Monitor returns the data value that has been replaced in memory. This returned value is
not valid for external memory mapped ports, but is correct for internal memory such as
RAM. Sometimes it may be desirable to modify a block of consecutive memory
addresses, such as clearing or filling a 16-byte row. The FILL<> command is used to
carry out this action. The format for this command is: FILL <starting address>
<ending address> <data>.
Figure 4.16 Results of the FILL command being executed.
Once the user’s test program is downloaded to the system using the LOAD<>
command, the program must be executed. This is done using the GO<> command. The
format for this command is: GO <address>. Generally, the user’s test program will
start at address $0911. After the test program is executed, the system should return to the
Monitor prompt. This allows the user to perform a MD<> command in order to see the
results of the tests performed.
55
Figure 4.17 Results of the GO command being executed.
When an invalid command is given to Monitor, it usually responds with ”you
missing something?”. However, sometimes a missing argument for invalid
instruction will cause Monitor to freeze, and the user must reset the microcontroller. It
should be noted that Monitor is case-sensitive, preferring all lower-case syntax.
Figure 4.18 Results of an invalid command request.
The Monitor operating system is a powerful tool when debugging a test program.
Only the basic commands for Monitor have been discussed. Its additional capabilities
include the ability to add software breakpoints, and execute code line by line. The user is
urged to delve into more detail in regards to this powerful operating system.
56
CHAPTER V
DATA ANALYSIS FOR REPEATABILITY
AND CORRELATION
As with most complex circuit designs, considerable debug efforts are needed after
the parts are soldered to the printed circuit board. These efforts may include tweaking
resistor and capacitor values or optimizing software. The design should be separated into
manageable blocks and first debugged individually. Once each block has been verified,
the entire system should be tested together when possible. When satisfied with the
system functionality, its performance must be characterized. The characterization
process must first determine how accurate the results are. The test results are compared
to data collected by hand using standard bench equipment. Secondly, it must be
determine how repeatable the automated test system is. Repeatability and accuracy
depend on the test instruments’ characteristics, the expected measurement, tester limits,
noise and the test circuit design [4].
5.1 Frequency Synthesizer Board results
Initial tests showed that the Frequency Synthesizer Board was capable of creating
a wide range of sine waves, but the square waves exhibited a lower frequency limit of
approximately 14kHz. To circumvent this problem, a larger Cosc capacitor (2nF) is used
when square waves are desired. This was done because the output frequency of the
MAX038 frequency synthesizer chip is a function of the input current and the attached
Cosc capacitor. A single-pole single-throw (SPST) reed relay was added to the board and
its coil was driven directly by the SELECT signal. When a square wave is selected, the
relay closes and connects the second capacitor in parallel with the much smaller onboard
Cosc capacitor. Since the current into the MAX038 remains the same regardless of the
SELECT signal, a much lower frequency square wave is possible. With this
modification, the lower frequency limit is below 2kHz.
57
Once programmed, it was seen that low-frequency square waves exhibited
considerable overshoot and ringing. The 90.9Ω resistor was replaced with a 0Ω-200Ω
single-turn potentiometer. Varying this resistor value changes the filter’s transient
response. The resistance value that correctly compensates this circuit is 115Ω, but could
vary slightly from board to board. As the resistor deviates from its ideal (critically
damped) value, the response will be either over or under damped.
Figure 5.1 2kHz square wave output (minimal persistence).
When programmed to output a 2kHz square wave, the measured output is very
accurate in terms of frequency. Its average amplitude is approximately 2.10Vpp,
including noise. Even with appropriate power supply decoupling capacitors and a 2nd
order low-pass filter, the noise floor of the MAX038 is considerable. Infinite persistence
on the oscilloscope was used to see the cumulative effects of the noise floor.
58
Figure 5.2 2kHz square wave output (infinite persistence).
Approximately 100mVpp of cumulative noise was exhibited on the settled signal.
This amount of noise will make the planned settling time measurement impossible.
Considerable board modifications would be needed in order to allow for this
measurement, and will be left for a future revision of this project.
Figure 5.3 2kHz square wave output (infinite persistence, zoomed in).
59
The output waveform exhibited rising and falling edge slew rates of over 60V/us
over its 10%-90% amplitude range. Near the zero-crossing, both the rising and falling
edge slew rates neared 100V/us. These slew rates should prove to be more than sufficient
when measuring the DUT’s slew rate.
Figure 5.4 Rising and falling slew rate measurements of 2kHz square wave output.
A fast Fourier transform (FFT) analysis was used to view the frequency content of
the waveform. As expected, most of its spectral power was contained in the 2kHz band,
while the even harmonics carried much of the remaining power.
60
Figure 5.5 Frequency spectrum of 2kHz square wave output.
A wide frequency range of sine waves were reproduced, and exhibited
satisfactory results. Frequency accuracy was very good, with the resolution of 1kHz
being realized.
Figure 5.6 Output signal and frequency spectrum of 2MHz sine wave output.
Frequency and amplitude data was recorded for programmed frequencies of
100kHz, 500kHz, 1MHz, 2MHz, 4MHz, 8MHz, and 16MHz. Mean amplitude, mean
61
frequency, standard deviation of frequency, and power spectral density data were
recorded.
Table 5.1 Recorded frequency and amplitude data for various sine waves.
Programmed
Frequency
(kHz)
100
500
1000
2000
4000
8000
16000
Mean
Amplitude
(V)
2.0449
2.0853
2.0669
2.0519
2.0360
2.0010
1.8163
Mean
Frequency
(kHz)
99.98
499.97
1000.00
2000.17
4000.03
7999.70
1599.52
Std. Dev. Of
Frequency
(kHz)
0.38
1.88
3.59
7.90
15.66
28.70
62.18
Difference Between
Main and Harmonic
(dB)
30.26
34.82
35.14
34.90
33.78
33.99
38.63
As with most electronic circuits suffering from bandwidth effects, it was seen that
the peak-to-peak amplitude of the sine waves decreased with increased frequency. At
low frequencies, the amplitude actually exceeded the nominal 2Vpp specification, but was
only 1.81Vpp when programmed to 16MHz. The nominal specification was best seen
when the output was programmed with mid-range frequencies. When comparing mean
frequency to the programmed frequency, the best frequency accuracy was seen with midrange frequencies. However, all mean frequencies were within +0.5kHz of their
programmed values, which verifies the 1kHz resolution of the frequency. When
comparing the standard deviation of the output frequency to the mean output frequency, it
can be seen that excellent results were achieved in the low and mid-range frequency
bands. This measurement signifies frequency jitter in the output signal. Lastly, when
comparing the power density of the main frequency component to the largest harmonic, it
was seen that the high-frequency range contained the most power in the root component.
62
Mean Frequency vs. Programm ed
Frequency
10
0
Program med Frequency (kHz)
Programm ed Frequency (kHz)
Difference Betw een Main Frequency
Com ponent and Largest Harmonic
Standard Deviation Vs. Mean Frequency
Program med Frequency (kHz)
16
00
0
10
0
16
00
0
80
00
50
0
10
00
20
00
40
00
0
80
00
0.01
40
00
0.02
20
00
0.03
50
40
30
20
10
0
10
00
0.04
50
0
root - harmonic (dB)
0.05
10
0
Standard Deviation /
Mean Frequency
50
0
10
00
20
00
40
00
80
00
16
00
0
1.0002
1.0001
1
0.9999
0.9998
0.9997
0.9996
0.9995
Mean / Programmed
Frequency
16
00
0
80
00
50
0
10
00
20
00
40
00
1.1
1.05
1
0.95
0.9
0.85
0.8
10
0
Vpp Output Voltage /
2Vpp
Norm alized Vpp Output Voltage
vs. Program med Frequency
Programm ed Frequency (kHz)
Figure 5.7 Signal characteristics of various sine waves.
Overall, the data suggests the successful completion of the Frequency Synthesizer
Board. In order to correctly interface the Frequency Synthesizer Card to the FPGA on
the Test and Measurement Board, it was realized that the FREQ[13..0] pins needed pullup resistors. Two 9-pin resistor packs tied to +5V were used to achieve this. With the
minor modifications suggested above, the board produces high fidelity sine waves across
a wide range of frequencies. Low frequency square waves exhibit excellent frequency
resolution, transient response, and slew rates. The noise floor was the only parameter
which performed worse than expected.
5.2 Test and Measurement Board results
Initial debug efforts were spent verifying the operation of the digital circuitry
onboard. The Motorola microcontroller was soon able to boot the Monitor operating
63
system. The memory mapped output ports were verified, and the corresponding relays
were verified working. This process was fairly tedious, but required for completeness.
The FPGA was programmed with simple test programs such as counters to verify
its operation. The JTAG programming interface was verified working, along with the
ability to run simple synchronous state machines at 20MHz.
The onboard analog-to-digital converter was heating up, and after some research
it seemed most likely that the internal ESD protection structures were conducting. After
reviewing the ADS8342 datasheet, it was realized that the analog inputs should be
clamped at +2.5V. This would require considerable change to the PCB, so the next
revision of the board will fix this problem. Since the settling time test will no longer be
performed, it was decided that the ADS8342 would simply be removed from the board.
Likewise, the THS7001 programmable gain amplifier was also heating up. After
looking more closely at its datasheet, it was realized that the preamp portion of the PGA
was not stable at a gain of +1V/V as configured. The minimum gain for stability of the
THS7001 preamp is -1V/V or +2 V/V. The preamp’s output pin and non-inverting pin were
lifted from their pads and two resistors were added to configure the preamp stage to a
gain of +6V/V. A thin braided wire was also connected from the PowerPad on the bottom
of the IC to a ground via, in order to provide a path for heat transfer.
Table 5.2 Component values changed on Test and Measurement Board.
OLD
NEW
C23
0.1uF
NOPOP
R01
90.9
100 variable
R03
10
Pin sockets
R04
NOPOP
Pin sockets
R15
10K
10K precision
R16
10K
9K precision
R23
24.9K
2.49K
R28
34.8K
NOPOP
R29
84.5K
20K precision
R64
1K
1K precision
U30
50MHz
20MHz
64
In order to yield optimum results, some component values were changed in order
to optimize the performance of various IC’s onboard.
After monitoring the output of the channel separation circuitry, it was decided that
the test would not yield useful results. The amplified noise superceded the planned
amplitude of the channel separation measurement. It was decided that no more efforts
would be dedicated to the channel separation test. The goals of the system have become
to achieve accurate and repeatable results when measuring slew rate, overload recovery
time, and bandwidth.
The FPGA software was tested for functionality. Communication between the
FPGA and microcontroller was working correctly over the SPI interface. The FPGA was
able to program the onboard digital-to-analog converter and the Frequency Synthesizer
Board. After tweaking each individual test, the gain-bandwidth, overload recovery, and
slew rate state machines executed correctly with a 20MHz system clock. However, once
combined into a single large state machine, the nearly full FPGA could not correctly
execute this large state machine at 20MHz. This timing resolution was not needed when
testing for bandwidth, so it was decided that two separate system clocks would be used
for clocking the FPGA. The 20MHz clock remained used when testing overload
recovery time and slew rate, giving these tests a timing resolution of 50ns. A 4MHz
clock was added to the board and connected to the FPGA’s second global clock (pin 79).
This clock is used when testing the bandwidth of a part, and does not change the 1kHz
resolution available when testing GBW.
Next, correlation and repeatability studies were performed on both a CMOS and
bipolar op-amp. The results should shed light on the abilities of the designed system.
The TI OPA347 was chosen to be the CMOS test vehicle, while the TI OPA277 was
chosen as the bipolar test vehicle. Both parts should theoretically be within the limits of
the system, and are good representatives of the low-to-medium bandwidth portion of the
precision op-amp portfolio. The OPA277 is considerably faster than the OPA347, but
will be tested over a larger voltage range. These two op-amps should exercise the ability
of the test system to gain/attenuate the input waveform and scale the output signal. The
65
CMOS part will use +2.5V power supplies, while the bipolar part will exercise +15V
supplies.
5.3 RC Configuration Card results
The RC Configuration Card worked as expected. Both surface mount 1206 and
through-hole resistors/capacitors can be soldered to the board. One manufactured board
can be cut into 10 individual RC Configuration Cards.
5.4 Analysis of OPA347 test results
Six different OPA347 op-amps were tested using the automated bench system.
Each part was tested at least twenty times. Most parts were tested 21 or 22 times, due to
false triggers that resulted in statistical outliers. These false triggers are usually caused
by noise present in the system, and the results are usually unreasonably large or small.
Those tests which yielded outliers have not been included in this statistical analysis.
All devices were powered with +2.5V power supplies. For all tests, a load of
100KΩ and 100pF [in parallel] was connected to ground. When testing for slew-rate and
bandwidth, the device was configured as a voltage follower and employed a 100KΩ load
resistor. When testing for overload recovery time, the device was setup as a noninverting amplifier with a gain of +2.5V/V. Two resistors of 40KΩ and 60KΩ were used
to provide this gain. These resistors in series also yield the desired 100K load.
Table 5.3 RC Configuration Card setup for OPA347.
Position
R05
R07
R11
R27
Value
40K
60K
100K
0
SR
√
√
OR
√
√
√
GBWP
√
√
The oscilloscope was configured for infinite persistence when attempting to find
the most accurate estimate of the DUT’s slew rate, overload recovery time, and
bandwidth. Each measurement was repeated for all six devices, and is referred to as the
ideal measurement (i). Each part was then tested using the automated bench test system.
66
After twenty valid test samples were gathered, the mean (µ) and standard deviation (σ) of
the automated measurements were calculated. The error (е) was calculated as
е = | (µ–ideal) / ideal |. This error estimation determines the system’s ability to accurately
reproduce values thought to be true. The repeatability (r) was calculated as r = 1 - |σ / µ|.
The repeatability determines the system’s ability to perform the measurement with high
precision, regardless of the accuracy of the system. Both the error and repeatability are
needed to characterize the performance of the test system. The goal set forth was to
design an automated test system with error less than 5% and repeatability greater than
95%.
Figure 5.8 Rising and falling slew rates of the OPA347.
When manually testing for the slew rate, the two relative data points were taken at
the horizontal center of the output waveform when crossing -0.8V and 0.8V. When
testing for rising edge slew rate, the system was able to reproduce the ideal measurement
with an error of no more than 2.41% with a repeatability of no less than 99.53% on all six
devices. When testing for falling edge slew rate, the system’s error was no more than
3.22%, and its repeatability was no less than 98.22%. The automated test system will be
considered a valid test solution for characterizing the slew rate of the TI OPA347.
Table 5.4 OPA347 error and repeatability data of rising-edge slew rate.
DUT1
DUT2
DUT3
DUT4
DUT5
DUT6
Ideal measurement (i)
0.142959
0.137952
0.143344
0.128320
0.130201
0.138038
Measured mean (µ)
0.145423
0.141219
0.146722
0.131417
0.132670
0.139894
Standard deviation (σ)
0.000452
0.000314
0.000301
0.000277
0.000225
0.000661
1.72%
2.37%
2.36%
2.41%
1.90%
1.34%
99.69%
99.69%
99.80%
99.79%
99.83%
99.53%
Error (е)
Repeatability (r)
67
Table 5.5 OPA347 error and repeatability data of falling-edge slew rate.
DUT1
DUT2
DUT3
DUT4
DUT5
DUT6
Ideal measurement (i)
0.166095
0.165787
0.169519
0.152920
0.136923
0.156627
Measured mean (µ)
0.171447
0.167365
0.172091
0.154627
0.140506
0.158810
Standard deviation (σ)
0.003058
0.000358
0.000557
0.000168
0.000339
0.000404
3.22%
0.95%
1.52%
1.12%
2.62%
1.39%
98.22%
99.79%
99.68%
99.89%
99.76%
99.75%
Error (е)
Repeatability (r)
When manually testing for the overload recovery time, the two relative data
points were taken at the falling [rising] edge of the input waveform and the horizontal
center of the output waveform as it crossed 2.3V [-2.3V].
Figure 5.9 Overload recovery times (Vcc and Vee) of the OPA347.
When testing for overload recovery time (Vcc), the system was able to reproduce
the ideal measurement with an error of no more than 3.24% with a repeatability of no less
than 99.83% on all six devices. When testing for overload recovery time (Vee), the
system’s error was no more than 2.02%, and its repeatability was no less than 99.73%.
The automated test system will be considered a valid test solution for characterizing the
overload recovery times of the TI OPA347.
Table 5.6 OPA347 error and repeatability data of overload recovery time (Vcc).
DUT1
DUT2
DUT3
DUT4
DUT5
DUT6
Ideal measurement (i)
18.234000
17.780000
18.325000
19.144000
21.234000
18.709000
Measured mean (µ)
17.662500
17.610000
17.757500
19.060000
21.092500
18.555000
0.022213
0.026157
0.024468
0.026157
0.018317
0.032036
3.24%
0.97%
3.20%
0.44%
0.67%
0.83%
99.87%
99.85%
99.86%
99.86%
99.91%
99.83%
Standard deviation (σ)
Error (е)
Repeatability (r)
68
Table 5.7 OPA347 error and repeatability data of overload recovery time (Vee).
DUT1
DUT2
DUT3
DUT4
DUT5
DUT6
Ideal measurement (i)
16.091000
16.636000
15.727000
17.909000
17.727000
16.818000
Measured mean (µ)
15.772500
16.422500
15.560000
17.722500
17.442500
16.512500
0.030240
0.044352
0.026157
0.044352
0.040636
0.031933
Standard deviation (σ)
Error (е)
Repeatability (r)
2.02%
1.30%
1.07%
1.05%
1.63%
1.85%
99.81%
99.73%
99.83%
99.75%
99.77%
99.81%
When testing for the DUT’s gain bandwidth product, the device was configured
as a voltage follower. Being that the device was configured to provide a gain of +1V/V,
the measured bandwidth is equivalent to the gain bandwidth product. The nominal input
voltage of 2Vpp was too large of a signal, and the part quickly became slew rate limited at
even low frequencies. An attenuated 200mVpp sine wave was used as input to the DUT,
and the output was monitored. A 4-point moving average was applied to both the input
and output signals in order to remove noise from the measurement.
Figure 5.10 Measuring bandwidth of the OPA347.
Due the noise present in the input and output signals, the comparator trigger levels
needed to be reduced. Infinite persistence was used on the oscilloscope to determine the
typical noise margins present on the output signal. In turn, rather than programming the
two corresponding DAC channels to +0.0707V, they were instead programmed to
+0.0480V.
69
Table 5.8 OPA347 error and repeatability data for gain bandwidth product.
DUT1
DUT2
DUT3
DUT4
DUT5
DUT6
Ideal measurement (i)
341.000000
346.000000
326.000000
325.000000
323.000000
339.000000
Measured mean (µ)
340.000000
360.000000
320.000000
340.000000
320.000000
350.000000
0.000000
0.000000
0.000000
0.000000
0.000000
0.000000
Standard deviation (σ)
Error (е)
Repeatability (r)
0.29%
3.89%
2.19%
4.41%
0.94%
3.14%
100.00%
100.00%
100.00%
100.00%
100.00%
100.00%
When testing for the gain-bandwidth product, the system was able to reproduce
the ideal measurement with an error of no more than 4.41% with a repeatability of 100%
on all six devices. It should be noted that the 10kHz resolution provided for within the
system does not allow for accuracies much higher than this when testing low bandwidth
parts. The PDS for the OPA347 specifies a typical GBW of 350kHz. Therefore, the
10kHz step size provides for nearly 3% error itself. Though the automated test system
will be considered a valid test solution for characterizing the gain-bandwidth product of
the TI OPA347, future characterization should employ a smaller step size to increase the
accuracy of the system.
5.5 Analysis of OPA277 test results
Six different OPA277 op-amps were tested using the automated bench system.
Each part was tested at least twenty times. Most parts were tested more often, due to
false triggers that resulted in statistical outliers. These false triggers are usually caused
by noise present in the system, and the results are usually unreasonably large or small.
Those tests which yielded outliers have not been included in this statistical analysis.
All devices were powered with +15V power supplies. For all tests, a 2KΩ load
was required. When testing for slew-rate and bandwidth, the device was configured as a
voltage follower and employed a 2KΩ load resistor. When testing for overload recovery
time, the device was configured as a non-inverting amplifier with a gain of +15V/V.
Two resistors of 133Ω and 1867Ω were used to provide this gain. These resistors in
series also yield the desired 2K load.
70
Table 5.9 RC Configuration Card setup for OPA277.
Position
R05
R07
R11
R27
R27
Value
133
1867
2K
100K
0
SR
√
√
OR
√
√
GBWP
√
√
√
The 100KΩ resistor placed at R27 acts a scaling resistor. In series with a 20KΩ
resistor (R29), it provides for a 6:1 scaling factor at the output. With the device being
powered by bipolar 15V supplies, the output should never go beyond these levels. As the
output is scaled, it should never exceed the +2.5V range of the digital-to-analog
converter. The scaling resistors are effectively in parallel with the desired load, therefore
the true load connected to the DUT’s output is 2KΩ||120KΩ. For all practical purposes,
this load resistance will be considered to be 2KΩ. The scaling resistor is only used when
testing for the slew rates and overload recovery times of the DUT. When testing for the
gain-bandwidth product of the device, no scaling is needed. Therefore, two different RC
Configuration Cards were needed to test the OPA277.
The oscilloscope was configured for infinite persistence when attempting to find
the most accurate estimate of the DUT’s slew rate, overload recovery time, and
bandwidth. Each measurement was repeated for all six devices, and compared against
the data measured by the automated bench test system.
Figure 5.11 Rising and falling slew rates of the OPA277.
When manually testing for the slew rate, the two relative data points were taken at
the horizontal center of the output waveform when crossing -4V and 4V. When testing
71
for rising edge slew rate, the system was able to reproduce the ideal measurement with an
error of no more than 4.98% with a repeatability of no less than 97.53% on all six
devices. When testing for falling edge slew rate, the system’s error was no more than
2.30%, and its repeatability was no less than 99.37%. The automated test system will be
considered a valid test solution for characterizing the slew rate of the TI OPA277.
Table 5.10 OPA277 error and repeatability data of rising-edge slew rate.
DUT1
DUT2
DUT3
DUT4
DUT5
DUT6
Ideal measurement (i)
0.695977
0.723088
0.728749
0.813339
0.692502
0.760652
Measured mean (µ)
0.662066
0.688678
0.692438
0.779561
0.658147
0.725908
Standard deviation (σ)
0.012632
0.012496
0.017124
0.018342
0.013304
0.014859
4.87%
4.76%
4.98%
4.15%
4.96%
4.57%
98.09%
98.09%
97.53%
97.65%
97.98%
97.95%
Error (е)
Repeatability (r)
Table 5.11 OPA277 error and repeatability data of falling-edge slew rate.
DUT1
DUT2
DUT3
DUT4
DUT5
DUT6
Ideal measurement (i)
0.660822
0.681741
0.695108
0.780687
0.666500
0.734551
Measured mean (µ)
0.647650
0.669336
0.679126
0.766123
0.653472
0.721235
Standard deviation (σ)
0.002326
0.003789
0.002536
0.004329
0.002772
0.004516
1.99%
1.82%
2.30%
1.87%
1.95%
1.81%
99.64%
99.43%
99.63%
99.43%
99.58%
99.37%
Error (е)
Repeatability (r)
When manually testing for overload recovery times, the output was considered to
no longer be saturated once the signal left its settled noise margin. Infinite persistence
was used to find this value. When testing for overload recovery time (Vcc), the system
was able to reproduce the ideal measurement with an error of no more than 3.58% with a
repeatability of no less than 99.09% on all six devices.
Figure 5.12 Overload recovery times (Vcc and Vee) of the OPA277.
72
When testing for overload recovery time (Vee), the system’s error was no more
than 1.56%, and its repeatability was no less than 96.99%. The automated test system
will be considered a valid test solution for characterizing the overload recovery times of
the TI OPA277.
Table 5.12 OPA277 error and repeatability data of overload recovery time (Vcc).
DUT1
DUT2
DUT3
DUT4
DUT5
DUT6
Ideal measurement (i)
3.618000
3.618000
3.582000
3.218000
3.618000
3.436000
Measured mean (µ)
3.752500
3.635000
3.707500
3.330000
3.725000
3.512500
Standard deviation (σ)
0.034317
0.028562
0.029357
0.025131
0.025649
0.022213
Error (е)
Repeatability (r)
3.58%
0.47%
3.39%
3.36%
2.87%
2.18%
99.09%
99.21%
99.21%
99.25%
99.31%
99.37%
Table 5.13 OPA277 error and repeatability data of overload recovery time (Vee).
DUT1
DUT2
DUT3
DUT4
DUT5
DUT6
Ideal measurement (i)
3.072000
2.927000
3.000000
2.636000
3.073000
2.818000
Measured mean (µ)
3.027500
2.925000
3.047500
2.645000
3.052500
2.852500
Standard deviation (σ)
0.057297
0.088109
0.049934
0.042612
0.030240
0.067814
Error (е)
Repeatability (r)
1.47%
0.07%
1.56%
0.34%
0.67%
1.21%
98.11%
96.99%
98.36%
98.39%
99.01%
97.62%
When testing for the DUT’s gain bandwidth product, the device was configured
as a voltage follower. Being that the device was configured to provide a gain of +1V/V,
the measured bandwidth is equivalent to the gain bandwidth product. The nominal input
voltage of 2Vpp was too large of a signal, and the part quickly became slew rate limited at
even low frequencies. An attenuated 200mVpp sine wave was used as input to the DUT,
and the output was monitored. A 4-point moving average was applied to both the input
and output signals in order to remove noise from the measurement.
73
Figure 5.13 Measuring bandwidth of the OPA277.
Due to the noise present in the output signals and the delays inherent to the
comparators, the comparator trigger levels needed to be reduced. Infinite persistence was
used on the oscilloscope to determine the typical noise margins present on the output
signal. In turn, rather than programming the two corresponding DAC channels to
+0.0707V, they were instead programmed to +0.0480V.
Table 5.14 OPA277 error and repeatability data for gain bandwidth product.
DUT1
DUT2
DUT3
DUT4
DUT5
DUT6
Ideal measurement (i)
914.000000
919.000000
955.000000
1052.000000
899.000000
973.000000
Measured mean (µ)
920.000000
921.500000
961.000000
1050.000000
923.900000
988.500000
0.000000
3.663475
3.077935
0.000000
2.936163
3.663475
Standard deviation (σ)
Error (е)
Repeatability (r)
0.65%
0.27%
0.62%
0.19%
2.70%
1.57%
100.00%
99.60%
99.68%
100.00%
99.68%
99.63%
When testing for the gain-bandwidth product, the system was able to reproduce
the ideal measurement with an error of no more than 2.70% with a repeatability of no less
than 99.60% on all six devices. As expected, the 10kHz resolution provided for within
the system allows for much higher accuracies when testing higher bandwidth parts. The
PDS for the OPA277 specifies a typical GBW of 1MHz. Therefore, the 10kHz step size
provides for only 1% error itself. The automated test system will be considered a valid
test solution for characterizing the gain-bandwidth product of the TI OPA277.
74
5.6 Test time
The designed automated test solution proved to be very efficient in testing the AC
parameters of the OPA347 and OPA277. Slew-rate and overload recovery time tests
proved to be the fastest, considering they only require one transition of the output signal
to take the needed measurement. The system is able to test either the rising or falling
edge slew rates in less than 0.2 seconds on both devices. The system is also capable of
testing either the Vcc or Vee overload recovery times in less than 0.2 seconds.
Table 5.15 Average test time for the OPA347 and OPA277.
OPA347
OPA277
SR (rising)
0.2s
0.2s
SR (falling)
0.2s
0.2s
OR (Vcc)
0.2s
0.2s
OR (Vee)
0.2s
0.2s
GBW
6.7s
9.1s
Testing the gain-bandwidth product of each device takes considerably more time.
The iterative method used requires taking more measurements, and is dependent on the
device being tested. As expected, the lower bandwidth part (OPA347) exhibited lower
average test time than its higher bandwidth counterpart (OPA277). A trade-off exists in
accuracy and test time. Using larger step sizes could reduce the test time when
measuring the GBW on higher bandwidth devices. Similarly, reduced error may be
possible by reducing the step size, especially when testing lower bandwidth parts. As a
rule of thumb, reducing step size increases both the accuracy and test time.
75
CHAPTER VI
CONCLUSIONS
6.1 Comparison of test results
The automated test system was able to produce acceptable test results on both the
OPA347 and OPA277. When considering all tests conducted on all twelve devices, the
average system error was 2.05%, with an average repeatability of 99.34%. Additional
test solutions can be easily and quickly created by configuring new RC Configuration
Cards.
Table 6.1 Comparison of automated test results for the OPA347 and OPA277.
OPA347
OPA277
2.02%
99.72%
0.2s
4.72%
97.88%
0.2s
1.80%
99.51%
0.2s
1.96%
99.51%
0.2s
1.56%
99.87%
0.2s
2.64%
99.24%
0.2s
1.49%
99.78%
0.2s
0.89%
98.08%
0.2s
2.48%
100.00%
6.7s
1.00%
99.77%
9.1s
SLEW RATE (RISING)
Average error
Average repeatability
Average test time
SLEW RATE (FALLING)
Average error
Average repeatability
Average test time
OVERLOAD RECOVERY (Vcc)
Average error
Average repeatability
Average test time
OVERLOAD RECOVERY (Vee)
Average error
Average repeatability
Average test time
GAIN-BANDWIDTH PRODUCT
Average error
Average repeatability
Average test time
Across all measurements, the highest error and lowest repeatability was seen
when testing the rising-edge slew rate of the OPA277. When testing this parameter,
additional error was introduced by a knee in the output signal. This knee produces an
error that is unpredictable, because it may vary from part to part. More accurate results
76
could be achieved by narrowing the measurement band from +4V to +3.5V, where the
knee would no longer have an effect on the measurement.
Figure 6.1 Knee in output when testing rising edge slew rate of the OPA277.
It should also be noted that the scaling resistors play an important role in testing
devices with high output voltages. If these resistors do not provide the desired X:Y
scaling factor exactly, additional error is introduced into the measurement. Hand selected
1% accuracy resistors were used when testing the OPA277. It is recommended that
precision resistors of 0.1% accuracy [or better] should be used when populating R27 and
R29.
Figure 6.2 Slew rate limiting while testing for gain-bandwidth product.
When validating the test solution for a new part, it is important to verify that the
op-amp is not slew rate limiting when testing for the gain-bandwidth product. At the
77
measured bandwidth, the output’s slew rate near the zero-crossing should be examined.
As seen in Figure 6.2, the OPA277 [device #1] showed a maximum slew rate of 0.27V/µs
while operating at the measured -3dB frequency. This slew rate is significantly less than
the 0.69V/µs measured earlier, and the part is therefore not slew rate limiting. Therefore,
a larger input sine wave could have been used, possibly leading to a more accurate
measurement. Similarly, the maximum slew rate seen when testing for the gainbandwidth product of the OPA347 was 0.13V/µs. This value is less than the 0.14V/µs
seen when testing the rising edge slew rate. Therefore, the 200mVpp sine wave used is
about the largest input signal that should be used when testing the OPA347.
6.2 Limitations of the system
Utilizing the designed measurement resolutions, the theoretical limits of the
system while maintaining less than 5% error and greater than 95% repeatability are:
‰ Slew rates (rising and falling edge)
„ 5V CMOS: 1.6V/µs (maximum)
„ 30V Bipolar: 9.6V/µs (maximum)
‰ Overload recovery times (Vcc and Vee)
„ 5V CMOS and 30V Bipolar: 1µs (minimum)
‰ Gain-bandwidth product
„ 5V CMOS and 30V Bipolar: 2MHz (maximum) @ G=+1
The system’s error will increase and repeatability will decrease as these limits are
approached or breached. Higher slew rates can be measured on higher voltage parts due
to the scaling resistors placed at the output. The slew rate and overload recovery time
measurements are mostly limited by the clock speed of the FPGA state machine. The
gain-bandwidth product measurement is limited by the speed of the LM211 comparators
used in the design. To measure parts with gain-bandwidth products greater than 2MHz,
the device should be configured to provide a gain larger than +1V/V.
78
6.3 Cost savings
The current system design can be manufactured and populated for under $1,000.
The results seen when testing the OPA347 and OPA277 are comparable in accuracy and
repeatability to what would be expected when using expensive automated test equipment.
Similarly, the measurements proved to be nearly as accurate as manual bench testing, but
with much higher speed. Also, when using the designed system a function generator and
expensive oscilloscope are not needed.
6.4 Future work
Another revision of system could help to improve the results of those tests which
were successful, and also help solve problems related to settling time and channel
separation tests. First, the Test and Measurement Board and Frequency Synthesizer
Board should be combined onto one circuit board. A high quality PCB containing more
internal power layers would help to reduce noise present in the system. Internal layers
would optimally be dedicated to +5V, -5V, +15V, -15V, and GND.
The Altera FPGA should be replaced with a bigger and faster device. This could
help to improve measurement resolutions, which should lead to decreased system error.
This would also allow for both pieces of FPGA software to be combined into one unit.
Devices from other manufacturers, such as Xilinx, should be considered. An external
memory-mapped SRAM should also be added to the microcontroller to allow for
increased program sizes.
A power pad heat sink should be added to the TI THS7001 PGA footprint on the
next circuit board revision. Decreased temperature should theoretically lead to improved
noise performance. Another PGA may also be used to replace the resistor scaling method
used in the current design. Many PGAs, including the THS7001, also have output
voltage clamping to protect connected analog-to-digital converters.
The method of generating square waves should also be improved. This may be
done by amplifying the square wave from the Frequency Synthesizer Card and using
clamping diodes set to +1V. Other methods independent of the Frequency Synthesizer
79
Card should also be considered. For instance, a digital-to-analog converter could be used
to generate sharp square wave edges with low noise and ringing.
To improve the channel separation test, high-Q bandpass filters should be added
to the null-output terminals of the DUT socket. These filters would theoretically only
allow for the desired crosstalk frequency (i.e. 15kHz) to pass to the peak detector circuits.
It would be prudent to make these filters adjustable so that they could be tuned to the
desired frequency. Additionally, the peak detector circuits should be altered to allow for
no more than +2.5V at their outputs. As currently configured, they can possibly damage
the sensitive inputs of the ADC by applying too large of a voltage.
A graphical user interface could also be created to make the system more user
friendly. Such an application could be programmed using Visual Basic, or another
similar language.
80
REFERENCES
1.
E. Miguelanez, “Semiconductor In-Fab Wafer Processing”, Retrieved March 19,
2005, from http://www.cee.hw.ac.uk/~ceeem1/ research/wafer_proc.html.
2.
C. Amos, “Faster, smaller, smarter, embedded data acquisition”, Retrieved March
19, 2005 from http://www.automationworld.com/cds_print.html?rec_id=517.
3.
R. Mancini, “Op Amps for Everyone”, 1st Edition, Newnes, 2002.
4.
S. Hidalgo, “DC Automated Bench Solution For A Dual Operational Amplifier in
Chip Scale Package”, Texas Tech University, 2003.
5.
A. Sedra and K. Smith, “Microelectronic Circuits”, Fourth Edition, Oxford
University Press, 1998.
6.
Texas Instruments Incorporated, “OPA277 product data sheet”, June 2000.
7.
Texas Instruments Incorporated, “OPA347 product data sheet”, June 2003.
8.
Texas Instruments Incorporated, “OPA37 product data sheet”, February 2005.
9.
Texas Instruments Incorporated, “OPA637 product data sheet”, June 2000.
10. Maxim Integrated Products, “MAX038 product data sheet”, 2004.
11. Texas Instruments Incorporated, “THS7001 product data sheet”, August 1999.
12. Altera Corporation, “Flex 10K Embedded Programmable Logic Device Family Data
Sheet”, January 2003.
13. M. Burns and G. W. Roberts, “An Introduction to Mixed-Signal IC Test and
Measurement”, Oxford University Press, New York, 2001.
81
APPENDIX A
EXAMPLE MICROCONTROLLER TEST PROGRAMS
82
Common.asm
** Code common to all test programs. Include common.asm in other files by typing
**
#include "common.asm"
** This program assumes the following Memory Map:
**
Interanl Registers $0000 - $03FF
**
Internal Ram $0800 - $08FF (256 byte page)
**
Internal Ram $0900 - $0BFF (768 byte page)
**
Internal EEPROM $0D00 - $0FFF
(768 byte page)
**
U23 Relay Driver [RelayDrive01..08]
$8000 - $8FFF
**
U25 Relay Driver [RelayDrive09..16]
$9000 - $9FFF
**
U27 Relay Driver [RelayDrive17..23]
$A000 - $AFFF
**
External EEPROM $C000 - $FFFF
**
$E000 - $FFFF Monitor Program + Vectors
** Monitor program uses 0800 - 087F for itself. So I am leaving the 256-byte page $0800 to
** $08FF for Monitor & stack and claim $0900 to $0BFF (768-bytes) as storage space for this
** code. This will give about 140+ bytes for our stack this way before running into Monitor's
** variables.
** Some print routines were modeled from original source code in Monitor
** operating system developed by the University of Florida.
** Setup SPI interface ** Example on pg. 226 of M68HC12B.pdf **
********************************************************************
** MEMORY RESERVE
********************************************************************
** 1 word stores up to 65536, or about 3.2ms at 20MHz (50ns resolution)
** 1 word stores up to 65536, or about 65MHz (1kHz resolution)
83
org
$0900
;Leave until $090F (16 ;bytes) for allocations
SRupresultH
ds.b
1
;byte #0900
SRupresultL
ds.b
1
;byte #0901
SRdnresultH
ds.b
1
;byte #0902
SRdnresultL
ds.b
1
;byte #0903
OVERLvccresultH
ds.b
1
;byte #0904
OVERLvccresultL
ds.b
1
;byte #0905
OVERLveeresultH
ds.b
1
;byte #0906
OVERLveeresultL
ds.b
1
;byte #0907
SETLG01vccresultH ds.b
1
;byte #0908
SETLG01vccresultL ds.b
1
;byte #0909
SETLG01veeresultH ds.b
1
;byte #090A
SETLG01veeresultL ds.b
1
;byte #090B
GBWPresultH
ds.b
1
;byte #090C
GBWPresultL
ds.b
1
;byte #090D
CHSEPresultH
ds.b
1
;byte #090E
CHSEPresultL
ds.b
1
;byte #090F
Iterations
ds.b
1
;max iterations = 255
********************************************************************
** SUBROUTINES
********************************************************************
org
$0A00
** Gain bandwidth test
GBPtest:
jsr
clrSPI
;Clear flags just in case
movb
#GBWP1, SP0DR
;Send "gain bandwidth" op-code to FPGA
brclr
PortP,#$08,Testdone
;Wait for testdone flag from FPGA
jsr
clrSPI
;Clear flags just in case
Testdone:
84
movb
#GBWP2, SP0DR
;Transfer result high-byte from FPGA
brclr
SP0SR,#$80,Flag5A
;Wait for flag
ldaa
SP0DR
;Result from FPGA place in RegA
staa
GBWPresultH
;Store result into allocated memory
jsr
clrSPI
;Clear flags just in case
jsr
wait
;Wait
movb
#GBWP3, SP0DR
;Transfer result low-byte from FPGA
brclr
SP0SR,#$80,Flag5B
;Wait for flag
ldaa
SP0DR
;Result from FPGA place in RegA
staa
GBWPresultL
;Store result into allocated memory
Flag5A:
Flag5B:
rts
** Overload recovery time (Vcc)
ORTVCCtest:
jsr
clrSPI
;Clear flags just in case
movb
#OVERL1A, SP0DR
;Send "overload (Vcc)" op-code to FPGA
Testdone1:
brclr
PortP,#$08,Testdone1
;Wait for testdone flag from FPGA
jsr
clrSPI
;Clear flags just in case
movb
#OVERL2, SP0DR
;Transfer result high-byte from FPGA
brclr
SP0SR,#$80,Flag3A
;Wait for flag
ldaa
SP0DR
;Result from FPGA place in RegA
staa
OVERLvccresultH
;Store result into allocated memory
jsr
clrSPI
;Clear flags just in case
jsr
wait
;Wait
Flag3A:
85
movb
#OVERL3, SP0DR
;Transfer result low-byte from FPGA
brclr
SP0SR,#$80,Flag3B
;Wait for flag
ldaa
SP0DR
;Result from FPGA place in RegA
staa
OVERLvccresultL
;Store result into allocated memory
jsr
wait
;Wait
Flag3B:
rts
** Overload recovery time (Vee)
ORTVEEtest:
jsr
clrSPI
;Clear flags just in case
movb
#OVERL1B, SP0DR
;Send "overload (Vee)" op-code to FPGA
Testdone2:
brclr
PortP,#$08,Testdone2
;Wait for testdone flag from FPGA
jsr
clrSPI
;Clear flags just in case
movb
#OVERL2, SP0DR
;Transfer result high-byte from FPGA
brclr
SP0SR,#$80,Flag4A
;Wait for flag
ldaa
SP0DR
;Result from FPGA place in RegA
staa
OVERLveeresultH
;Store result into allocated memory
jsr
clrSPI
;Clear flags just in case
jsr
wait
;Wait
movb
#OVERL3, SP0DR
;Transfer result low-byte from FPGA
brclr
SP0SR,#$80,Flag4B
;Wait for flag
ldaa
SP0DR
;Result from FPGA place in RegA
staa
OVERLveeresultL
;Store result into allocated memory
jsr
wait
;Wait
Flag4A:
Flag4B:
86
rts
** Rising edge slew-rate test
SRrise:
jsr
clrSPI
;Clear flags just in case
movb
#SLEWR1A, SP0DR
;Send "slew-rate" op-code to FPGA
Testdone3:
brclr
PortP,#$08,Testdone3
;Wait for testdone flag from FPGA
jsr
clrSPI
;Clear flags just in case
movb
#SLEWR2, SP0DR
;Transfer result high-byte from FPGA
brclr
SP0SR,#$80,Flag1A
;Wait for flag
ldaa
SP0DR
;Result from FPGA place in RegA
staa
SRupresultH
;Store result into allocated memory
jsr
clrSPI
;Clear flags just in case
jsr
wait
;Wait
movb
#SLEWR3, SP0DR
;Transfer result low-byte from FPGA
brclr
SP0SR,#$80,Flag1B
;Wait for flag
ldaa
SP0DR
;Result from FPGA place in RegA
staa
SRupresultL
;Store result into allocated memory
jsr
wait
;Wait
Flag1A:
Flag1B:
rts
** Falling edge slew-rate test
SRfall:
jsr
clrSPI
;Clear flags just in case
movb
#SLEWR1B, SP0DR
;Send "slew-rate" op-code to FPGA
87
Testdone4:
brclr
PortP,#$08,Testdone4
;Wait for testdone flag from FPGA
jsr
clrSPI
;Clear flags just in case
movb
#SLEWR2, SP0DR
;Transfer result high-byte from FPGA
brclr
SP0SR,#$80,Flag2A
;Wait for flag
ldaa
SP0DR
;Result from FPGA place in RegA
staa
SRdnresultH
;Store result into allocated memory
jsr
clrSPI
;Clear flags just in case
jsr
wait
;Wait
movb
#SLEWR3, SP0DR
;Transfer result low-byte from FPGA
Flag2A:
Flag2B:
brclr SP0SR,#$80,Flag2B
;Wait for flag
ldaa
SP0DR
;Result from FPGA place in RegA
staa
SRdnresultL
;Store result into allocated memory
jsr
wait
;Wait
rts
** Clear memory locations
clearm:
movw
#$FFFF, SRupresultH
;clear memory locations w/ $FF
movw
#$FFFF, SRdnresultH
; using 16-bit MOVM instruction
movw
#$FFFF, OVERLvccresultH
; takes care of the lower 8-bits that way
movw
#$FFFF, OVERLveeresultH
movw
#$FFFF, SETLG01vccresultH
movw
#$FFFF, SETLG01veeresultH
movw
#$FFFF, GBWPresultH
movw
#$FFFF, CHSEPresultH
rts
88
** Reset for relays K01 - K23 **
resALL:
bclr
PortP, #%00000111
;Set gain of 0.08 (lowest) in U02
movb
#%00000000, U23driver
;reset K01-K08
movb
#%00000001, U25driver
;reset K09-K16
movb
#%00000000, U27driver
;reset K17-K23 to defualt positions
rts
** PGA Settings **
setupPP:
movb
#%00000111, DDRP
;Setup PP[2:0] outputs, PP[7:3] inputs
PortP, #%00000111
;Set gain of 0.08 in U02
bclr
PortP, #%00000110
;Set gain of 0.16 in U02
bset
PortP, #%00000001
rts
PGA008:
bclr
rts
PGA016:
rts
PGA032:
bclr
PortP, #%00000101
bset
PortP, #%00000010
;Set gain of 0.32 in U02
rts
PGA063:
bclr
PortP, #%00000100
bset
PortP, #%00000011
;Set gain of 0.63 in U02
rts
PGA126:
bclr
PortP, #%00000011
bset
PortP, #%00000100
;Set gain of 1.26 in U02
rts
PGA252:
89
bclr
PortP, #%00000010
bset
PortP, #%00000101
;Set gain of 2.52 in U02
rts
PGA501:
bclr
PortP, #%00000001
bset
PortP, #%00000110
;Set gain of 5.01 in U02
rts
PGA100:
bset
PortP, #%00000111
;Set gain of 10.0 in U02
bset
PortS, #%10000000
;Sets /SS high to prevent glitch
bset
DDRS, #%10000000
;Make /SS an output
bset
DDRS, #%01000000
;Make SCK an output
bset
DDRS, #%00100000
;Make MOSI an output
bclr
DDRS, #%00010000
;Make MISO an input
movb
#%00000010, SP0BR
;Set SPI clock at Eclock/8
movb
#%00010010, SP0CR1
;MSTR=1, CPOL=0, CPHA=0, no INTs, SSOE=1
movb
#%00001000, SP0CR2
;PortS outs normal,inputs have pull-ups
ldaa
SP0SR
;load SR to clear flags
ldaa
SP0DR
;load DR to clear flags
bset
SP0CR1,#%01000000
;turn on SPI system (SPE=1)
ldaa
SP0SR
;load SR to clear flags
ldaa
SP0DR
;load DR to clear flags
rts
setSPI:
rts
clrSPI:
rts
** Wait timers **
wait:
90
ldx
#$01F4
;outside loop
#$7D
;inside loop
loop2:
ldaa
loop1:
deca
bne
loop1
dex
bne
loop2
rts
** Holds the tester in continuous looping state. Will have to reset processor to get out of loop.
Hold
jmp
Hold
** Print number prints in ASCII hex the number in register A
print_number:
psha
anda
; saves state of A
#%11110000
lsra
; get upper nibble for the first number
; shift it right to get the nibble
lsra
lsra
lsra
bsr
pn_doit
pula
; change A and print it pn_next:
; get the next nibble
anda
#%00001111
; mask to do so
bsr
pn_doit
; change A and print it
cmpa
#$09
; is it greater than 9?
bgt
pn_abcdef
; if so, print a character
adda
#48
; if not, print a number starting at 48 ASCII
bra
pn_print
rts
pn_doit:
91
pn_abcdef:
adda
#55
; if so, print a letter starting at 55, = 65-10
put_char
; print it
pn_print:
bsr
rts
; return
** Put_char sends the character in A register out the serial port if possible it checks the TC flag
** and blocks until it is set.
put_char:
psha
bsr
; save A because tc_check messes it up
tc_check
; checks TX status register to make sure
pula
staa
; can transfer. restores status of A
SC0DRL
; loads A onto the data register to be transfered
rts
; returns
** Polling subroutine to make sure system is ready before transferring another character
tc_check:
psha
; saves the state of a, which will be modified
tc_2:
ldaa
SC0SR1
; checks the transfer complete status bit in the
anda
#%01000000
; status register by anding it with the proper
beq
tc_2
; bit, keeps polling if transfer is not complete
pula
; restores state of a
rts
; returns
********************************************************************
** EQUATES begin
********************************************************************
Monitor
equ
$E000
;Location of Monitor program (in EEPROM)
Stack
equ
$08FF
;Internal RAM
92
U23driver
equ
$8000
;Driver for Relays01:08 on board
U25driver
equ
$9000
;Driver for Relays09:16 on board
U27driver
equ
$A000
;Driver for Relays17:23 on board
PortP
equ
$0056
;PortP Data Register
DDRP
equ
$0057
;PortP Data Direction Register
PortT
equ
$00AE
;General Input/Output Pins on Port T
DDRT
equ
$00AF
;Port T Data Direction Register
SP0CR1
equ
$00D0
;SPI Control Register 1
SP0CR2
equ
$00D1
;SPI Control Register 2
SP0BR
equ
$00D2
;SPI Baud Rate Register
SP0SR
equ
$00D3
;SPI Status Register
SP0DR
equ
$00D5
;SPI Data Register
PortS
equ
$00D6
;PortS Data Register
DDRS
equ
$00D7
;PortS Data Direction Register
INIT
equ
$68
;Initialization dummy op-code
SLEWR1A
equ
$69
;Start slew-rate op-code (rising)
SLEWR1B
equ
$70
;Start slew-rate op-code (falling)
SLEWR2
equ
$71
;Get slew-rate result high-byte code
SLEWR3
equ
$72
;Get slew-rate result low-byte code
OVERL1A
equ
$73
;Start overload recovery op-code (Vcc)
OVERL1B
equ
$74
;Start overload recovery op-code (Vee)
OVERL2
equ
$75
;Get overload result high-byte code
OVERL3
equ
$76
;Get overload result low-byte code
SETLG1A
equ
$77
;Start settling time 0.1% op-code (Vcc)
SETLG1B
equ
$78
;Start settling time 0.1% op-code (Vee)
SETLG2
equ
$79
;Get settling time 0.1% high-byte code
SETLG3
equ
$7A
;Get settling time 0.1% low-byte code
GBWP1
equ
$7B
;Start gain-bandwidth test op-code
GBWP2
equ
$7C
;Get gain-bandwidth high-byte code
GBWP3
equ
$7D
;Get gain-bandwidth low-byte code
CHSEP1
equ
$7E
;Start channel separation test op-code
CHSEP2
equ
$7F
;Get channel separation high-byte code
93
CHSEP3
equ
$80
;Get channel separation low-byte code
SC0SR1
equ
$00C4
;SCI Status Register 1
SC0DRL
equ
$00C7
;SCI Data Register Low
OPA347-gbw.asm
** Test program for testing gain-bandwidth product of the
** Texas Instruments OPAx347
org
$0911
lds
#Stack
sei
;Don't run into memory allocations
;Disable interrupts
jsr
setupPP
;Setup PortP[2:0] as outputs, rest as inputs
jsr
setSPI
;Setup SPI in master-mode
jsr
clearm
;Clear memory locations reserved for test results
movb
#INIT, SP0DR
;Send "initialization" op-code to FPGA
jsr
wait
;Wait
jsr
clrSPI
;Clear flags just in case
movb
#$0A, Iterations
;(hex) Determine how many times to run tests
jsr
resALL
;Reset all relays to default pos, PGA=0.08V/V
movb
#%10001010, U27driver
;Relays 17-23-X (good idea to do power relays first)
movb
#%11000001, U25driver
;Relays 9-16
movb
#%00100001, U23driver
;Relays 1-8
jsr
wait
;Wait for relays to settle out
jsr
GBPtest
;Runs gain-bandwidth product test
jsr
printrs
;Print results of test
dec
Iterations
;Decrement 'Iterations'
beq
TheEnd
;If zero, go to end
jmp
Start
; Otherwise, go run test sequence again
Start:
94
TheEnd:
jsr
resALL
jmp
Monitor
;Reset all relays to default pos, PGA=0.08V/V
printrs:
ldaa
Iterations
jsr
print_number
ldaa
#$3A
jsr
put_char
ldaa
#$20
jsr
put_char
ldaa
GBWPresultH
jsr
print_number
ldaa
GBWPresultL
jsr
print_number
ldaa
#$0A
jsr
put_char
ldaa
#$0D
jsr
put_char
; colon
; new line
; carraige return
rts
#include "common.asm"
OPA277-gbw.asm
** Test program for testing gain-bandwidth product of the Texas Instruments OPAx277
org
$0911
lds
#Stack
sei
;Don't run into memory allocations
;Disable interrupts
95
jsr
setupPP
;Setup PortP[2:0] as outputs, rest as inputs
jsr
setSPI
;Setup SPI in master-mode
jsr
clearm
;Clear memory locations reserved for test results
movb
#INIT, SP0DR
;Send "initialization" op-code to FPGA
jsr
wait
;Wait
jsr
clrSPI
;Clear flags just in case
movb
#$0A, Iterations
;(hex) Determine how many times to run tests
jsr
resALL
;Reset all relays to default pos, PGA=0.08V/V
movb
#%10001110, U27driver
;Relays 17-23-X (good idea to do power relays first)
movb
#%10000001, U25driver
;Relays 9-16
movb
#%00100001, U23driver
;Relays 1-8
jsr
wait
;Wait for all the relays to settle out
jsr
GBPtest
;Runs gain-bandwidth product test
jsr
printrs
;Print results of test
dec
Iterations
;Decrement 'Iterations'
beq
TheEnd
;If zero, go to end
jmp
Start
; Otherwise, go run test sequence again
jsr
resALL
;Reset all relays to default pos, PGA=0.08V/V
jmp
Monitor
Start:
TheEnd:
printrs:
ldaa
Iterations
jsr
print_number
ldaa
#$3A
jsr
put_char
ldaa
#$20
jsr
put_char
ldaa
GBWPresultH
; colon
96
jsr
print_number
ldaa
GBWPresultL
jsr
print_number
ldaa
#$0A
jsr
put_char
ldaa
#$0D
jsr
put_char
; new line
; carraige return
rts
#include "common.asm"
OPA347-sror.asm
** Test program for testing slew rates and overload recovery times of the Texas Instruments
** OPAx347
org
$0911
lds
#Stack
sei
;Don't run into memory allocations
;Disable interrupts
jsr
setupPP
;Setup PortP[2:0] as outputs
jsr
setSPI
;Setup SPI in master-mode
jsr
clearm
;Clear memory locations reserved for results
movb
#INIT, SP0DR
;Send "initialization" op-code to FPGA
jsr
wait
;Wait
jsr
clrSPI
;Clear flags just in case
movb
#$0A, Iterations
;(hex) how many times to run test sequence
Start:
** Overload recovery tests (Vcc and Vee)
** R05=40K, R07=60K <-- Gain = +2.5V/V in non-inverting configuration
** Also yields 100K load in non-inverting configuration
97
** C90 cap (100pF) load is also switched in
** Typical value from PDS is 23us
jsr
resALL
;Reset all relays to default pos, PGA=0.08V/V
movb
#%10001010, U27driver
;Relays 17-23-X (good idea to do power relays first)
movb
#%11000001, U25driver
;Relays 9-16
movb
#%01000101, U23driver
;Relays 1-8
jsr
wait
;Wait for all the relays to settle out
jsr
ORTVCCtest
;Do overload recovery time Vcc test
jsr
ORTVEEtest
;Do overload recovery time Vee test
** Slew rate tests (up and down)
** R11=100K Used in buffer configuration, proving correct load C90 cap (100pF) load is also
** switched in. Typical value from PDS is 0.17V/us, or 9.41us for 1.6V swing
jsr
resALL
;Reset all relays to default pos, PGA=0.08V/V
movb
#%10001010, U27driver
;Relays 17-23-X (good idea to do power relays first)
movb
#%11100001, U25driver
;Relays 9-16
movb
#%00100001, U23driver
;Relays 1-8
jsr
wait
;Wait for all the relays to settle out
jsr
SRrise
;Do rising-edge slew rate test
jsr
SRfall
;Do falling-edge slew rate test
jsr
printrs
;Print results of test
dec
Iterations
;Decrement 'Iterations'
beq
TheEnd
;If zero, go to end
jmp
Start
; Otherwise, go run test sequence again
jsr
resALL
;Reset all relays to default pos, PGA=0.08V/V
jmp
Monitor
TheEnd:
printrs:
98
ldaa
Iterations
jsr
print_number
ldaa
#$3A
jsr
put_char
ldaa
#$20
jsr
put_char
ldaa
SRupresultH
jsr
print_number
ldaa
SRupresultL
jsr
print_number
ldaa
#$20
jsr
put_char
ldaa
SRdnresultH
jsr
print_number
ldaa
SRdnresultL
jsr
print_number
ldaa
#$20
jsr
put_char
ldaa
OVERLvccresultH
jsr
print_number
ldaa
OVERLvccresultL
jsr
print_number
ldaa
#$20
jsr
put_char
ldaa
OVERLveeresultH
jsr
print_number
ldaa
OVERLveeresultL
jsr
print_number
ldaa
#$0A
jsr
put_char
ldaa
#$0D
jsr
put_char
; colon
; new line
; carraige return
99
rts
#include "common.asm"
OPA277-sror.asm
** Test program for testing slew rates and overload recovery times of the Texas Instruments
** OPAx277
org
$0911
lds
#Stack
sei
;Don't run into memory allocations
;Disable interrupts
jsr
setupPP
;Setup PortP[2:0] as outputs
jsr
setSPI
;Setup SPI in master-mode
jsr
clearm
;Clear memory locations reserved for results
movb
#INIT, SP0DR
;Send "initialization" op-code to FPGA
jsr
wait
;Wait
jsr
clrSPI
;Clear flags just in case
movb
#$0A, Iterations
;(hex) Determine how many times to run tests
Start:
** Overload recovery tests (Vcc and Vee)
** R05=133, R07=1867 <-- Gain = +15V/V in non-inverting configuration. Also yields 2K load
** in non-inverting configuration. C90 cap (100pF) load is NOT switched in. Scaling to 16.7%
** output w/ 100K@R27 and 20K@R29. Typical value from PDS is 3us.
jsr
resALL
;Reset all relays to default pos, PGA=0.08V/V
movb
#%10001110, U27driver
;Relays 17-23-X (good idea to do power relays first)
movb
#%10000101, U25driver
;Relays 9-16
movb
#%01000101, U23driver
;Relays 1-8
100
jsr
wait
;Wait for all the relays to settle out
jsr
ORTVCCtest
;Do overload recovery time Vcc test
jsr
ORTVEEtest
;Do overload recovery time Vee test
** Slew rate tests (up and down)
** R11=2K Used in buffer configuration, proving correct load. C90 cap (100pF) load is NOT
** switched in. Scaling to 16.7% output w/ 100K@R27 and 20K@R29. Typical value from
** PDS is 0.8V/us, or 4.44us for 8V swing.
jsr
resALL
;Reset all relays to default pos, PGA=0.08V/V
movb
#%00001110, U27driver
;Relays 17-23-X (good idea to do power relays first)
movb
#%10100101, U25driver
;Relays 9-16
movb
#%00100001, U23driver
;Relays 1-8
jsr
PGA501
jsr
wait
;Wait for all the relays to settle out
jsr
SRrise
;Do rising-edge slew rate test
jsr
SRfall
;Do falling-edge slew rate test
jsr
printrs
;Print results of test
dec
Iterations
;Decrement 'Iterations'
beq
TheEnd
;If zero, go to end
jmp
Start
; Otherwise, go run test sequence again
jsr
resALL
;Reset all relays to default pos, PGA=0.08V/V
jmp
Monitor
TheEnd:
printrs:
ldaa
Iterations
jsr
print_number
ldaa
#$3A
jsr
put_char
; colon
101
ldaa
#$20
jsr
put_char
ldaa
SRupresultH
jsr
print_number
ldaa
SRupresultL
jsr
print_number
ldaa
#$20
jsr
put_char
ldaa
SRdnresultH
jsr
print_number
ldaa
SRdnresultL
jsr
print_number
ldaa
#$20
jsr
put_char
ldaa
OVERLvccresultH
jsr
print_number
ldaa
OVERLvccresultL
jsr
print_number
ldaa
#$20
jsr
put_char
ldaa
OVERLveeresultH
jsr
print_number
ldaa
OVERLveeresultL
jsr
print_number
ldaa
#$0A
jsr
put_char
ldaa
#$0D
jsr
put_char
; new line
; carraige return
rts
#include "common.asm"
102
APPENDIX B
FPGA SUBSYSTEMS
103
RUNTESTS.vhd
-- Runtests subsystem is the state machine that does the majority of the work.
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity runtests is port(
-- DAC: DACdbA/B/C/D[15..0], writetoDACs, DACSdone
DACdbA,DACdbB,DACdbC,DACdbD
: out std_logic_vector(15 downto 0);
writetoDACs
: out std_logic;
DACSdone
: in std_logic;
-- ADC: ADCretrieved[15..0], ADCdone, ADCchA1/0, readfromADC
ADCretrieved
: in std_logic_vector(15 downto 0);
ADCdone
: in std_logic;
ADCchA1, ADCchA0, readfromADC
: out std_logic;
-- WaveformGenerator: wave_sync, wave_select, freq[13..0]
wave_sync
: in std_logic;
wave_select
: out std_logic;
freq
: buffer std_logic_vector(13 downto 0);
-- Triggers: triggerA, triggerB, triggerC, triggerD
triggerA, triggerB, triggerC, triggerD
: in std_logic;
-- SPI: ss, SPIreceived[7..0], SPIsendLOAD, SPIsend[7..0]
ss
: in std_logic;
SPIreceived
: in std_logic_vector(7 downto 0);
SPIsend
: out std_logic_vector(7 downto 0);
SPIsendLOAD
: out std_logic;
-- Others fastclk, count[15..0], clrcount
fastclk
: in std_logic;
count
: in std_logic_vector(15 downto 0);
GPIO
: out std_logic_vector(7 downto 0);
clrcount
: out std_logic;
testdone
: out std_logic );
end runtests;
104
Architecture behavior of runtests is
type state_type is (
start,setup01,setup02,setup03,
tA01,tA02,tA03,tA04,tA05,tA06,
tA15,tA16,tA17,tA18,tA19,
tA20,tA21,tA22,tA23,tA24,tA25,tA26,tA27,tA28,tA29,
tA30,tA31,tA32,tA33,tA34,tA35,tA36,tA37,tA38,tA39,
tA40,tA41,tA42,tA43,tA44,tA45,tA46,
tA50,tA51,tA52,tA53,tA54,tA55,tA56 );
signal prior_state, pres_state, next_state : state_type;
signal result
: std_logic_vector(15 downto 0);
signal PGAgain
: std_logic_vector(7 downto 0);
begin
process(prior_state, pres_state, next_state, fastclk)
begin
if(rising_edge(fastclk)) then
prior_state <= pres_state;
pres_state <= next_state;
case prior_state is
-- Wait for SS transistion low and then high (SPI data swap complete). Load received byte into temp
-- register. Depending on op-code, jump to test, or if not valid (or INIT), jump back to beginning of
-- program.
when start =>
SPIsendLOAD <= '0';
writetoDACs <= '0';
testdone <= '0';
clrcount <= '1';
-- clear external counter
freq <= "00000000000001";
-- slowest possible square wave
wave_select <= '0';
-- square=0, sine=1
DACdbA <= "0000000000000000";
-- -2.5V
105
DACdbB <= "0000000000000000";
-- -2.5V
DACdbC <= "0000000000000000";
-- -2.5V
DACdbD <= "0000000000000000";
-- -2.5V
next_state <= setup01;
when setup01 =>
if(ss = '0') then next_state <= setup02;
else next_state <= setup01;
end if;
when setup02 =>
if(ss = '1') then next_state <= setup03;
else next_state <= setup02;
end if;
when setup03 =>
-- h69(SR rising), h70(SR falling), h73(OverloadVcc), h74(OverloadVee)
if SPIreceived = "01101001" then next_state <= tA01;
elsif SPIreceived = "01110000" then next_state <= tA01;
elsif SPIreceived = "01110011" then next_state <= tA01;
elsif SPIreceived = "01110100" then next_state <= tA01;
else next_state <= start;
end if;
-- SLEW RATE &OVERLOAD RECOVERY tests: Set freq synth board to slowest possible square wave.
-- Set two DAC channels to predetermined voltage levels. Monitor their corresponding trigger signals. At
-- first trigger, clear (zero) the counter. At second trigger, record the value at 'count'.
when tA01 =>
SPIsendLOAD <= '0';
writetoDACs <= '0';
freq <= "00000000000001";
-- slowest possible square wave
wave_select <= '0';
-- square='0', sine='1'
clrcount <= '1';
-- clear external counter
next_state <= tA02;
when tA02 =>
if SPIreceived = "01101001" then
-- rising slew rate
DACdbA <= "0000000000000000";
-- -2.5V
106
DACdbB <= "0101110111011110";
-- set low (1st) trigger to -0.667V PA277)
DACdbC <= "1010001000100010";
-- set high (2nd) trigger to +0.667V (OPA277)
--
DACdbB <= "0101011100001010";
-- set low (1st) trigger to -0.8V (OPA347)
--
DACdbC <= "1010100011110101";
-- set high (2nd) trigger to +0.8V (OPA347)
DACdbD <= "0000000000000000";
-- -2.5V
elsif SPIreceived = "01110000" then
-- falling slew rate
DACdbA <= "0000000000000000";
-- -2.5V
DACdbB <= "0101110111011110";
-- set low (1st) trigger to -0.667V (OPA277)
DACdbC <= "1010001000100010";
-- set high (2nd) trigger to +0.667V (OPA277)
--
DACdbB <= "0101011100001010";
-- set low (1st) trigger to -0.8V CMOS (OPA347)
--
DACdbC <= "1010100011110101";
-- set high (2nd) trigger to +0.8V (OPA347)
DACdbD <= "0000000000000000";
-- -2.5V
elsif SPIreceived = "01110011" then
-- overload Vcc
DACdbA <= "0000000000000000";
-- -2.5V
DACdbB <= "0000000000000000";
-- -2.5V
DACdbC <= "1111000110101010";
-- set output (2nd) trigger to +2.22V (OPA277)
DACdbC <= "1111010111000010";
-- set output (2nd) trigger to +2.3V (OPA347)
DACdbD <= "1000000000000000";
-- set input (1st) trigger to 0V
elsif SPIreceived = "01110100" then
-- overload Vee
DACdbA <= "0000000000000000";
-- -2.5V
DACdbB <= "0000000000000000";
-- -2.5V
DACdbC <= "0001000011100101";
-- set output (2nd) trigger to -2.17V (OPA277)
DACdbC <= "0000101000111101";
-- set output (2nd) trigger to -2.3V (OPA347)
DACdbD <= "1000000000000000";
-- set input (1st) trigger to 0V
--
--
end if;
next_state <= tA03;
when tA03 =>
writetoDACs <= '1';
next_state <= tA04;
when tA04 =>
writetoDACs <= '1';
next_state <= tA05;
when tA05 =>
writetoDACs <= '0';
next_state <= tA06;
107
when tA06 =>
if(DACSdone = '1') then next_state <= tA33;
else next_state <= tA06;
end if;
when tA33 =>
if SPIreceived = "01101001" then next_state <= tA15;
-- rising slew rate
elsif SPIreceived = "01110000" then next_state <= tA34;
-- falling slew rate
elsif SPIreceived = "01110011" then next_state <= tA40;
-- overload Vcc
elsif SPIreceived = "01110100" then next_state <= tA50;
-- overload Vee
end if;
-- Rising edge SR
when tA15 =>
-- wait for triggerB to be low
if(triggerB = '0') then next_state <= tA16;
else next_state <= tA15;
end if;
when tA16 =>
-- wait for triggerB to go high
if(triggerB = '1') then next_state <= tA17;
else next_state <= tA16;
end if;
when tA17 =>
clrcount <= '1';
-- clear external counter
next_state <= tA18;
when tA18 =>
clrcount <= '0';
-- allow counter to count
next_state <= tA19;
when tA19 =>
-- triggerC should be low
next_state <= tA20;
when tA20 =>
-- wait for triggerB to go high
if(triggerC = '1') then next_state <= tA21;
else next_state <= tA20;
end if;
-- Falling edge SR
when tA34 =>
-- wait for triggerC to be high
108
if(triggerC = '1') then next_state <= tA35;
else next_state <= tA34;
end if;
when tA35 =>
-- wait for triggerC to go low
if(triggerC = '0') then next_state <= tA36;
else next_state <= tA35;
end if;
when tA36 =>
clrcount <= '1';
-- clear external counter
next_state <= tA37;
when tA37 =>
clrcount <= '0';
-- allow counter to count
next_state <= tA38;
when tA38 =>
-- triggerB should be high
next_state <= tA39;
when tA39 =>
-- wait for triggerB to go low
if(triggerB = '0') then next_state <= tA21;
else next_state <= tA39;
end if;
-- Overload recovery time (Vcc)
when tA40 =>
-- wait for triggerC to be high
if(triggerC = '1') then next_state <= tA41;
else next_state <= tA40;
end if;
when tA41 =>
-- wait for triggerD to be high
if(triggerD = '1') then next_state <= tA42;
else next_state <= tA41;
end if;
when tA42 =>
-- wait for triggerD to go low
if(triggerD = '0') then next_state <= tA43;
else next_state <= tA42;
end if;
when tA43 =>
clrcount <= '1';
-- clear external counter
109
next_state <= tA44;
when tA44 =>
clrcount <= '0';
-- allow counter to count
next_state <= tA45;
when tA45 =>
-- triggerC should be high
next_state <= tA46;
when tA46 =>
-- wait for triggerC to go low
if(triggerC = '0') then next_state <= tA21;
else next_state <= tA46;
end if;
-- Overload recovery time (Vee)
when tA50 =>
-- wait for triggerC to be low
if(triggerC = '0') then next_state <= tA51;
else next_state <= tA50;
end if;
when tA51 =>
-- wait for triggerD to be low
if(triggerD = '0') then next_state <= tA52;
else next_state <= tA51;
end if;
when tA52 =>
-- wait for triggerD to go high
if(triggerD = '1') then next_state <= tA53;
else next_state <= tA52;
end if;
when tA53 =>
clrcount <= '1';
-- clear external counter
next_state <= tA54;
when tA54 =>
clrcount <= '0';
-- allow counter to count
next_state <= tA55;
when tA55 =>
-- triggerC should be low
next_state <= tA56;
when tA56 =>
-- wait for triggerC to go high
if(triggerC = '1') then next_state <= tA21;
else next_state <= tA56;
110
end if;
-- Common to all of the tAxx tests (rising SR, falling SR, overload Vcc, overload Vee)
when tA21 =>
result <= count;
-- load 16-bit value from ext counter
next_state <= tA22;
-- COMMON to all tests, return the 16-bit result to the microcontroller. Place the upper byte of the count
-- in the SPI register. Wait for swap. Place the lower byte of the count in the SPI register. Wait for swap.
-- Once done, jump back to beginning of program.
when tA22 =>
SPIsend(7 downto 0) <= result(15 downto 8);
next_state <= tA23;
-- load result high-byte into SPI register
when tA23 =>
SPIsendLOAD <= '1';
next_state <= tA24;
when tA24 =>
SPIsendLOAD <= '0';
testdone <= '1';
next_state <= tA25;
when tA25 =>
if(ss = '0') then next_state <= tA26;
else next_state <= tA25;
end if;
-- wait for SPI transfer
when tA26 =>
if(ss = '1') then next_state <= tA27;
else next_state <= tA26;
end if;
when tA27 =>
SPIsend(7 downto 0) <= result(7 downto 0);
next_state <= tA28;
-- load result low-byte into SPI register
when tA28 =>
SPIsendLOAD <= '1';
next_state <= tA29;
when tA29 =>
111
SPIsendLOAD <= '0';
next_state <= tA30;
when tA30 =>
if(ss = '0') then next_state <= tA31;
else next_state <= tA30;
end if;
-- wait for SPI transfer
when tA31 =>
if(ss = '1') then next_state <= tA32;
else next_state <= tA31;
end if;
when tA32 =>
testdone <= '0';
next_state <= start;
when others =>
-- When lost, always return to the beginning
next_state <= start;
end case;
end if;
end process;
-- Temporary disabled outputs just for compiler's sake....
ADCchA1
<= '0';
ADCchA0
<= '0';
readfromADC
<= '0';
GPIO(7 downto 0)
<= "00000000";
end behavior;
HC12ADDRDEC.vhd
-- Address Decoder for the HC12 microcontroller
Library ieee;
USE ieee.std_logic_1164.all;
112
ENTITY hc12addrdec IS PORT (
A
: IN STD_LOGIC_VECTOR (15 DOWNTO 12);
ECLK, RESET, RW, DBE
: IN STD_LOGIC;
U23_LE, U25_LE, U27_LE
: OUT STD_LOGIC
EEPROM_OE_CE, NOT_ECLK
: OUT STD_LOGIC );
END hc12addrdec;
ARCHITECTURE Logic OF hc12addrdec IS
BEGIN
-- MEM-NOT-ECLK -- U19 Used to demultiplex A15:8 from bus
NOT_ECLK <= NOT ECLK;
-- UP-OUT1-LE -- U23 $8000 - $8FFF -U23_LE <= (NOT RW AND ECLK AND RESET AND DBE AND A(15) AND NOT A(14)
AND NOT A(13) AND NOT A(12));
-- UP-OUT2-LE -- U25 $9000 - $9FFF -U25_LE <= (NOT RW AND ECLK AND RESET AND DBE AND A(15) AND NOT A(14)
AND NOT A(13) AND A(12));
-- UP-OUT3-LE -- U27 $A000 - $AFFF -U27_LE <= (NOT RW AND ECLK AND RESET AND DBE AND A(15) AND NOT A(14)
AND A(13) AND NOT A(12));
-- MEM-EEPROM-OECE -- U22 $C000 - $FFFF -EEPROM_OE_CE <= NOT (RW AND NOT DBE AND RESET AND A(15) AND A(14));
END Logic;
DACCONTROL.vhd
-- Takes in a rising-edge 'writetoDACs' signal, writes all four DACs with values on their respective busses,
-- sends out 'DACSdone' signal.
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
113
Entity daccontrol is port(
fastclk,writetoDACs
: in std_logic;
DACdbA,DACdbB,DACdbC,DACdbD
: in std_logic_vector(15 downto 0);
DACrst,DACchannelA1,DACchannelA0
: out std_logic;
DACloaddacs,DACcs,DACSdone
: out std_logic;
DACdb
: out std_logic_vector(15 downto 0) );
end daccontrol;
Architecture behavior of daccontrol is
subtype state_type is STD_LOGIC_VECTOR(4 downto 0);
constant DACSstart01
: state_type:="00000";
constant DACSstart02
: state_type:="00001";
constant DACS01
: state_type:="00011";
constant DACS02
: state_type:="00010";
constant DACS03
: state_type:="00110";
constant DACS04
: state_type:="00111";
constant DACS05
: state_type:="00101";
constant DACS06
: state_type:="00100";
constant DACS07
: state_type:="01100";
constant DACS08
: state_type:="01101";
constant DACS09
: state_type:="01111";
constant DACS10
: state_type:="01110";
constant DACS11
: state_type:="01010";
constant DACS12
: state_type:="01011";
constant DACS13
: state_type:="01001";
constant DACS14
: state_type:="01000";
constant DACS15
: state_type:="11000";
constant DACS16
: state_type:="11001";
constant DACS17
: state_type:="11011";
constant DACS18
: state_type:="11010";
constant DACS19
: state_type:="11110";
constant DACS20
: state_type:="11111";
constant DACS21
: state_type:="11101";
constant DACS22
: state_type:="11100";
constant DACS23
: state_type:="10100";
114
constant DACS24
: state_type:="10101";
constant DACS25
: state_type:="10111";
constant DACSend
: state_type:="10110";
signal pres_state, next_stat : state_type;
begin
process(pres_state)
begin
case pres_state is
when DACSstart01 => next_state <= DACSstart02;
when DACSstart02 =>
-- wait for start to go high
if(writetoDACs = '1') then next_state <= DACS01;
else next_state <= DACSstart02;
end if;
when DACS01 => next_state <= DACS02; --2
when DACS02 => next_state <= DACS03; --3
when DACS03 => next_state <= DACS04; --4
when DACS04 => next_state <= DACS05; --5
when DACS05 => next_state <= DACS06; --6
when DACS06 => next_state <= DACS07; --7
when DACS07 => next_state <= DACS08; --8
when DACS08 => next_state <= DACS09; --9
when DACS09 => next_state <= DACS10; --10
when DACS10 => next_state <= DACS11; --11
when DACS11 => next_state <= DACS12; --12
when DACS12 => next_state <= DACS13; --13
when DACS13 => next_state <= DACS14; --14
when DACS14 => next_state <= DACS15; --15
when DACS15 => next_state <= DACS16; --16
when DACS16 => next_state <= DACS17; --17
when DACS17 => next_state <= DACS18; --18
when DACS18 => next_state <= DACS19; --19
when DACS19 => next_state <= DACS20; --20
when DACS20 => next_state <= DACS21; --21
when DACS21 => next_state <= DACS22; --22
115
when DACS22 => next_state <= DACS23; --23
when DACS23 => next_state <= DACS24; --24
when DACS24 => next_state <= DACS25; --25
when DACS25 => next_state <= DACSend; --26
when DACSend => next_state <= DACSstart01; --27
when others => next_state <= DACSstart01;
end case;
end process;
process(fastclk)
begin
if(fastclk'event and fastclk = '1' ) then
pres_state <= next_state;
-- DACSdone
if(pres_state=DACSend or pres_state=DACS25 or pres_state=DACS24)
then DACSdone <= '1';
else DACSdone <= '0';
end if;
-- DACrst
if(pres_state=DACSstart01 or pres_state=DACSstart02 or pres_state=DACS01)
then DACrst <= '0';
else DACrst <= '1';
end if;
-- DACcs
if(pres_state=DACS05 or pres_state=DACS06 or pres_state=DACS10 or pres_state=DACS11 or
pres_state=DACS16 or pres_state=DACS17 or pres_state=DACS22 or pres_state=DACS23)
then DACcs <= '0';
else DACcs <= '1';
end if;
-- DACloaddacs
if(pres_state=DACSstart01 or pres_state=DACSstart02 or pres_state=DACS01 or
pres_state=DACS02 or pres_state=DACS03 or pres_state=DACSend)
then DACloaddacs <= '1';
else DACloaddacs <= '0';
end if;
116
-- DACSdb
if(pres_state=DACS03 or pres_state=DACS04 or pres_state=DACS05 or pres_state=DACS06 or
pres_state=DACS07)
then DACdb <= DACdbA;
elsif(pres_state=DACS08 or pres_state=DACS09 or pres_state=DACS10 or pres_state=DACS11
or pres_state=DACS12 or pres_state=DACS13)
then DACdb <= DACdbB;
elsif(pres_state=DACS14 or pres_state=DACS15 or pres_state=DACS16 or pres_state=DACS17
or pres_state=DACS18 or pres_state=DACS19)
then DACdb <= DACdbC;
elsif(pres_state=DACS20 or pres_state=DACS21 or pres_state=DACS22 or pres_state=DACS23
or pres_state=DACS24 or pres_state=DACS25)
then DACdb <= DACdbD;
else DACdb <= "0000000000000000";
end if;
-- DACchannelA1
if(pres_state=DACS14 or pres_state=DACS15 or pres_state=DACS16 or pres_state=DACS17 or
pres_state=DACS18 or pres_state=DACS19 or pres_state=DACS20 or pres_state=DACS21 or
pres_state=DACS22 or pres_state=DACS23 or pres_state=DACS24 or pres_state=DACS25)
then DACchannelA1 <= '1';
else DACchannelA1 <= '0';
end if;
-- DACchannelA0
if(pres_state=DACSstart01 or pres_state=DACSstart02 or pres_state=DACS01 or
pres_state=DACS02 or pres_state=DACS03 or pres_state=DACS04 or pres_state=DACS05
or pres_state=DACS06 or pres_state=DACS07 or pres_state=DACS14 or pres_state=DACS15 or
pres_state=DACS16 or pres_state=DACS17 or pres_state=DACS18 or pres_state=DACS19)
then DACchannelA0 <= '0';
else DACchannelA0 <= '1';
end if;
end if;
end process;
end behavior;
117
ADCCONTROL.vhd
-- Takes in a rising-edge 'readfromADC' signal, along with the corresponding channel selectors 'ADCchA1'
-- and 'ADCchA0'. Reads the 16-bit value from the ADC using its protocol. It then latches the parallel data
-- on the 'ADCretrieved' bus and pulses the 'ADCdone' signal.
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity adccontrol is port(
fastclk
: in std_logic;
readfromADC,ADCchA1,ADCchA0
: in std_logic;
ADCretrieved
: out std_logic_vector(15 downto 0);
ADCdone
: out std_logic;
ADCbusy
: in std_logic;
ADCdb
: in std_logic_vector(15 downto 0);
ADCchannelA1,ADCchannelA0
: out std_logic
ADCconv,ADCrd,ADCcs
: out std_logic );
end adccontrol;
Architecture behavior of adccontrol is
subtype state_type is STD_LOGIC_VECTOR(3 downto 0);
constant ADCSstart01
: state_type:="0000";
constant ADCSstart02
: state_type:="0001";
constant ADCS01
: state_type:="0011";
constant ADCS02
: state_type:="0010";
constant ADCS03
: state_type:="0110";
constant ADCS04
: state_type:="0111";
constant ADCS05
: state_type:="0101";
constant ADCS06
: state_type:="0100";
constant ADCS07
: state_type:="1100";
constant ADCS08
: state_type:="1101";
constant ADCS09
: state_type:="1111";
constant ADCS10
: state_type:="1110";
118
constant ADCS11
: state_type:="1010";
constant ADCS12
: state_type:="1011";
constant ADCS13
: state_type:="1001";
constant ADCS14
: state_type:="1000";
signal pres_state, next_state : state_type;
signal DB
: std_logic_vector(15 downto 0);
signal temp
: std_logic;
begin
process(pres_state)
begin
case pres_state is
when ADCSstart01 => next_state <= ADCSstart02;
temp <= '0';
when ADCSstart02 =>
if(readfromADC = '1') then next_state <= ADCS01;
else next_state <= ADCSstart02;
end if;
when ADCS01 => next_state <= ADCS02;
ADCchannelA1 <= ADCchA1;
ADCchannelA0 <= ADCchA0;
when ADCS02 => next_state <= ADCS03;
when ADCS03 => next_state <= ADCS04;
when ADCS04 => next_state <= ADCS05;
when ADCS05 => next_state <= ADCS06;
when ADCS06 =>
if(ADCbusy = '0') then next_state <= ADCS07;
else next_state <= ADCS06;
end if;
when ADCS07 => next_state <= ADCS08;
when ADCS08 => next_state <= ADCS09;
DB <= ADCdb;
when ADCS09 => next_state <= ADCS10;
when ADCS10 =>
119
if(temp = '0') then next_state <= ADCS11;
else next_state <= ADCS12;
end if;
when ADCS11 => next_state <= ADCS03;
temp <= '1';
when ADCS12 => next_state <= ADCS13;
ADCretrieved <= DB;
when ADCS13 => next_state <= ADCS14;
when ADCS14 => next_state <= ADCSstart01;
when others => next_state <= ADCSstart01;
end case;
end process;
process(fastclk)
begin
if(fastclk'event and fastclk = '1' ) then
pres_state <= next_state;
if(pres_state=ADCS13 or pres_state=ADCS14) then ADCdone <= '1';
else ADCdone <= '0';
end if;
if(pres_state=ADCS03) then ADCconv <= '0';
else ADCconv <= '1';
end if;
if(pres_state=ADCS03 or pres_state=ADCS07 or pres_state=ADCS08) then ADCcs <= '0';
else ADCcs <= '1';
end if;
if(pres_state=ADCS07 or pres_state=ADCS08) then ADCrd <= '0';
else ADCrd <= '1';
end if;
end if;
end process;
end behavior;
120
SPI.vhd
-- SPI subsystem * communication between FPGA and HC12
-- The SPI subsystem is a bidirectional serial datalink. The serial clock (SCK) is derived from an external
-- source. Eight rising edges on SCK serial shift the data left.. MSB <- LSB. To return data to the HC12,
-- the calling program should load parallel data on the RETURNDATA bus, and then clock the
-- EXTLOAD signal once. The serial shift register will then have the data ready to be sent. The HC12
-- initiates the transfer and receives the swapped data. The 8-bit SPI register in the HC12, along with the 8-- bit SPIdata register seen below, effectively create a 16-bit distributed register, whose contents are
-- swapped after 8 clk cycles. The FPGA is the slave device, and the HC12 is the master (initiates transfers
-- and generates serial clock).
library ieee;
use ieee.std_logic_1164.all;
entity spi is port(
EXTLOAD
: in std_logic; --rising edge triggered parallel data load
RETURNDATA
: in std_logic_vector (7 DOWNTO 0); --Parallel data to go in shift reg
SCK
: in std_logic; --SPI clk (rising edge in middle of data bit)
MOSI
: in std_logic; --SPI data in (MSbit in first)
MISO
: out std_logic; --SPI data out (MSbit out first)
SPIdata
: buffer std_logic_vector (7 DOWNTO 0) ); --Parallel data in shift reg
end spi;
architecture behavior of spi is
begin
process(sck, extload)
begin
if extload = '1' THEN
SPIdata <= RETURNDATA;
elsif (sck'event and sck='1') then
SPIdata(7 downto 1) <= SPIdata(6 downto 0);
SPIdata(0) <= MOSI;
else SPIdata <= SPIdata;
121
end if;
end process;
MISO <= SPIdata(7);
end behavior;
COUNTER.vhd
-- 16-bit free running counter.
-- On rising edge of clock signal, counts up by 1. Every 65,536 clocks, the 16-bit counter is reset. i.e. This
-- should happen every 1.6ms at 40MHz clk. Asynchronous high-true clear signal resets counter to 0x0000.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY counter IS PORT(
clk
: in STD_LOGIC;
clrcount
: in STD_LOGIC;
count_output
: buffer STD_LOGIC_VECTOR (15 DOWNTO 0));
END counter;
ARCHITECTURE behavior OF counter IS
BEGIN
PROCESS (clk, clrcount)
BEGIN
if clrcount = '1' then
count_output <= "0000000000000000";
elsif (clk'EVENT AND clk = '1') THEN
count_output <= count_output + 1;
else
count_output <= count_output;
end if;
END PROCESS;
END behavior;
122
TRIGGERGATE.vhd
library ieee;
use ieee.std_logic_1164.all;
entity triggergate is port(
fastclk
: in std_logic;
triggerin
: in std_logic;
triggerout
: out std_logic );
end triggergate;
architecture behavior of triggergate is
signal shiftreg
: std_logic_vector(3 downto 0);
begin
process(fastclk)
begin
if (fastclk'event and fastclk='1') then
shiftreg(3 downto 1) <= shiftreg(2 downto 0);
shiftreg(0) <= triggerin;
else shiftreg <= shiftreg;
end if;
end process;
triggerout <= shiftreg(3) and shiftreg(2) and shiftreg(1) and shiftreg(0);
end behavior;
NOTTRIBUS.vhd
-- 14-bit NOT/tristate gate for Frequency Synthesizer Card Rev. A
-- This unit takes in a 'high-true' data bus of 14-bits. A '1' at the input yields a 'tri-state' or 'High-Z' output.
-- This increases the frequency out of the "Freq Synth" card. A '0' at the input yields a '0' at the output.
-- This is done b/c there are external pull-up resistors on this data-bus.
123
library ieee;
use ieee. std_logic_1164.all;
entity nottribus is port(
freq
: in std_logic_vector(13 downto 0);
f8192K, f4096K, f2048K, f1024K
: out std_logic;
f512K, f256K, f128K
: out std_logic;
f64K, f32K, f16K, f8K, f4K, f2K, f1K
: out std_logic );
end nottribus;
architecture behavior of nottribus is
begin
with freq(13) select f8192K <= 'Z' when '1', '0' when others;
with freq(12) select f4096K <= 'Z' when '1', '0' when others;
with freq(11) select f2048K <= 'Z' when '1', '0' when others;
with freq(10) select f1024K <= 'Z' when '1', '0' when others;
with freq(9) select f512K <= 'Z' when '1', '0' when others;
with freq(8) select f256K <= 'Z' when '1', '0' when others;
with freq(7) select f128K <= 'Z'when '1', '0' when others;
with freq(6) select f64K <= 'Z' when '1', '0' when others;
with freq(5) select f32K <= 'Z' when '1', '0' when others;
with freq(4) select f16K <= 'Z' when '1', '0' when others;
with freq(3) select f8K <= 'Z' when '1', '0' when others;
with freq(2) select f4K <= 'Z' when '1', '0' when others;
with freq(1) select f2K <= 'Z' when '1', '0' when others;
with freq(0) select f1K <= 'Z' when '1', '0' when others;
end behavior;
CLKDIV.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
124
ENTITY clkdiv IS PORT(
clk
: in STD_LOGIC;
divided
: buffer STD_LOGIC_VECTOR (19 DOWNTO 0) );
END clkdiv;
ARCHITECTURE behavior OF clkdiv IS
BEGIN
PROCESS (clk)
BEGIN
if (clk'EVENT AND clk = '1') THEN
divided <= divided + 1;
else
divided <= divided;
end if;
END PROCESS;
END behavior;
MYSR.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY mySR IS PORT(
set
: in STD_LOGIC;
reset
: in STD_LOGIC;
triggered
: buffer STD_LOGIC );
END mySR;
ARCHITECTURE behavior OF mySR IS
BEGIN
PROCESS (set, reset)
BEGIN
if reset = '1' then
125
triggered <= '0';
elsif (set'EVENT and set='1') THEN
triggered <= '1';
else
triggered <= triggered;
end if;
END PROCESS;
END behavior;
FINDEVENTS.gdf
126
TRIGGERGATES.gdf
127
APPENDIX C
FPGA MAIN GRAPHICAL DESIGN FILES
system-gbw@183
system-gbw@79
INPUT
VCC
INPUT
VCC
fastclk
slowclk
INPUT
VCC
INPUT
VCC
INPUT
VCC
system-gbw@12 FPGA-HC12-P4
system-gbw@13 FPGA-HC12-P3
system-gbw@14 FPGA-HC12-P2
OUTPUT
slowclk
GPIO[7..0]
Testdone
OUTPUT
OUTPUT
OUTPUT
system-gbw@78
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
TriggerA
TriggerB
TriggerC
TriggerD
system-gbw@80
system-gbw@182
system-gbw@184
OUTPUT
OUTPUT
VCC
low
DACSDONE
high
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
system-gbw@17
system-gbw@18
system-gbw@24
system-gbw@25
system-gbw@26
system-gbw@27
DACdbA[15..0]
DACdbB[15..0]
DACdbC[15..0]
DACdbD[15..0]
WRITETODACS
OUTPUT
OUTPUT
Testdone
system-gbw@15
ADCchA1
ADCchA0
ReadfromADC
OUTPUT
8192K
4096K
2048K
1024K
512K
256K
128K
64K
32K
16K
8K
4K
2K
1K
system-gbw@36
OUTPUT
system-gbw@28
system-gbw@29
GND
ADCdone
ADCretrieved[15..0]
OUTPUT
OUTPUT
OUTPUT
system-gbw@30
INPUT
VCC
SYNC
OUTPUT
SELECT
OUTPUT
system-gbw@31
OUTPUT
slowclk
slowclk_div[19]
slowclk_div[19..0]
freq[13..0]
OUTPUT
OUTPUT
OUTPUT
system-gbw@7
INPUT
VCC
SS
SPIsend[7..0]
SPIsendLOAD
SPIreceived[7..0]
OUTPUT
OUTPUT
OUTPUT
foundFE[1..0]
resetFE
CLRCOUNT
SPIsendLOAD
SPIsend[7..0]
resetFE
TriggerB
TriggerC
foundFE[1..0]
system-gbw@8
system-gbw@9
SCK
MOSI
OUTPUT
OUTPUT
OUTPUT
MISO
system-gbw@11
SPIreceived[7..0]
INPUT
VCC
INPUT
VCC
system-gbw@37
system-gbw@38
system-gbw@39
system-gbw@40
system-gbw@41
system-gbw@44
system-gbw@45
system-gbw@46
system-gbw@47
system-gbw@53
system-gbw@54
system-gbw@55
system-gbw@56
ADCchA1
ADCchA0
ReadfromADC
ADCdone
ADCretrieved[15..0]
ADCchannelA1
ADCchannelA0
ADCconv
ADCrd
ADCcs
slowclk
ADCbusy
ADCdb[15..0]
WRITETODACS
DACdbA[15..0]
DACdbB[15..0]
DACdbC[15..0]
DACdbD[15..0]
DACSDONE
system-gbw@101
DACchannelA1
DACchannelA0
DACloaddacs
DACcs
DACrst
DACdb[15..0]
slowclk
system-gbw@100
system-gbw@99
system-gbw@97
system-gbw@96
system-gbw@95
system-gbw@94
system-gbw@93
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
system-gbw@173
system-gbw@174
system-gbw@175
system-gbw@176
system-gbw@177
system-gbw@179
system-gbw@187
system-gbw@189
HC12-A15
HC12-A14
HC12-A13
HC12-A12
HC12-A11
HC12-A10
HC12-A9
HC12-A8
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
HC12-A[15..12]
system-gbw@163
HC12-ECLK
system-gbw@160 HC12-RESET
system-gbw@150
HC12-RW
system-gbw@167
HC12-DBE
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
system-gbw@202
UP-OUT1-LE
system-gbw@200
UP-OUT2-LE
system-gbw@199
UP-OUT3-LE
MEM-EEPROM-OECE system-gbw@205
MEM-NOT-ECLK system-gbw@203
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
DACdb15
DACdb14
DACdb13
DACdb12
DACdb11
DACdb10
DACdb9
DACdb8
DACdb7
DACdb6
DACdb5
DACdb4
DACdb3
DACdb2
DACdb1
DACdb0
system-gbw@140
DACrst
DACloaddacs
DACchannelA1
DACchannelA0
DACcs
system-gbw@119
system-gbw@92
system-gbw@90
system-gbw@141
system-gbw@89
system-gbw@142
system-gbw@88
system-gbw@143
system-gbw@87
system-gbw@144
system-gbw@86
system-gbw@147
system-gbw@85
system-gbw@148
system-gbw@83
system-gbw@149
system-gbw@128
system-gbw@102
system-gbw@131
OUTPUT
system-gbw@132
OUTPUT
system-gbw@133
OUTPUT
system-gbw@134
OUTPUT
system-gbw@135
system-gbw@136
OUTPUT
HC12-ECLK
WIRE
OUTPUT
system-gbw@139
system-gbw@120
system-gbw@122
system-gbw@125
system-gbw@126
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
ADCdb15
ADCdb14
ADCdb13
ADCdb12
ADCdb11
ADCdb10
ADCdb9
ADCdb8
ADCdb7
ADCdb6
ADCdb5
ADCdb4
ADCdb3
ADCdb2
ADCdb1
ADCdb0
ADCbusy
ADCchannelA1
ADCchannelA0
ADCconv
ADCrd
ADCcs
ADCclk
INPUT
VCC
system-gbw@103
system-gbw@104
system-gbw@112
system-gbw@113
system-gbw@114
system-gbw@115
System: Gain Bandwidth Product
system-gbw.gdf
Scott Gulas, TTU
Rev. A
Sheet 1 of 1
OUTPUT
system-sror@183
system-sror@79
INPUT
VCC
INPUT
VCC
fastclk
slowclk
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
system-sror@17
OUTPUT
Testdone
system-sror@15
OUTPUT
SELECT
system-sror@31
OUTPUT
8192K
4096K
2048K
1024K
512K
256K
128K
64K
32K
16K
8K
4K
2K
1K
system-sror@36
OUTPUT
fastclk
OUTPUT
GPIO[7..0]
OUTPUT
INPUT
VCC
INPUT
VCC
INPUT
VCC
system-sror@12
FPGA-HC12-P4
system-sror@13 FPGA-HC12-P3
system-sror@14 FPGA-HC12-P2
OUTPUT
system-sror@78
system-sror@182
system-sror@184
low
OUTPUT
fastclk
system-sror@80
VCC
OUTPUT
Testdone
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
TriggerA
TriggerB
TriggerC
TriggerD
high
OUTPUT
DACdbA[15..0]
DACdbB[15..0]
DACdbC[15..0]
DACdbD[15..0]
WRITETODACS
DACSDONE
system-sror@18
system-sror@24
system-sror@25
system-sror@26
system-sror@27
system-sror@28
system-sror@29
GND
ADCchA1
ADCchA0
ReadfromADC
ADCdone
ADCretrieved[15..0]
OUTPUT
OUTPUT
OUTPUT
OUTPUT
system-sror@30
INPUT
VCC
SYNC
OUTPUT
freq[13..0]
OUTPUT
OUTPUT
OUTPUT
system-sror@7
SS
INPUT
VCC
SPIsend[7..0]
SPIsendLOAD
SPIreceived[7..0]
OUTPUT
OUTPUT
OUTPUT
OUTPUT
fastclk
CLRCOUNT
COUNT[15..0]
CLRCOUNT
SPIsendLOAD
SPIsend[7..0]
system-sror@8
system-sror@9
SCK
MOSI
OUTPUT
MISO
system-sror@11
SPIreceived[7..0]
INPUT
VCC
INPUT
VCC
OUTPUT
system-sror@37
system-sror@38
system-sror@39
system-sror@40
system-sror@41
system-sror@44
system-sror@45
system-sror@46
system-sror@47
system-sror@53
system-sror@54
system-sror@55
system-sror@56
ADCchA1
ADCchA0
ReadfromADC
ADCdone
ADCretrieved[15..0]
ADCchannelA1
ADCchannelA0
ADCconv
ADCrd
ADCcs
fastclk
WRITETODACS
DACdbA[15..0]
DACdbB[15..0]
DACdbC[15..0]
DACdbD[15..0]
DACSDONE
ADCbusy
ADCdb[15..0]
DACchannelA1
DACchannelA0
DACloaddacs
DACcs
DACrst
DACdb[15..0]
fastclk
system-sror@101
system-sror@100
system-sror@99
system-sror@97
system-sror@96
system-sror@95
system-sror@94
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
system-sror@173
system-sror@174
system-sror@175
system-sror@176
system-sror@177
system-sror@179
system-sror@187
system-sror@189
HC12-A15
HC12-A14
HC12-A13
HC12-A12
HC12-A11
HC12-A10
HC12-A9
HC12-A8
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
HC12-A[15..12]
system-sror@163
HC12-ECLK
system-sror@160 HC12-RESET
system-sror@150
HC12-RW
system-sror@167
HC12-DBE
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
system-sror@202
UP-OUT1-LE
system-sror@200
UP-OUT2-LE
system-sror@199
UP-OUT3-LE
MEM-EEPROM-OECE system-sror@205
MEM-NOT-ECLK system-sror@203
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
DACdb15
DACdb14
DACdb13
DACdb12
DACdb11
DACdb10
DACdb9
DACdb8
DACdb7
DACdb6
DACdb5
DACdb4
DACdb3
DACdb2
DACdb1
DACdb0
system-sror@140
DACrst
DACloaddacs
DACchannelA1
DACchannelA0
DACcs
system-sror@119
system-sror@93
system-sror@92
system-sror@141
system-sror@90
system-sror@142
system-sror@89
system-sror@143
system-sror@88
system-sror@144
system-sror@87
system-sror@147
system-sror@86
system-sror@148
system-sror@85
system-sror@149
system-sror@83
system-sror@128
system-sror@131
system-sror@102
system-sror@132
OUTPUT
system-sror@133
OUTPUT
system-sror@134
OUTPUT
system-sror@135
OUTPUT
system-sror@136
system-sror@139
OUTPUT
HC12-ECLK
WIRE
OUTPUT
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
ADCdb15
ADCdb14
ADCdb13
ADCdb12
ADCdb11
ADCdb10
ADCdb9
ADCdb8
ADCdb7
ADCdb6
ADCdb5
ADCdb4
ADCdb3
ADCdb2
ADCdb1
ADCdb0
ADCbusy
ADCchannelA1
ADCchannelA0
ADCconv
ADCrd
ADCcs
ADCclk
INPUT
VCC
system-sror@103
system-sror@104
system-sror@112
system-sror@113
system-sror@114
system-sror@115
system-sror@120
system-sror@122
system-sror@125
system-sror@126
System: Slew rate & Overload Recovery Time
system-sror.gdf
Scott Gulas, TTU
Rev. A
Sheet 1 of 1
APPENDIX D
HARDWARE SCHEMATICS
1
2
3
4
5
6
JP5
+5V
GND
-5V
NOTES:
A
JP6
1
2
3
+5V
Voltage inputs
for PCB
R13
150
Header 3
-- place U3, U5, and J3 very close together to minimize the length of the SYNC trace
+5V
-- all 1uF, 0.1uF, and 1nF caps should be non-polarized ceramic capacitors
GND
-5V
R14
150
C01
1uF
GND
C02
1uF
-5V
GND
1
2
GND
+5V
Header 2
DS1
A
D1
1N914
Lamp
DS2
P1
L1
L2
220nH
220nH
C19
56pF
C20
110pF
WAVEOUT R11
50
1
2
FILTERED
COND
GND
BNC-CONN
C21
56pF
D2
1N914
Lamp
GND
50ohm, 50MHz Lowpass Filter
R06
1K
R07
1K
Place decoupling caps as
close to pins 4 & 8 as
-5V
8
+5V
+5V
Place decoupling cap as
close to pin 16 as possible.
C04
0.1uF
C03
0.1uF
Do not allow SYNC,
WAVEOUT, &
FILTERED traces to
cross each other
+5V
6
C05
0.1uF
JP2
Q2
2N3906
7
2
5
GND
U1B
MAX412CSA
WAVEOUT
1
2
GND
GND
GND
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
Header 2
U4
JP1
4
5
6
7
8
9
10
11
12
13
14
15
8.192MHz
4.096MHz
2.048MHz
1.024MHz
512kHz
256kHz
128kHz
64kHz
32kHz
16kHz
8kHz
4kHz
2kHz
1kHz
2
4
6
8
10
12
14
16
18
20
22
24
26
28
GND
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
3
16
VDD
U1A
+5V
2
3
17
VREF
1
2
IOUT 1
IOUT 2
-5V
1
1
SYNC
R09
R08
3.33k
2.7M
2uA to
750uA
-5V
JP4
+5V
SELECT
GND
C06
2
27
Cap Var
35pF
26
Header 3
Place 1nF decoupling cap as
close to pin 16 as possible.
GND
PDV
PDR
FIN
+5V
GND
R03
7
6
5
21
28
10
4
33K
Place decoupling cap as
close to pin 1 as possible.
0.1uF
R02
9
8
R01
1
SYNC
3.3M
R05
10K
5
2
R04
6
3.3M
3
7.5K
1
R12
33K
+/-2.5V
Surround pin 5 (COSC), 8
(FADJ), and 10 (IIN) with
ground to minimize stray
capacitances.
U2
MAX427CSA
-5V
VSS
C14
Cap Var
14
35pF
5
1
7
GND
8
10
C13
0.1uF
+2.5V
8
2
GND
C09
0.1uF
+5V
GND
GND
2
6
9
11
18
15
U3
SYNC
COSC
REF
DADJ
FADJ
IN
V+
DV+
A0
A1
OUT
GND
GND
GND
GND
GND
DGND
PDI
PDO
V-
C17
1nF
17
+5V
16
3
4
+5V
GND
Place decoupling cap as
close to pin 3 as possible.
C08
0.1uF
C
R10
+5V
GND
SELECT
WAVEOUT
19
13
GND
12
GND
20
-5V
+5V
-5V
MAX038CWP
-5V
C11
0.1uF
C18
0.1uF
100
MC145151-2
GND
GND
GND
+5V
C07
20pF
D
C10
7
R2
R1
R0
T/R
LD
FV
PDout
3
1
Y1
8.192MHz
VDD
OSCin
OSCout
1 = sine
0 = square
MX7541KCWN
4
C
1
2
3
GND
U5
N13
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
0V to 5V square
wave output
Header 2
SYNC
23
22
25
24
20
19
18
17
16
15
14
13
12
11
1
2
GND
MAX412CSA
18
RFB
JP3
Q1
2N3904
GND
GND
Header 14X2
8.192MHz
4.096MHz
2.048MHz
1.024MHz
512kHz
256kHz
128kHz
64kHz
32kHz
16kHz
8kHz
4kHz
2kHz
1kHz
B
4
B
2Vpp output
sine or square wave
C12
0.1uF
Place decoupling caps as
close to pins 17 & 20 as
C15
0.1uF
GND
C16
0.1uF
GND
GND
Place decoupling caps as
close to pins 4 & 7 as
D
GND
Title
Frequency Synthesizer Board
Size
Number
Revision
A
B
Date:
File:
1
2
3
4
5
4/4/2005
Sheet 1of 1
C:\Documents and Settings\..\FreqSynth.SchDoc
Drawn By: Scott Gulas, TTU
6
1
2
3
4
5
6
7
8
U07
+5V
GND
Scope GND
N01
N05
1
2
1
2
3
4
5
+15V
-15V
GND
POWER
+EXTSUP
-EXTSUP
A
+5V
+15V
C01
20V Cap
22uF
GND
-15V
C02
20V Cap
22uF
GND
+EXTSUP
-EXTSUP
C04
20V Cap
22uF
C03
20V Cap
22uF
GND
GND
C05
20V Cap
22uF
GND
R64
U16
REF1004I2.5
POWER
JP02
R23
24.9K
100uA bias
+2.5Vref
1K
C06
220uF
6.3V Cap
6, 8
1
2
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
+5V
DACrst
18
DACloaddacs 19
20
GND
DACchanselA1 21
DACchanselA0 22
23
DACcs#
24
GND
+5V
JP01
GND
GND
DACdb15
DACdb14
DACdb13
DACdb12
DACdb11
DACdb10
DACdb9
DACdb8
DACdb7
DACdb6
DACdb5
DACdb4
DACdb3
DACdb2
DACdb1
DACdb0
1
2
1, 2, 3 GND
NC
NC
GND
C08
0.1uF
GND
5, 7
4
Scope GND
C07
0.1uF
JP03
GND
GND
GND
1
2
+5V
+15V
R17
200
Scope GND
DS01
GND
JP04
GND
GND
R20
750
DS02
-5V
Scope GND
GND
Lamp
R18
200
1
2
+EXTSUP
R19
750
-15V
Lamp
R21
750
DS03
Lamp
GND
R22
750
DS04
Lamp
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
RSTSEL
RST
LOADDACS
R/~W
A1
A0
~CS
DGND
DS05
NC
NC
NC
NC
sense VoutA
VoutA
sense VrefL AB
VrefL AB
VrefH AB
sense VrefH AB
sense VoutB
VoutB
sense VoutC
VoutC
sense VrefH CD
VrefH CD
VrefL CD
sense VrefL CD
sense VoutD
VoutD
VSS
AGND
VCC
VDD
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
-5V -5V
DacOutA
C09
0.1uF
-2.5Vref
+2.5Vref
A
DacOutC
+5V +5V
+2.5Vref
-2.5Vref
C11
0.1uF
DAC7644
GNDGND
C17
0.1uF
DS06
10K
Lamp
+2.5Vref R16
10K
GND
+5V
+15V
WAVEIN
RelayDrive01 3
GND
GNDGND
2
C41
0.1uF
+5V
GND
SPST Coto 9001-05-00
C42
0.1uF
C24
0.1uF
GND
C25
0.1uF
1
GND
2Vpp input
sine or square wave
GND
K19
4
RelayDrive19 3
Input
R06
R08
PLUG
100
2
+5V
NullOutA
10
NullOutB
8
K15
GND
9
SPST Coto 9001-05-00
R09
100K
RelayDrive15 12
B
1
K02
4
RelayDrive02 3
1
+5V
R07
GND
5
4
1
3
6
7
+V
IN+
IN-
FBK
OUT
REF
NC
NC
NC
-V
NC
NC
NC
NC
13
12
11
10
+15V
1
R10
GND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
AIN3
AIN2
AIN1
AIN0
COMMON
NC
REFGND
REFIN
NC
+AVDD
AGND
-AVDD
AGND
NC
NC
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
BGND
DacOutD
TP06
TP05
TP04
GND
GNDGND
GND
+2.5Vref C13
0.1uF
C14
4.7uF
+5V
GND
-5V
GND
ADCdb15
ADCdb14
ADCdb13
ADCdb12
ADCdb11
ADCdb10
ADCdb9
ADCdb8
C15
0.1uF
C16
4.7uF
GNDGND
GND
ADS8342
GNDGND
2
-15V
6
1K
3
GND
8
9
14
16
R26
200
5
+15V
+15V
1
-15V
-15V
TP02
10
TP03
8
C39
0.1uF
+5V
3
B
R66
6
1
GND
+5V
TP04
0
2, 5, 8
C40
0.1uF
RelayDrive1612
GND
U33
BUF634U
K16
9
SPST Coto 9001-05-00
NC
NC
CLKDIV0
CLKDIV1
A0
A1
BYTE
~CONV
~RD
~CS
CLK
+DVDD
DGND
-DVDD
BUSY
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
BVDD
U05
8 OPA228
INA111AU
NAis SPDT TXS2-4.5V
PLUG
2
-15V
RG1
RG2
C22
4.7uF
C21
0.1uF
+15V
U04
2
15
+5V
R14
20K
GND
-15V
GND
1
2
GND
-15V
PLUG
C23
0.1uF
5
C26
1uF
1
GND
JP06
C20
4.7uF
C19
0.1uF
+15V
3
-15V
10
C92
K01
4
7
-5V
-2.5Vref
+15V
4
µA79M05CKTP
3
OUT
GND
1
6
7
IN
C27
1uF
U06
8 OPA277
4
U03
4
-15V
10
R25
-5V
2
C18
4.7uF
R24
4
Voltage outputs to freq
synth daughter board
7
1
1
2
3
1
2
3
4
ADCchanselA1 5
ADCchanselA0 6
7
GND
8
ADCconv
9
ADCrd
10
ADCcs
ADCclk
11
12
13
GND
14
15
ADCbusy
16
ADCdb0
17
ADCdb1
18
ADCdb2
19
ADCdb3
ADCdb4
20
21
ADCdb5
22
ADCdb6
ADCdb7
23
24
GND
R15
-EXTSUP
U08
GNDGND
Lamp
JP05
Output
C12
1uF
DacOutD
-5V
GND
+5V
+5V
+15V
+5V
GND
-5V
C10
1uF
GNDGND
DacOutB
-15V
+15V
-15V
-15V
C45
0.1uF
NAis SPDT TXS2-4.5V
R27
OutTerm
-15V
-15V
GND
+15V
-15V
GND
GND
GND
-15V
+15V
1
2
3
4
5
6
7
8
9
10
GND
VrefPGA
-VinPGA
VoutPreAmp
-VinPreAmp
+VinPreAmp
Vcc-PreAmp
Vcc+PreAmp
NC
NC
20 PGAG0
19 PGAG1
18 PGAG2
17
GND
16
15
-15V
14
-15V
13
+15V
12
+15V
11
G0
G1
G2
SHDN
VoutPGA
VLNegClamp
Vcc-PGA
Vcc+PGA
VhPosClamp
NC
TP08
10
K17
2
+5V
V-
SPST Coto 9001-05-00
8
GND
RelayDrive17
12
1
+5V
1
K07
4
C38
0.1uF
PosTerm
RelayDrive07 3
2
THS7001
+5V
GND
NegTerm
PosTerm
V-
NAis SPDT TXS2-4.5V
+15V
C29
0.1uF
GND
C30
0.1uF
GND
C95
1uF
GND
-15V
+15V
-15V
C31
0.1uF
GND
C32
0.1uF
GND
C43
1uF
GND
C44
1uF
GND
1
K08
4
OutTerm
NegTerm
PosTerm
V-
C36
0.1uF
RelayDrive08 3
2
SPST Coto 9001-05-00
A1
A2
A3
A4
V-
SPST Coto 9001-05-00
C96
1uF
GND
R11
PLUG
V+
R12
PLUG
+5V
B1
B2
B3
B4
NullOutA C1
C2
C3
GND
VC4
GND
V-
Single Dual
Dual Single
Off
-In
+In
V-
OutA
-InA
+InA
V-
V+
OutB
-InB
+InB
Off
V+
Out
NC
Off
-In
+In
V-
OutA
-InA
+InA
V-
V+
OutB
-InB
+InB
Off
V+
Out
NC
Off
-In
+In
V-
OutA
-InA
+InA
V-
V+
OutB
-InB
+InB
Off
V+
Out
NC
1
9
8
R29
84.5K
R13
PLUG
R28
34.8K
C33
0.1uF
A8
A7
A6
A5
GND
GND
GND
GNDGND
V+
OutTerm
C94
1uF
GND
K14
NAis SPDT TXS2-4.5V
DUT
*DUT* Single or dual OPA
9 TP01
TP07
4
1
PLUG
RelayDrive06 3
GND
R30
+15V
R31
3.3K 5
6
3.32K
ADJA1
GND
2
TP04
DacOutA 3
NOPOP
ADJA2
GND
NOPOP
-15V
4
U09
BAL
BAL/STB
+15V
8
+V
+15V
2
TP04
DacOutC 3
ADJC2
GND
-15V
R34
3.3K 5
6
3.32K
NOPOP
+5V
+15V
-V
R33
ADJC1
GND
TriggerA R32
1K
GND
7
1
IN+ COL OUT
IN- EMIT OUT
NOPOP
-15V
4
LM211
B8
B7
B6
B5
V+
NullOutB
C8
C7
C6
C5
V+
OutTerm
NegTerm
PosTerm
+5V
C35
0.1uF
GND
GND
V+
DUT/PdipSocket
C34
0.1uF
C37
0.1uF
C90
100pF
C
GND
+5V
C91
PLUG
GND
R36
+15V
R37
3.3K 5
6
3.32K
ADJB1
GND
TP04
2
DacOutB 3
NOPOP
ADJB2
GND
NOPOP
-15V
4
BAL
BAL/STB
+V
IN+ COL OUT
IN- EMIT OUT
8
7
1
+15V
TriggerC R35
1K
GND
+5V
+15V
-V
C48
0.1uF
-15V
C51
0.1uF
GND
U11
BAL
BAL/STB
+15V
8
+V
+15V
IN+ COL OUT
IN- EMIT OUT
+5V
+15V
-V
NOPOP
ADJD2
GND
-15V
C52
0.1uF
GND
R39
R40
3.3K 5
6
3.32K
ADJD1
GND
TriggerB R38
1K
GND
7
1
TP01
2
DacOutD 3
NOPOP
-15V
LM211
4
GND
U12
BAL
BAL/STB
+V
IN+ COL OUT
IN- EMIT OUT
8
7
1
+15V
TriggerD R41
1K
GND
+5V
+15V
-V
-15V
LM211
C49
0.1uF
GND
GND
U10
LM211
C47
0.1uF
V+
2
R04
NOPOP
4
GND
+15V
TP07
10
GND
+5V
K12
SPST Coto 9001-05-00
2, 5, 8
C28
56pF
R03
4
6
1
3
SPST Coto 9001-05-00
R05
RelayDr ive12 3
220nH
SPST Coto 9001-05-00
K06
4
2
L01
90.9
1
RelayDr ive10 3
R01
GND
U02
4
WAVEIN
U01
BUF634U
1
7
+15V
1
RelayDr ive09 3
SPST Coto 9001-05-00
R02
200
PLUG
+5V
GND
C93
1uF
12
-15V
+5V
10
+5V
2
2
K13
SPST Coto 9001-05-00
RelayDrive03 3
+5V
2
2
4
RelayDrive04 3
1
+5V
2
2
K09
SPST Coto 9001-05-00
+5V
RelayDrive05 3
GND
RelayDr ive14
K03
4
4
1
1
NegTerm
RelayDr ive13 3
K04
4
K11
SPST Coto 9001-05-00
1
RelayDr ive11 3
K05
4
K10
SPST Coto 9001-05-00
1
C46
0.1uF
C50
0.1uF
C53
0.1uF
C54
0.1uF
C
GND
GND
GND
GND
GND
K21
3
5
RelayDrive21 12
A-NC
A-NO
A
B-NC
B-NO
B
9
U13
4
1
+5V
10
8
TXS2-4.5 (Dual config)
3
5
K23
TEST POINTS:
GND
-EXTSUP
TP01 - INPUT TO DUT
TP02 - OUTPUT FROM CHANNEL SEPARATION TEST
TP03 - OUTPUT OF DUT
TP04 - OUTPUT OF BUFFER AFTER DUT
TP05 - OUTPUT OF POSITIVE PEAK DETECTOR
TP06 - OUTPUT OF NEGATIVE PEAK DETECTOR
TP07 - OUTPUT OF INPUT BUFFER
TP08 - OUTPUT OF PGA
-5V
-15V
10
8
3
5
RelayDrive23 12
5
6
K22
-COIL +COIL
A-NC
A-NO
A
B-NC
B-NO
B
RelayDrive22 12
9
A-NC
A-NO
A
B-NC
B-NO
B
9
V+
4
V-
TP04
-COIL +COIL
2
3
R42
2K
-15V
1
+15V
+5V
4
BAL
BAL/STB
-15V
+V
IN+ COL OUT
IN- EMIT OUT
7
1
+15V
10
R44
1M
K18
-COIL +COIL
1
C55
0.1uF
GND
+5V
C56
0.1uF
U15A
OPA2132U
2
9
1
A
3
TP05
+15V
1
TXS2-4.5 (Dual config)
4
+15V
+15V
R43
8
10
GND
RelayDrive18 12
-V
LM211
-15V
8
8
+5V
+15V
10
8
C59
10uF
16V Cap
+5V
GND
-15V
4
GND
+EXTSUP
C61
0.1uF
-15V
GND
NAis SPDT TXS2-4.5V
C62
0.1uF
GND
GND
+15V
TXS2-4.5 (Dual config)
+15V
POWER SUPPLIES:
+15V
R45
2K
-15V
2
3
-15V
4
IN+ COL OUT
IN- EMIT OUT
-V
LM211
MUST BE SUPPLIED: +5V +15V -15V
OPTIONAL: +EXTSUP -EXTSUP
GENERATED ONBOARD: -5V +2.5V(ref) -2.5V(ref)
C57
0.1uF
GND
C58
0.1uF
+V
8
7
1
+15V
10
-15V
GND
R46
10
R47
1M
K20
9
U15B
OPA2132U
6
5
B
7
TP06
8
RelayDrive20 12
1
C60
10uF
16V Cap
+5V
GND
4
TP04
BAL
BAL/STB
8
U14
5
6
-15V
NAis SPDT TXS2-4.5V
GND
D
D
Title
Test and Measurement Board
Size
Number
Revision
A
D
Date:
File:
1
2
3
4
5
6
7
4/5/2005
Sheet 1 of 2
C:\Documents and Settings\..\Split 1.SchDocDrawn By: Scott Gulas
8
1
2
3
4
5
6
7
8
A
A
N02
SMODN/BKGD
ADDR0/DATA0
HC12-A1
ADDR1/DATA1
HC12-A2
MEM-EEPROM-OECE
27
14
47
15
46
16
45
17
44
18
43
19
42
20
41
PAD6
PAD5
PAD4
14
GND
GND
U22
PAD3
18
16
14
12
9
7
5
3
R52
33.2
TDO
TDI
TCK
TMS
R53
33.2
R54
33.2
R55
HC12-A14
HC12-A13
HC12-A12
HC12-A11
HC12-A10
HC12-A9
HC12-A8
HC12-A7
HC12-A6
HC12-A5
HC12-A4
HC12-A3
HC12-A2
HC12-A1
HC12-A0
3
4
OUT
Vcc5
Vdd
GND
+5V
PA7/ADDR15
PA6/ADDR14
PA5/ADDR13
PA4/ADDR12
PA3/ADDR11
PA2/ADDR10
HC12-A15D7
HC12-A14D6
HC12-A13D5
HC12-A12D4
HC12-A11D3
HC12-A10D2
HC12-A9D1
HC12-A8D0
HC12-A15D7
HC12-A14D6
HC12-A13D5
HC12-A12D4
HC12-A11D3
GND
2
3
4
5
6
7
8
9
10
OE
LE
VCC
D1
D2
D3
D4
D5
D6
D7
D8
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
C80
79
183
FPGA_TDI 153
FPGA_TDO
4
FPGA_TMS 50
FPGA_TCK
1
51
EEPROM
+5V
U24
1
2
3
4
5
6
7
8
GND
GND
9
SN74HCT573ADW
HC12-A10D2
TriggerA
TriggerB
TriggerC
TriggerD
78
80
182
184
DATA0
156
157
158
159
161
162
164
166
U31
+5V
1B
2B
3B
4B
5B
6B
7B
8B
GND
1C
2C
3C
4C
5C
6C
7C
8C
COM
18
17
16
15
14
13
12
11
10
RelayDrive01
RelayDrive02
RelayDrive03
RelayDrive04
RelayDrive05
RelayDrive06
RelayDrive07
RelayDrive08
CLK
CLK
0.1uF
EPC2_TDO
DATA0
EPC2_TCK
DCLK
RP01
19
18
17
16
15
14
13
12
+5V
1
2
3
4
5
6
7
8
9
COM
GND
R1
R2
R3
R4
R5
R6
R7
R8
nSTATUS
CONF_DONE
GND
1
2
3
4
5
6
7
8
9
10
TDO
VCC
DATA
TMS
TCK
VPP
DCLK
NC
VCCSEL
NC
NC
NC
NC
VPPSEL
OE
nINIT_CONF
nCS
nCASC
GND
TDI
20
19
18
17
16
15
14
13
12
11
+5V
EPC2_TMS
C81
0.1uF
GND
nCONFIG
nCEO
nCE
MSEL0
MSEL1
nSTATUS
nCONFIG
DCLK
CONF_DONE
TDI
TDO
TMS
TCK
nTRST
IN
IN
IN
IN
nWS
nRS
nCS
CS
RDYnBUSY
CLKUSR
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
INIT_DONE
DEV_CLRn
DEV_OE
GND
EPC2_TDI
Altera EPC2
9pin RPACK
4.7K
+5V
ULN2803A Relay driver
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
OE
GND
50MHz
GND
Vss
GND
+5V
+5V
+5V
+5V
C87
1uF
C88
1uF
GND
GND
C89
1uF
GND
77
106
109
117
6
137
23
145
35
181
43
76
U30
1
2
+5V
GND
0.1uF
20
GND
GND
C77
U23
1
GND
11
UP-OUT1-LE
C85
0.1uF
GND
+5V
D Connector 25
42
5
110
66
118
34
138
22
146
165
178
194
84
98
1
26
2
23
21
24
25
3
4
5
6
7
8
9
10
+5V
C84
0.1uF
GND
GND
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
+5V
C83
0.1uF
C86
1uF
JP15
+5V
+5V
C82
0.1uF
33.2
PAD0
GND
+5V
GND
PAD1
Vrh
R59
1K
SN74HC244DW
PAD2
Vrl
R57
1K
TCK
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
R58
1K +5V
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
PAD7
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
GND
U32A
EPF10K20RC208-3
3
154
108
107
52
105
155
2
GND
GND
GND
nSTATUS
nCONFIG
DCLK
CONF_DONE
B
206
204
208
207
16
10
+5V +5V +5V
R60 R61 R62
1K 1K 1K
19
180
186
nS TATUS
48
19
18
17
16
15
13
12
11
HC12-A15D7
HC12-A14D6
HC12-A13D5
HC12-A12D4
HC12-A11D3
HC12-A10D2
HC12-A9D1
HC12-A8D0
+5V
CONF_DONE
49
13
GND
10
A1
A2
A3
A4
A5
A6
A7
A8
20
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
12
+5V
26
28
20
C75
0.1uF
GND
2
4
6
8
11
13
15
17
VCC
1
2
50
GND
Vdda
C76
0.1uF
+5V +5V
33.2
OE1
OE2
Enable
11
Vssa
+5V
R51
1
19
nCONFIG
R50
4.99K
VCC
GND
GND
22
6
10
+5V
GND
27
RXX
13
8
11
~WE
TXX
~CE
PS0/RxD
PS1/TxD
PS2
14
7
N03
1
6
2
7
3
8
4
9
5
61
62
63
SDO/MOSI
SCK
SDI/MISO
PS3
64
PS4
65
PS5
PS6
66
68
67
~CS/~SS
Vfp
PDLC5
PDLC4
PDLC6
69
70
71
PDLC3
72
PDLC1
PDLC0
Vssx
Vddx
PDLC2
73
74
75
76
51
21
ADDR2/DATA2
+5V
GND
20
48
91
32
124
59
130
72
152
171
188
201
+5V
HC12-A0
0.1uF
+5V
R56
1K +5V
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
PT7
VEE
2
16
+5V
C63
0.1uF
21
33
49
81
82
123
129
151
185
PT6
52
10
40
PT5
9
39
PT4
GP-I/O
53
38
Vss
PT3
54
8
37
GND
Vdd
7
36
+5V
55
35
PT2
8
7
6
5
4
3
2
1
6
34
JP08
56
33
B
57
5
32
PT1
4
31
PT0
58
30
PP0
59
29
PGAG0
GND
GND
60
28
PP1
R1OUT R1IN
R2OUT R2IN
15
MAX232ACSE
3
27
PP2
PGAG1
GND
2
26
PP3
PGAG2
4.99K
1
25
PP4
FPGA_HC12_P1
24
PP5
FPGA_HC12_P2
GND
VDD
VCC
T1IN T1OUT
T2IN T2OUT
12
9
+5V
+5V GND
77
PP6
80
FPGA_HC12_P3
GND
R49
C1+
C1C2+
C2-
11
10
+15V
SetJumper
4.99K
C71
0.1uF
PS7
FPGA_HC12_P4
C67
1uF
GND
PP7
C66
1uF
GND
R48
78
C65
0.1uF
GND
+5V
79
C64
0.1uF
GND
+5V
23
+5V
22
+5V
1
2
1
3
4
5
~OE
JP09
C72
0.1uF
1
2
3
SetJumper
+5V
0.1uF
U21
JP10
+5V
U29
TDO
GND
TMS
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
C74
TDI
C73
GND
U20
C78
GND
10
GND
GND
9
SN74HCT573ADW
C69
GND
COM
10
1
2
GND
0V to 5V square
wave input
Input
JP17
JP14
EPC2_TDI
TDI
FPGA_TDI
0.1uF
GND
1
2
3
R63
+5V
+5V
SELECT
4.99K
1
2
3
GND
~CS/~SS
SCK
SDO/MOSI
SDI/MISO
FPGA_HC12_P4
FPGA_HC12_P3
FPGA_HC12_P2
FPGA_HC12_P1
1 = sine
0 = square
Output
SetJumper
7
8
9
11
12
13
14
15
JP18
C79
1
GND
UP-OUT3-LE
11
C70
U19
MEM-NOT-ECLK
GND
1
11
2
3
4
5
6
7
8
9
HC12-A15D7
HC12-A14D6
HC12-A13D5
HC12-A12D4
HC12-A11D3
HC12-A10D2
HC12-A9D1
HC12-A8D0
GND
10
OE
LE
D1
D2
D3
D4
D5
D6
D7
D8
HC12-A15D7
HC12-A14D6
HC12-A13D5
HC12-A12D4
HC12-A11D3
HC12-A10D2
HC12-A9D1
HC12-A8D0
0.1uF
VCC
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
20
+5V
19
18
17
16
15
14
13
12
HC12-A15
HC12-A14
HC12-A13
HC12-A12
HC12-A11
HC12-A10
HC12-A9
HC12-A8
GND
2
3
4
5
6
7
8
9
10
OE
LE
D1
D2
D3
D4
D5
D6
D7
D8
VCC
20
RP03
+5V
+5V
U28
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
GND
SN74HCT573ADW
19
18
17
16
15
14
13
12
1
2
3
4
5
6
7
8
GND
9
1B
2B
3B
4B
5B
6B
7B
8B
GND
1C
2C
3C
4C
5C
6C
7C
8C
COM
ULN2803A Relay driver
18
17
16
15
14
13
12
11
10
RelayDrive17
RelayDrive18
RelayDrive19
RelayDrive20
RelayDrive21
RelayDrive22
RelayDrive23
+5V
1
2
3
4
5
6
7
8
9
COM
R1
R2
R3
R4
R5
R6
R7
R8
GP-I/O
JP07
GND
9pin RPACK
4.7K
TEST POINTS:
TP01 - INPUT TO DUT
TP02 - OUTPUT FROM CHANNEL SEPARATION TEST
TP03 - OUTPUT OF DUT
TP04 - OUTPUT OF BUFFER AFTER DUT
TP05 - OUTPUT OF POSITIVE PEAK DETECTOR
TP06 - OUTPUT OF NEGATIVE PEAK DETECTOR
TP07 - OUTPUT OF INPUT BUFFER
TP08 - OUTPUT OF PGA
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
2
4
6
8
10
12
14
16
18
20
22
24
26
28
Output
SYNC
SELECT
8.192MHz
4.096MHz
2.048MHz
1.024MHz
512kHz
256kHz
30
31
36
37
38
39
40
41
128kHz
64kHz
32kHz
16kHz
8kHz
4kHz
2kHz
1kHz
44
45
46
47
53
54
55
56
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ADCdb0
ADCdb1
ADCdb2
ADCdb3
ADCdb4
ADCdb5
ADCdb6
ADCdb7
57
58
60
61
62
63
64
65
SN74HCT573ADW
17
18
24
25
26
27
28
29
8
7
6
5
4
3
2
1
GND
0.1uF
U27
U32B
EPF10K20RC208-3
SetJumper
C68
1500pF
GND
HC12-R W#
HC12-R ESET#
HC12-ECLK
HC12-DBE#
JP16
SYNC
1
2
3
150
160
163
167
168
169
170
172
JP12
EPC2_TMS
TMS
FPGA_TMS
9pin RPACK
4.7K
+5V
ULN2803A Relay driver
1
2
3
SetJumper
HC12-A15
HC12-A14
HC12-A13
HC12-A12
HC12-A11
HC12-A10
HC12-A9
HC12-A8
R1
R2
R3
R4
R5
R6
R7
R8
173
174
175
176
177
179
187
189
UP-OUT3-LE
UP-OUT2-LE
UP-OUT1-LE
MEM-NOT-ECLK
MEM-EEPROM-OECE
2
3
4
5
6
7
8
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
+5V
4MHz
RelayDrive09
RelayDrive10
RelayDrive11
RelayDrive12
RelayDrive13
RelayDrive14
RelayDrive15
RelayDrive16
196
197
198
199
200
202
203
205
3
4
18
17
16
15
14
13
12
11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
+5V
4
OUT
Vcc5
1C
2C
3C
4C
5C
6C
7C
8C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SRT
OE
GND
1B
2B
3B
4B
5B
6B
7B
8B
140
141
142
143
144
147
148
149
DACdb15
DACdb14
DACdb13
DACdb12
DACdb11
DACdb10
DACdb9
DACdb8
128
131
132
133
134
135
136
139
DACdb7
DACdb6
DACdb5
DACdb4
DACdb3
DACdb2
DACdb1
DACdb0
116
119
120
121
122
125
126
127
102
103
104
111
112
113
114
115
C
DACrst
DACloaddacs
DACchanselA1
DACchanselA0
DACcs#
ADCbusy
ADCchanselA1
ADCchanselA0
ADCconv
ADCrd
ADCcs
ADCclk
93
ADCdb8
94
ADCdb9
ADCdb10 95
ADCdb11 96
ADCdb12 97
ADCdb13 99
ADCdb14 100
ADCdb15 101
N04
SW-PB
VCC
1
2
1
2
3
4
5
6
7
8
COM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
~RESET
GND
~MR
MAX6412
+5V
GND
19
18
17
16
15
14
13
12
1
83
85
86
87
88
89
90
92
GND
C
5
+5V
U26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
2
3
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
JP13
EPC2_TCK
TCK
FPGA_TCK
RP02
+5V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
U17
HC12-RESET#
D1
D2
D3
D4
D5
D6
D7
D8
20
67
68
69
70
71
73
74
75
U18
2
3
4
5
6
7
8
9
VCC
190
191
192
193
195
HC12-A15D7
HC12-A14D6
HC12-A13D5
HC12-A12D4
HC12-A11D3
HC12-A10D2
HC12-A9D1
HC12-A8D0
OE
LE
I/O
I/O
I/O
I/O
I/O
HC12-A9D1
HC12-A8D0
HC12-R W#
1
GND
UP-OUT2-LE
11
GND
100K
0.1uF
U25
+5V +5V
1
2
3
SetJumper
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ADDR9/PA1
!XIRQ/PE0
ADDR8/PA0
!IRQ/PE1
!R/W / PE2
XTAL
!LSTRB/PE3
EXTAL
!RESET
Vddx
Vssx
ECLK/PE4
GND +5V
HC12-R ESET#
GND +5V
HC12-ECLK
MODA/PE5
MODB/PE6
ADDR7/DATA7
ADDR6/DATA6
ADDR5/DATA5
ADDR4/DATA4
!DBE/PE7
HC12-DBE#
HC12-A7
HC12-A6
HC12-A5
R65
HC12-A4
HC12-A3
ADDR3/DATA3
JP11
EPC2_TDO
TDO
FPGA_TDO
POWER SUPPLIES:
MUST BE SUPPLIED: +5V +15V -15V
OPTIONAL: +EXTSUP -EXTSUP
GENERATED ONBOARD: -5V +2.5V(ref) -2.5V(ref)
D
D
Title
Test and Measurement Board
Size
Number
Revision
A
D
Date:
File:
1
2
3
4
5
6
7
4/5/2005
Sheet 2 of 2
C:\Documents and Settings\..\Split 2.SchDocDrawn By: Scott Gulas
8
1
2
3
4
5
6
A
A
JP1
JP2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B
C
RC01
RC02
RC03
RC04
RC05
RC06
RC07
RC08
RC09
RC10
RC11
RC12
RC13
RC14
RC15
RC16
RC17
RC18
RC19
RC20
RC21
RC22
RC23
RC24
RC25
RC26
RC27
RC28
RC29
RC30
Header 30
JP3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
JP4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Header 30
Header 30
RC31
RC32
RC33
RC34
RC35
RC36
RC37
RC38
RC39
RC40
RC41
RC42
RC43
RC44
RC45
RC46
RC47
RC48
RC49
RC50
RC51
RC52
RC53
RC54
RC55
RC56
RC57
RC58
RC59
RC60
JP5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
JP6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Header 30
RC61
RC62
RC63
RC64
RC65
RC66
RC67
RC68
RC69
RC70
RC71
RC72
RC73
RC74
RC75
RC76
RC77
RC78
RC79
RC80
RC81
RC82
RC83
RC84
RC85
RC86
RC87
RC88
RC89
RC90
Header 30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B
C
Header 30
D
D
Title
RC Configuration Card
Size
Number
Revision
A
B
Date:
File:
1
2
3
4
5
4/5/2005
Sheet 1 of 1
C:\Documents and Settings\..\RC.SchDoc Drawn By: Scott Gulas
6
PERMISSION TO COPY
In presenting this thesis in partial fulfillment of the requirements for a master’s
degree at Texas Tech University or Texas Tech University Health Sciences Center, I
agree that the Library and my major department shall make it freely available for
research purposes. Permission to copy this thesis for scholarly purposes may be granted
by the Director of the Library or my major professor. It is understood that any copying
or publication of this thesis for financial gain shall not be allowed without my further
written permission and that any user may be liable for copyright infringement.
Agree (Permission is granted.)
____Scott M. Gulas_______________________________
Student Signature
__May 04, 2005____
Date
Disagree (Permission is not granted.)
_______________________________________________
Student Signature
_________________
Date