B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Features
Applications
Voltage range 7 to 28V (42V peak),
Limited down to 5V for start-stop systems
Sleep mode current 20µA typically
QFN package -40°C ... 150°C junction (170°C peak)
•
General Description
•
•
Microcontroller supply 3.3V or 5V, up to 70mA,
>70mA with external boost transistor
Adjustable watchdog and reset generation
Smart wake-up via BUS interface or KL15
•
•
Dead time generation (dynamical change)
Motor current measurement amplifier
•
•
•
Over current switch-off (dynamical change)
FET short circuit protections (dynamical change)
Configurable voltage monitoring
•
•
•
LIN2.x transceiver, compatible down to LIN1.3
PWM interface, bidirectional with error feedback
End-of-line high-speed flashing via LIN
•
•
•
•
Ordering information
Product
ID
Feature
Packages
E523.01C LIN2.x or PWM interface
QFN44L7, QSOP44,
QFN48L7
E523.11C PWM interface only
see above
E523.02C .01C, 2 half-bridges only see above
E523.12C .11C, 2 half-bridges only
•
•
•
BLDC(EC) motor control , multiple DC motor control
Fuel, Hydraulic, Oil and Water pumps
Cooling fans, HVAC fans, positioning systems
Turbo charger adjustment
The IC is a system base chip for driving BLDC and DC
motors in B6, full bridge or half bridge applications.
The IC ensures a safe, autonomous start-up and wakeup. It is suitable for high temperature applications. An
integrated linear regulator supplies an external microcontroller. The supply output current can be "boosted"
with an external transistor.
For controlling the motor, six power FET gate drivers
with dynamically programmable, very precise dead time
generation are implemented. Versions driving two half
bridges only are available.
Measurement functions for motor current, battery
voltage and temperature are implemented.
The IC has integrated programmable safety functions on
motor over current, battery over and under voltage, over
temperature and short circuits at all six power FETs.
Two product versions with a “state of the art” LIN2.2A or
bidirectional PWM interface are available. The LIN interface supports flash mode to upload a new firmware to
the microcontroller.
see above
Typical Application Circuit
This document contains information on a pre-production product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
Elmos Semiconductor AG
Data Sheet QM-No.: 25DS0128E.00
B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Functional Diagram
Figure 1: Functional diagram
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Elmos Semiconductor AG
Data Sheet QM-No.: 25DS0128E.00
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Pin Configuration
Figure 2: QFN44L7 pin configuration, transparent top view, not to scale
Figure 3: QFN48L7 pin configuration, transparent top view, not to scale, with >0.6mm distance between VBAT,
VBATS, BUS to ground.
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Elmos Semiconductor AG
Data Sheet QM-No.: 25DS0128E.00
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Figure 4: QSOP44 pin configuration, transparent top view, not to scale
Pin Description
Table 1: Pin description
pin number pin number pin number
QFN44L7 QFN48L7
QSOP44
1
1
6
2
2
7
3
3
8
4
4
9
5
5
10
6
6
11
7
8
9
10
11
12
13
14
15
16
17
7
8
9
10
11
12
13
14
15
16
17
12
13
14
15
16
17
18
19
20
21
22
Name
Type 1)
Description
PWMH3
PWMH2
PWMH1
TXD
RXD
PWML3
D, I
D, I
D, I
D, I
D, O
D, I
PWML2
PWML1
CLK
CSB
SI
SO
SCLK
VSEL
NRES
n. c.
VIN
BUS
D, I
D, I
D, I
D, I
D, I
D, OHiZ
D, I
D, IO
DOd, O
A/D, I
A, IO
High side control signal, half bridge 3 2)
high side control signal, half bridge 2
high side control signal, half bridge 1
Bus interface transmit signal
Bus interface receive signal
Low side control signal, half bridge 3 2), watchdog
trigger
Low side control signal, half bridge 2
Low side control signal, half bridge 1
Microcontroller clock
SPI chip select (low active)
SPI data in
SPI data out
SPI clock
VCC voltage selection, interrupt output
External microcontroller reset
Must not be connected externally
Analogue input voltage, emergency shut-off
Bus interface (LIN or PWM)
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Data Sheet QM-No.: 25DS0128E.00
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
pin number pin number pin number Name
QFN44L7 QFN48L7
QSOP44
18
n. c.
18
19
23
BUSGND
20
n. c.
19
21
24
VBATS
22
n. c.
20
23
25
PGND2
21
24
26
S
22
25
27
D3
23
26
28
GH3
24
27
29
M3
25
28
30
GL3
26
29
31
D2
27
30
32
GH2
28
31
33
M2
29
32
34
GL2
31
34
36
GH1
32
35
37
M1
33
36
38
GL1
34
37
39
T
35
38
40
PGND1
36
39
41
VG
40
n. c.
37
41
42
VBAT
42
n. c.
38
43
43
VDD
39
44 4)
44
VCCP
40
44 4)
1
VCC
41
45
42
46
43
47
44
48
Die paddle Die paddle
2
3
4
5
-
IP
IM
IO
GND
-
Type 1)
S
A, I
S
A, I
S
A, O
A, I
A, O
A, S
A, O
A, I
A, O
A, O
A, I
A, O
D, I
S
S
S
S
A, O
A, I
A, I
A, I
A, O
S
S
Description
Must not be connected externally
Bus interface ground
Must not be connected externally
Motor bridge supply sense
Must not be connected externally
Power ground
KL15 wake-up
High side supply, half bridge 3 2)
High side gate driver output, half bridge 3 2)
Motor phase, half bridge 3 2)
Low side gate driver output, half bridge 3 3)
High side supply, half bridge 2
High side gate driver output, half bridge 2
Motor phase, half bridge 2
Low side gate driver output, half bridge 2
High side gate driver output, half bridge 1
Motor phase, half bridge 1
Low side gate driver output, half bridge 1
Debug and test mode activation
Power ground
Power FET gate driver supply voltage
Must not be connected externally
Main power supply (battery)
Must not be connected externally
Internal 3.3V voltage regulator
VCC regulator driver output
Microcontroller - IC interface voltage and feedback for VCC regulator
Motor current measurement amplifier
Motor current measurement amplifier
Motor current measurement amplifier
Ground
Ground 5)
S = supply, A = analogue, D = digital (push-pull), DOd = digital (open drain), I = input, O = output, OHiZ = output (high impedance default)
To be connected to GND in 523.02 and 523.12 versions
3)
To be left open in 523.02 and 523.12 versions
4)
VCC and VCCP internally connected in QFN48L7 package
5)
To be connected to ground with optimal thermal coupling
1)
2)
Note: GND, BUSGND, PGND1, PGND2 have to be connected externally and with die paddle in shortest way.
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Data Sheet QM-No.: 25DS0128E.00
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Figure 5: Pin clamping illustration
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Data Sheet QM-No.: 25DS0128E.00
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
1 Absolute Maximum Ratings
Stresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. These
are stress ratings only; operation of the device at these or any other conditions beyond those listed in the operational sections of this document is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltage with respect to ground. Currents flowing into terminals are positive,
those drawn out of a terminal are negative.
Table 1.1: Absolute maximum ratings of pin voltages
Description
Condition
VBAT, VBATS, VG, S, GL1-3 voltage
t < 500ms
BUS voltage
t < 500ms
M1-3 phase voltage
Symbol
VVBAT
Min
-0.3
-24
-27
-3V
-0.3V
-3V
VBUS
VM1-3
t < 500ms
VIN voltage
VVIN
|IVIN| < 3mA, series
resistance required
D1-3 voltage
VD1-3
t < 500ms
D1-3 to M1-3 voltage
VD1-3 - VM1-3
t < 500ms
GH1-3 voltage
VGH1-3
t < 500ms
GL1-3 voltage
BUSGND shift to GND
VCCP voltage
VCC voltage
VGL1-3
VBUSGND
VVCCP
VVCCP
1)
TXD, RXD, PWMH1-3, PWML1-3, CLK, IP,
IM, CSB, SCLK, SI, SO, VSEL, NRES, T
voltage
VDD voltage
IO voltage
Load capacity at pin SO
1)
Max
40
42
40
42
VVBATS + 3V
40
42
40
40
Unit
V
V
V
V
V
V
V
V
-0.3
50
52
40
42
VM1-3 - 0.3V VD1-3 + 0.3V
50
52
-0.3V
VVG + 0.3V
-0.3
0.3
-0.3
8
-0.3
5.5
V
V
V
V
V
V
V
V
V
VIO,VCC
-0.3V
VVCC + 0.3V
-
VVDD
-0.3
3.6
V
VIO,VDD
CSO
-0.3V
-
VVDD + 0.3V
1
nF
To be connected on PCB
Table 1.2: Absolute maximum ratings of pin currents
Description
GH1-3, GL1-3 current 1)
Condition
Symbol
IO,DRV
IGL1-3,sum,on
Min
-75
-400
-170
Max
75
400
170
Unit
mA
mA
mA
IGH1-3,GL1-3,sum,off
-340
340
mA
IO,VCC
-5
5
mA
t < 10µs
Current sum of all on-switched GL1-3
Current sum of all off-switched GH1-3 and GL1-3
RXD,SO, RESN, IO current
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Data Sheet QM-No.: 25DS0128E.00
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
1)
Additional limitations due to IC total power dissipation have to be considered
Table 1.3: Thermal absolute maximum ratings
Description
Storage temperature
Ambient temperature
Condition
QFN44L7, QFN48L7
QSOP44
Junction temperature continuous
QFN44L7, QFN48L7
QSOP44
Junction temperature life-time profile for QFN44L7 TJ < 110°C
and QFN48L7 packages 2)
TJ < 130°C
TJ < 150°C
TJ < 160°C
TJ < 170°C
Junction temperature life-time profile for QSOP44 TJ < 110°C
package 2)
TJ < 125°C
IC total power dissipation for QFN44L7 and
QFN48L7 package 3)
IC total power dissipation for QSOP44 package 3)
Symbol
TS
TA
Ptot
Min
-40
-40
-40
-40
-40
1000
+ 3000
+ 6000
+ 1000
+ 120
9000
+ 1000
-
Max
150
150
125
150
125
2.4 4)
Unit
°C
°C
°C
°C
°C
h
h
h
h
h
h
h
W
Ptot
-
0.99 4)
W
TJ
tT,J,QFN
tT,J,QSOP
The maximum junction temperature for special product versions with optional gold-bonding is limited to 150°C.
2)
According to various automotive conform medium- and high-temperature profiles, refer to figure below
3)
For high ambient temperatures Ptot decreases due to the thermal resistance of the IC package.
4)
The maximum IC power dissipation is derived from the thermal resistances of IC and PCB and the temperature difference junction to ambient. The total IC power dissipation is calculated from the sum of:
• VCC regulator power dissipation (VVBAT - VVCC) * IVCC
• VG regulator power dissipation (VVBAT - VVG) * IVG
• FET controller output dissipation at each of the 6 gate outputs (QPFET * fPWM)2 * (10...20)Ω
• internal power dissipation VVBAT * 3mA
1)
Figure 6: Life time parameter illustration
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Data Sheet QM-No.: 25DS0128E.00
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
2 ESD Protection
Description
Condition
Symbol
Min
Max
Unit
ESD HBM Protection at all Pins
1)
VESD(HBM)
-2
2
kV
ESD HBM Protection at pin BUS
1)
VESD(HBM)
-8
8
kV
ESD HBM Protection at pin S, VIN
1)
VESD(HBM)
-4
4
kV
ESD CDM Protection at all Pins
2)
VESD(CDM)
-500
500
V
ESD CDM Protection at Corner Pins
2)
VESD(CDM)C
-750
750
V
According to AEC-Q100-002 (HBM) chip level test
2)
According to AEC-Q100-011 (CDM) chip level test
1)
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Data Sheet QM-No.: 25DS0128E.00
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
3 Recommended Operating Conditions
Parameters are guaranteed within the range of recommended operating conditions unless otherwise specified. Positive currents flow into the device pins. The first electrical potential connected to the IC must be GND.
Table 3.1: Recommended operating conditions
Parameter
Junction temperature
VBAT voltage
VBAT voltage at cold crank (wake-up
functionality limited)
Condition
continuous
Symbol
Min
Typ
Max
Unit
TJ
VVBAT
-40
7 1)
6.7 1)
13
-
150
28
-
°C
V
V
5.3 1)
5 1)
-
-
V
V
7
5
0
0
0
0.8
0
13
-
28
70
0.2
1
1.5
V
V
V
mA
VVCC
VVCC
V
If VCC 5V mode: -IVCC
< 10mA
VCC 3.3V mode only
VCC 3.3V mode only,
-IVCC < 10mA
VBATS voltage
VBATS voltage at cold crank (short circuit
protection limited)
VVBATS
VCC load current
TXD, PWMH1-3, PWML1-3, CLK, CSB,
SCLK, SI, VSEL
-IVCCP
VDI,VCC
L level
H level
IP, IM voltage
VAI
For QFN44L7 and QSOP44 packages only: If a VCC boost transistor is used, the minimal needed VBAT voltage is increased by the individual basis-emitter voltage of the external boost-transistor (VBE,boost,VCC).
2)
Refer to VCC regulator parameter specification, complete functionality not tested in production
1)
Figure 7: VBAT recommended operating condition functional overview (not to scale)
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Data Sheet QM-No.: 25DS0128E.00
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Table 3.2: SPI and CLK input clock recommended operating conditions
Parameter
Condition
Symbol
SPI frequency
fSCLK
Min
-
Typ
-
Max
4
Unit
MHz
SPI data setup time
tspi,ds
62
-
-
ns
SPI data hold time
tspi,dh
62
-
-
ns
SPI clock setup time
tspi,cs
62
-
-
ns
SPI clock hold time
tspi,ch
62
-
-
ns
SPI access gap
CLK input clock frequency
CLK input clock time low
CLK input clock time high
tspi,gap
fCLK
tCLK,L
tCLK,H
3
4
15
15
-
32
-
µs
MHz
ns
ns
1)
Multiple of 4MHz, 5MHz or 6MHz required
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Data Sheet QM-No.: 25DS0128E.00
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
4 Electrical Characteristics
VVBAT = 5V to 28V, for LIN parameters 7V to 18V, TA = -40°C to +150°C (reduced to -40°C to 125°C for QSOP44
packages), unless otherwise noted. Typical values are at VVBAT = 12.0V and TA = +25°C. Positive currents flow into
the device pins.
4.1 Power Supply and Management
Table 4.1: Thermal parameters
Parameter
Thermal resistance junction to case 2)
Thermal resistance junction to ambient
1)
Based on simulation
2)
Not tested in production
2)
Condition
QFN44L7, QFN48L7
QSOP44
Table 4.2: Current consumption parameters
Parameter
Condition
Current consumption in sleep mode
TA < 50°C, VVBAT =
VVBATS = 12V
Current consumption in run mode,
Modulated motor,
power FET gate switching and microcon- fPWM = 25kHz
troller current consumption not included
Min
-
Typ
65
Max
5 1)
-
Unit
K/W
K/W
Symbol
(IVBAT + IVBATS)SLEEP
Min
-
Typ
14
Max
50
Unit
µA
(IVBAT + IVBATS)ACT
-
5
10
mA
Min
1.7
-
Typ
3.4
-
Max
5
6
Unit
V
V
tWU,up
-
5
0.25
50
10
µs
ms
Ipd,S
td,sleep
2
43
10
-
20
-
µA
µs
Symbol
VVCC3
Min
3.2
Typ
3.3
Max
3.4
Unit
V
VVCC5
4.85
5.0
5.15
V
IVCC,lim
-160
-120
-80
mA
Table 4.3: Wake-up and shut-down parameters
Parameter
Condition
S (KL15) threshold voltage
VVBAT > 7V
VBAT wake-up threshold during power-up
(BUS = 'H' or S = 'H')
S (KL15) filter delay
VVBAT > 7V
Over all wake-up delay until controller is Typical buffer capareleased (VG not available)
cities
S pull down current
VS > 1.7
Delay time for entering sleep mode
SLEEPCTRL[1] = 1
Table 4.4: VCC microcontroller supply parameters
Parameter
Condition
VCC regulator output voltage 3.3V mode VVSEL = 'L', VVBAT >
5.3V, -IVCC < 70mA
VVSEL = 'L', VVBAT >
5.0V, -IVCC < 10mA 1)
VCC regulator output voltage 5V mode
VVSEL = 'H', VVBAT > 7V,
-IVCC < 70mA
VVSEL = 'H', VVBAT >
6.7V, -IVCC < 10mA 1)
VCC current limitation
1)
Symbol
Rth,J-C,QFN
Rth,J-A,QSOP44
Symbol
Vth,S
VVBAT,wake,start-up
td,S
Not tested in production
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Data Sheet QM-No.: 25DS0128E.00
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Table 4.5: Reset parameters
Parameter
VCC reset threshold 3.3V mode
VCC reset threshold 5V mode
Condition
Rising
Falling
Hysteresis
Rising
Falling
Hysteresis
Symbol
VVCC3,UV
Table 4.6: Power FET gate voltage supply electrical parameters
Parameter
Condition
VG regulator output voltage
VVBAT >12V , -IVG <
35mA
VG regulator output voltage at low VBAT 5.5V < VVBAT < 12V,
-IVG < 35mA
5V < VVBAT < 5.5V,
-IVG < 35mA
VG current limitation
Table 4.8: Digital pin parameters
Parameter
VSEL, CSB, SCLK, SI, CLK, TXD,
PWMH1-3, PWML1-3 input threshold
CSB, TXD pull-up current
SCLK, SI, CLK, PWMH1-3, PWML1-3
pull-down current
VSEL pull down current
T input threshold
Typ
2.85
2.75
0.1
4.35
4.25
0.1
6
Max
3.0
2.9
4.5
4.4
10
Unit
V
V
V
V
V
V
µs
Symbol
VVG
Min
11
Typ
12
Max
13
Unit
V
VVG,LV
-
13V
-
-
13V
-
IVG,lim
VVBAT 0.6V
VVBAT 0.7V
-110
-80
-35
mA
Symbol
VVDD
fOSC
Min
3.0
0.9
Typ
3.3
1
Max
3.6
1.1
Unit
V
MHz
Min
0.22
0.21
0.01
-
Typ
0.1
-50
50
Max
0.79
0.78
-
Unit
VVCC
VVCC
VVCC
µA
µA
10
0.85
10
0
0.82
-5
0
50
0.79
50
0.18
1
5
µA
VVDD
V
µA
VVCC
VVCC
µA
0.21
-
0.78
VVDD
0.22
-
0.79
VVDD
VVCC5,UV
VCC reset detection time
Table 4.7: Internal supply parameters
Parameter
Internal supply VDD voltage
Internal oscillator
td,VCC,UV
Min
2.7
2.6
0.05
4.15
4.05
0.05
2
Condition
IVDD = 0A
Condition
Rising
Falling
Hysteresis
Symbol
Vth,i
IPU
IPD
IVSEL,pd
Vth,T
Rising
Falling
T pull-down current
SO, VSEL, RXD, NRES output voltage
SO, VSEL, RXD output voltage
SO, NRES output leakage
Io < 1mA, 'L' level
-Io < 1mA, 'H' level
IT,pd
Vo,LOW
Vo,HIGH
Io,leak
VIN input threshold
SECURCTRL[3] = 1
Vth,VIN
VIN input hysteresis
SECURCTRL[3] = 1
Vi,VIN,HYST
0.01
0.1
-
VVDD
VIN pull-down resistance 1)
SECURCTRL[3] = 1
RPD,VIN
-
125k
-
Ω
1)
Not tested in production
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
4.2 Power FET Gate Driver
Table 4.9: Power FET gate driver electrical parameters
Parameter
Condition
On-resistance of high and low side drivers Switched on
Switched off
Current consumption of high side drivers Switched on
Switched off
Switch delay from input control signal to
gate driver output
BRIDGEMODE[6]
=0
Symbol
ron,G 1)
Isup,D1-3
td,DRV
BRIDGEMODE[6]
=1
Emergency shut-off debounce time
1)
2)
SECURCTRL[3] =
1
Max
20
10
300
150
Unit
Ω
Ω
µA
µA
tsyn +
tsyn +
300ns 2) 800ns 2)
-
0
300
800
ns
-
50
-
μs
Symbol
Vth,SC,min
Min
0.345
Typ
0.413
Max
0.486
Unit
V
Vth,SC,max
3
3.3
3.6
V
SCTH[2:0] = 5,
VVBAT > 5V, VVBATS >
5V
1.62
2.48
3.46
V
SCTH[2:0] = 2,
VVBAT > 5V, VVBATS >
3V
SCTH_xS = 1
0.54
0.83
1.15
V
Vth,SC,HRES,min
0
26
52
mV
Vth,SC,HRES,max
3
3.3
3.6
V
td,SC
tMT,SC,max
12.6
3
14
15.4
µs
μs
Symbol
Voffset,in
Min
-3
Typ
0
Max
3
Unit
mV
Ileak,in
ERRA
-3.5
-5
-
0
0
1
3.5
5
-
mV
µA
%
Minimum short circuit threshold in high
resolution mode 1)
Maximum short circuit threshold in high
SCTH_xS = 127
resolution mode 1)
Short circuit detection filter time 2)
Maximum short circuit masking time (10% SCTH[6:4] = 7
accuracy)
2)
tsyn 2)
Typ
8
4
100
50
rGH1-3on, rGH1-3off,M, rGH1-3off, rGL1-3on, rGL1-3off
Synchronizing time: tsyn = (4...5) * TCLK,dead
Table 4.10: Power FET short circuit parameters
Parameter
Condition
Minimum short circuit threshold in low res- SCTH[2:0] = 0
olution mode 1)
Maximum short circuit threshold in low
SCTH[2:0] = 7,
resolution mode 1)
VVBAT > 7V, VVBATS >
7V
1)
tVIN,deb
Min
-
High side and low side FETs
Not tested in production
4.3 Measurement Functions
Table 4.11: Motor current measurement amplifier parameters
Parameter
Condition
Input offset
VIP < 1.5V, TJ <
85°C
VIP < 1.5V
Input leakage current
Current amplification error
A = 100, VIM < 1.5V
This document contains information on a pre-production product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
Elmos Semiconductor AG
Data Sheet QM-No.: 25DS0128E.00
14 / 75
B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Parameter
Output resistance
Condition
|IIO| < 2mA
Table 4.12: Internal analogue signal measurement parameters
Parameter
Condition
VBAT measurement divisor
VG measurement divisor
VIN measurement tolerance
0.3V < VVIN < 2V
GL1-3 measurement tolerance
0.3V < VGL1-3 < 2V
Temperature measurement tolerance 1)
TJ > 125°C
1)
Symbol
rIO
Min
-
Typ
-
Max
100
Unit
Ω
Symbol
RDVBAT
RDVG
VERR,VIN
VERR,GL1-3
Terr,HT
Min
11.5
4.5
-10
-100
-11
Typ
12
5
0
0
0
Max
12.5
5.5
10
100
11
Unit
mV
mV
K
Symbol
VVBAT,OV
Min
29
28
0.5
50
Typ
30
29
1
70
Max
31
30
100
Unit
V
V
V
µs
Min
13
12
0.5
6.0
5.8
0.1
5.0
4.8
0.1
50
Typ
14
13
1
6.4
6.2
0.2
5.4
5.2
0.2
70
Max
15
14
6.8
6.6
5.8
5.6
100
Unit
V
V
V
V
V
V
V
V
V
µs
F31
Min
-20
0
0.45
-3
Typ
0
0
8 / 64
0.5
55 / 64
63 / 64
0
Max
20
0.55
1
3
ta,OC
5
13
20
Unit
mV
VVDD
VVDD
VVDD
VVDD
VVDD
%/
VVDD
μs
Not tested in production
4.4 Monitoring and Safety
Table 4.13: VBAT over voltage parameters
Parameter
Condition
VBAT over voltage threshold
Rising
Falling
Hysteresis
VBAT over voltage detection time
td,VBAT,OV
Table 4.14: VG over and under voltage parameters
Parameter
Condition
VG over voltage threshold
Rising
Falling
Hysteresis
VG under voltage threshold for VVBAT,min > Rising
7V (SAFECTRL[5] = 0)
Falling
Hysteresis
VG under voltage threshold for VVBAT,min > Rising
6V (SAFECTRL[5] = 1)
Falling
Hysteresis
VG over and under voltage detection time
Symbol
VVG,OV
VVG,UV
VVG,UV,6V
td,VG
Table 4.15: Motor over current parameters
Parameter
Condition
Motor over current comparator offset
1V < VIO < 2.7V
Motor over current reference
IOCOMPTHR = 0
IOCOMPTHR = 8
IOCOMPTHR = 32
IOCOMPTHR = 55
IOCOMPTHR = 63
Motor over current accuracy after calibra- 1)
tion by microcontroller with external ADC
Motor over current detection time
1)
Symbol
Voffset,IO
VDAC,OC
Calibration done at IOCOMPTHR = 8 and IOCOMPTHR = 55, measured at IOCOMPTHR = 32
This document contains information on a pre-production product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
Elmos Semiconductor AG
Data Sheet QM-No.: 25DS0128E.00
15 / 75
B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Table 4.16: Over temperature parameters
Parameter
Condition
Over temperature threshold
Rising
Falling
Hysteresis
Over temperature detection time
1)
Symbol
Totemp
td,otemp
Min
170
150
5
50
Typ
15
70
Max
200
100
Unit
o
C
o
C
°C
μs
Min
230
5.4
115
57
28
14
2
200
Typ
256
8
128
64
32
16
4
400
Max
282
8.8
143
73
38
20
10
1000
Unit
ms
ms
ms
ms
ms
ms
μs
µs
Production test is based on calculation
Table 4.17: Watchdog parameters
Parameter
Condition
Register watchdog first open window time
Register watchdog closed window time
WDCTRL[7] = 1
Register watchdog open window time
WDCTRL[5:4] = 3
WDCTRL[5:4] = 2
WDCTRL[5:4] = 1
WDCTRL[5:4] = 0
CLK watchdog detection time
Watchdog reset activation duration
Symbol
WDT,FOW
WDT,CW
WDT,OW
WDT,d,CLK
WDT,RES
4.5 Communication Interfaces
Table 4.18: General BUS interface parameters
Parameter
Condition
Symbol
Min
Typ
Max
Unit
BUS dominant output voltage
VBUS,DOM
-
0.7
1.2
V
BUS receiver dominant level
VBUS,DOM
-
-
0.4
VVBAT
BUS receiver recessive level
VBUS,REC
0.6
-
-
VVBAT
BUS receiver hysteresis
VBUS,HYS
0.02
0.05
0.2
VVBAT
IBUS,LIMIT
20
-
300
mA
RBUS,SLAVE
10
40
100
kΩ
tBUS,WU
tBUS,LOW
70
3
9
150
12
μs
ms
Table 4.19: LIN specific DC parameters (523.01 and 523.02 only)
Parameter
Condition
LIN conform functional range VBAT
Recessive output voltage
TXD = 'H'
Symbol
VLIN,VBAT
VLIN,REC
Typ
-
Max
18
VVBAT
Unit
V
-
Dominant output voltage
VLIN,DOM
Min
7
VVBAT
-1V
-
0.7
1.2
V
VLIN,DOM1
-
1.1
2
V
VLIN,DOM
VLIN,REC
0.6
-
0.4
-
VVBAT
VVBAT
TXD = 'L', VVBAT > 5V,
RLIN = 1.3kΩ 1)
1)
BUS output current limitation
BUS pull-up resistance 1)
BUS wake-up debounce time
BUS dominant clamping time-out
1)
1)
IOCFG[7] = 1
External resistor to VBAT
Not tested in production
Dominant output voltage
TXD = 'L', VVBAT = 7.0V,
RLIN = 500Ω 1)
TXD = 'L', VVBAT = 18V,
RLIN = 500Ω 1)
Receiver dominant level
Receiver recessive level
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Data Sheet QM-No.: 25DS0128E.00
16 / 75
B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Parameter
LIN bus centre voltage
Receiver hysteresis
Output current limitation
Pull-up resistance
Leakage current (driver off)
Leakage current flowing into pin BUS
Pull-up current flowing out of pin BUS
Leakage current, ground disconnected
(GND = VBAT)
Leakage current, supply disconnected
Leakage current, supply disconnected
Clamping voltage
Input capacitance 2)
1)
2)
Condition
VLIN,BUSCNT = (VLIN,THDOM +
VLIN,THREC) / 2
VLIN,THREC - VLIN,THDOM
VLIN > 2.5V
Symbol
VLIN,BUSCNT
Min
0.475
Typ
-
Max
0.525
Unit
VVBAT
VLIN,HYS
ILIN,LIMIT
RLIN,SLAVE
0.03
40
30
0.05
40
VLIN = 12V, VVBAT =
9V ... 12V, TJ < 50°C
transmitter passive, 7V
< VVBAT < 18V, 7V < VLIN
< 18V, VLIN > VVBAT,
TJ < 125°C
transmitter passive, 7V
< VVBAT < 18V, VLIN = 0V
VVBAT = 13.5V, 0V < VLIN
< 18V
VLIN = 12V, VVBAT = 0V,
TJ < 50°C
VVBAT = 0V, 0V < VLIN <
18V
TJ < 125°C
VVBAT = 0V, ILIN = 1mA
7V < VVBAT < 18V
IBUS_PAS_rec50
6
-
VVBAT
mA
kΩ
μA
ILIN,BUSREC
-
0.175
200
60
12
20
μA
ILIN,BUSDOM
-1
-
-
mA
ILIN,NOGND
-1
-
0.1
mA
IBUS,50
-
1
2
μA
ILIN
-
-
20
μA
VLIN,CLAMP
CLIN,PIN
40
-
-
30
V
pF
Min
1
Typ
-
Max
3
Unit
V/μs
0.5
-
3
V/μs
tLIN,SYM
tTXD,PDT
tTXD,SYM
tRXD,PDR
tRXD,SYM
tLIN,DB
DLIN,1
-5
-2
-2
0.3
0.396
-
5
4
2
6
2
6
-
μs
μs
μs
μs
μs
μs
-
DLIN,2
-
-
0.581
-
DLIN,3
0.417
-
-
-
External resistor to VBAT
Not tested in production
Table 4.20: LIN specific AC parameters (523.01 and 523.02 only)
Parameter
Condition
Output slew rate 1)
CLIN = 1nF ... 10nF, RLIN =
500Ω ... 1kΩ, 1μs < tLIN <
5μs, VVBAT = 18V
CLIN = 1-10nF, RLIN = 500Ω ...
1kΩ, 1μs < tLIN < 5μs, VVBAT =
7V
Symmetry of rising and falling edge 1)
VVBAT = 18V
1)
Transmit propagation delay
Transmit propagation delay symmetry 1)
Receiver propagation delay
Receiver propagation delay symmetry
Receiver debounce time
Duty cycle
VLIN,THREC,max = 0.744 * VVBAT,
VLIN,THDOM,max = 0.581 * VVBAT,
VVBAT = 7V ... 18V, tBIT = 50µs,
DLIN,1 = tBUSREC,min / 2 / tBIT
VLIN,THREC,min = 0.422 * VVBAT,
VLIN,THDOM,min = 0.284 * VVBAT,
VVBAT = 7V ... 18V, tBIT = 50µs,
DLIN,2 = tBUSREC,max / 2 / tBIT
V,LIN,THREC,max = 0.778 * VVBAT,
VLIN,THDOM,max = 0.616 * VVBAT,
Symbol
SRLIN,OUT
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Elmos Semiconductor AG
Data Sheet QM-No.: 25DS0128E.00
17 / 75
B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Parameter
1)
Condition
VVBAT = 7V ... 18V, tBIT = 96µs,
DLIN,3 = tBUSREC,min / 2 / tBIT
VLIN,THREC,min = 0.389 * VVBAT,
VLIN,THDOM,min = 0.251 * VVBAT,
VVBAT = 7V ... 18V, tBIT = 96µs,
DLIN,4 = tBUSREC,max / 2 / tBIT
Symbol
Min
Typ
Max
Unit
DLIN,4
-
-
0.590
-
These parameters are a documentation of LIN1.3 specification only and not valid for this product (refer to section LIN Compatibility).
Table 4.21: Firmware upload via LIN (flash mode) parameters (523.01 and 523.02 only)
Parameter
Condition
Symbol
Min
LIN flash mode receive data baud rate 1) VVBAT=13V
BLIN,RXD
1)
LIN flash mode transmit data baud rate
VVBAT=13V
BLIN,TXD
1)
Typ
115
250
Max
-
Unit
kBd
kBd
Not tested in production
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Data Sheet QM-No.: 25DS0128E.00
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
5 Typical Operating Characteristics
30
22
25
20
I(VBAT) + I(VBATS) / µA
(I(VBAT) + I(VBATS)) / µA
Sleep Mode Current vs. VBAT
T = 50°C, V(VBAT) = V(VBATS)
20
15
10
5
18
16
14
12
10
8
0
0
5
10
15
20
25
30
35
-40
40
V(VBAT) / V
-20
0
20
40
60
80
Temp. / °C
V(VG) vs. V(VBAT)
I(VG) = 10mA
14
5.5
12
V(VCC) / V
10
V(VG) / V
Supply Mode Current vs. Temperature
V(VBAT) = 13.5V
8
6
4
2
V(VCC) vs. V(VBAT)
I(VCC) = -20mA
5.0
4.5
4.5
4.0
4.0
3.5
3.5
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0.0
0
0
5
10
15
20
25
30
5.5
5.0
0.0
0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0
35
V(VBAT) / V
V(VBAT) / V
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Data Sheet QM-No.: 25DS0128E.00
19 / 75
B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
V(VCC) vs. V(VBAT)
3,3V mode, I(VCC) = -20mA
3.31
V(VCC) vs. V(VBAT)
5V mode. I(VCC) = -20mA
5.05
5.04
3.30
5.03
5.02
5.01
V(VCC) / V
V(VCC) / V
3.29
3.28
3.27
5.00
4.99
4.98
4.97
3.26
4.96
4.95
3.25
0
5
10
15
20
25
30
35
0
40
10
15
20
25
30
35
40
V(VBAT) / V
V(VBAT) / V
1.60
5
V(VTEMP) vs. Temperature
V(VBAT) = 13.5V
1.50
V(VTEMP) / V
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
-40 -20 0 20 40 60 80 100120140160180
Junction temp. / °C
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Data Sheet QM-No.: 25DS0128E.00
20 / 75
B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
6 Detailed functional description
The IC is a system base chip including:
Section 6.1:
●
Power supply management
●
Microcontroller supply with reset generation
●
Power FET gate driver supply
●
Sleep mode and wake-up functionality
Section 6.2:
●
Initial IC configuration for the customer application
Section 6.3:
●
B6 bridge power FET gate driver
●
Dead time generation
●
Power FET short circuit protection, drain-source monitoring
Section 6.4:
●
Motor current measurement
●
Advanced analogue signal measurement
Section 6.5:
●
Monitoring and protection against failure effects
●
Watchdog
●
Interrupt
Section 6.6:
●
LIN or PWM interface
●
SPI interface
A dedicated functionality at VIN pin can be used to fulfil functional safety requirements.
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Data Sheet QM-No.: 25DS0128E.00
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
6.1 Power Supply and Management
The power supply contains:
●
VCC linear voltage regulator for external microcontroller supply (3.3V or 5V, 70mA)
●
VG linear voltage regulator for power FET switching (12V, 35mA)
●
Power-on reset and microcontroller reset generation
●
Power-up, sleep mode and wake-up sequencing
Figure 8: Power supply block diagram
Table 6.1: Register VREGCTRL (0x07), VCC and VG supply control
MSB
LSB
Content
-
-
-
-
VCC_SON VSEL
VGON
VCCON
Reset value
0
0
0
0
0
0
0
1
Internal access
-
-
-
-
R
R
R
R
External access
R
R
R
R
R/W
R/W
R/W
R/W
Bit Description
VCC_SON: 1: VCC is connected to VDD in sleep mode internally, if VSEL = 'L'
0: VCC is off in sleep mode
VSEL: 1: µC supply VCC is 5V, 0: µC supply VCC is 3.3V
VGON: 1: Enable VG supply
VCCON: 1: Enable VCC supply
6.1.1 VCC Microcontroller Supply
The VCC regulator is a linear NMOS regulator with current limitation. The level at VSEL pin sets the microcontroller
supply voltage to 3.3V or 5V. The voltage selection has to be confirmed by setting VSEL bit in VREGCTRL register
accordingly.
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Data Sheet QM-No.: 25DS0128E.00
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Figure 9: VCC regulator block diagram, case microcontroller supply is 3.3V, VREGCTRL[2] to be set to 0
Figure 10: VCC regulator block diagram, case microcontroller supply is 5V, VREGCTRL[2] to be set to 1
To increase the available output current or to reduce power dissipation within the IC to allow higher ambient temperatures, an external NPN bipolar boost transistor may be inserted.
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Data Sheet QM-No.: 25DS0128E.00
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Figure 11: VCC block diagram, case external VCC boost transistor
Security warning: If using an external boost transistor an external current limitation must be inserted.
Figure 12: Proposal of short circuit protection at microcontroller supply, when using an external boost transistor
Note: The stability of the implemented circuitry has to be ensured by the customer.
In sleep mode, the VCC regulator is switched off. If setting VCC_SON bit in VREGCTRL register, VCC pin is connected to the internal 3.3V supply VDD (VCC in 3.3V mode only). Then the output current is limited to 300µA. An
overload leads to IC and microcontroller reset and restart.
Note: If VCC is enabled in sleep mode, all input pins should have pull resistances externally to avoid increased current consumption.
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Data Sheet QM-No.: 25DS0128E.00
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
6.1.2 Power FET Gate Voltage Supply VG
The VG regulator is used to:
● supply the low side gate drivers
●
charge the bootstrap capacitors via external bootstrap diodes.
The VG regulator is a linear low drop PMOS regulator with current limitation. The output is safe against reverse currents. So in case of battery voltage drops, the regulator output voltage can be higher than battery voltage. The storage capacitor does not discharge against battery.
Figure 13: VG regulator block diagram
The chip internal divided VG voltage can be switched to AOUT by setting AMUX register via SPI.
6.1.3 Internal Supply VDD
A linear 3.3V voltage regulator with current limitation supplies the internal digital and analogue components of the
IC. External loads at VDD pin are not allowed.
6.1.4 Reset
The internal supply VDD and the microcontroller supply VCC are monitored by the IC. After power-up or in case of
low voltage at VCC or VDD, the IC is reset and the signal at NRES pin for the external microcontroller is set to L.
The reset is set to H, if VDD and VCC is powered up successfully.
NRES pin is an open drain output.
Note: The VCC regulator is switched off, when NRES is 'L'.
6.1.5 IC State Control
The IC is clocked by an integrated oscillator with f OSC frequency.
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Figure 14: IC states diagram
Table 6.2: IC states description
POR
(Deep-) Sleep
Power-up
Initial configuration
Run
Internal supply on
on
on
on
on
Oscillator
off
off
on
on
on
VCC supply
off
off
on
on
on 2)
VG supply
off
off
off
off
on 2)
Power FET
gate driver
disabled 1)
disabled 1)
disabled 1)
disabled 1)
enabled 2)
Monitoring
off
off
on
on
on
Measurement off
off
off
off
on
1)
High side and low side power FETs switched off
2)
Depending on configuration
6.1.5.1 Power Up
After applying battery voltage, the IC ensures a save power-up of microcontroller and B6 bridge. All high side and
low side driver outputs are off (clamped to ground or to motor phase) to prevent the external B6 bridge from cross
current.
Sleep mode activation after power-up is level sensitive to S pin. If S pin is low, the IC enters sleep mode. If S pin is
'H', the IC is in active mode.
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Data Sheet QM-No.: 25DS0128E.00
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Figure 15: Power up timing diagram, typical scenario with S = 'H'
Figure 16: Power up timing diagram, typical scenario with S = 'L'
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
6.1.5.2 Shut-down and Sleep Mode
Sleep mode (deep-sleep mode) is entered via SPI command written to SLEEPCTRL register. In sleep mode, all
registers are cleared except the IRQSTAT1 and IRQSTAT2 interrupt status registers. All regulators and monitoring
are off except VDD and power-on reset (POR) generation.
Table 6.3: Register SLEEPCTRL (0x03) 1), sleep mode control
MSB
LSB
Content
-
-
-
-
-
-
DELAYSLE SLEEP
EP
Reset value
0
0
0
0
0
0
0
0
Internal access
-
-
-
-
-
-
R/W
R/W
External access
R
R
R
R
R
R
W
W
Bit Description
DELAYSLEEP: Goto sleep after td,sleep
SLEEP: Enter sleep mode
1)
Bits in register are self-clearing
Figure 17: Shut-down timing diagram
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
6.1.5.3 Wake Up
Wake-up from sleep mode can be done by two independent wake-up sources:
●
BUS pin: A falling edge at BUS pin followed by a dominant bus level maintained for a time period t BUS,WU results in a remote wake up request. If BUSWAKEEDGE bit in CHIPCTRL register is 0, the IC wakes up immediately. Else the IC wakes up at the next rising edge at BUS pin.
●
S pin: A rising edge or high level at S pin wakes up the IC. The sensitivity can be configured by SSENS bit
in CHIPCTRL register.
Figure 18: Wake up via S pin, typical scenario
Warning: Wake-up from sleep mode via S pin with SSENS = 0 requires a rising edge at S pin after writing the SPI
sleep command. In several applications it cannot be ensured under all circumstances. Then wake-up events may
not be recognized and the system remains in sleep mode (dead lock). To avoid this situation, SSENS bit in
CHIPCTRL register has to be set to 1.
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Table 6.4: Register CHIPCTRL (0x02), wake-up configuration
MSB
LSB
Content
-
-
-
-
-
SSENS
BUSWAKEEDGE
BUSWAKEEN
Reset value
0
0
0
0
0
0
1
1
Internal access
-
-
-
-
-
R
R
R
External access
R
R
R
R
R
R/W
R/W
R/W
Bit Description
SSENS: 1: Wake up at S is level sensitive (high level leads to wake up), 0: Wake up at S is
edge sensitive (rising edge)
BUSWAKEEDGE: 1: BUS wake up at rising edge, 0: BUS wake up at falling edge
BUSWAKEEN: BUS wake up enable
Figure 19: Wake-up via BUS pin, typical scenario with BUSWAKEEDGE = 1
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Figure 20: Wake-up via BUS pin, typical scenario with BUSWAKEEDGE = 0
6.1.6 Board Level Protection
VBAT (VBATS), S and GND must be protected against reverse polarity and ISO pulses on PCB level.
Table 6.5: Reverse polarity protection concepts
PCB Terminal
Reverse Polarity
Protection Device
PCB Circuitry
Description
Battery (high side) NMOS transistor
Charge pump
Battery (high side) Diode
Diode
Increases the minimum battery voltage
Ground (low side) NMOS transistor
-
VG regulator output can be used to drive the gate of the
reverse polarity protection transistor.
Note: For LIN applications, a low side reverse polarity protection is not possible due to EMC requirements.
At VBAT (VBATS) filtering is necessary to prevent the IC from malfunction and destruction caused by EME and EMI.
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
6.2 Initial Configuration and Security
Some registers of the IC are only writeable within the initial configuration state (refer to restricted register table).
After power-up or wake-up an initial IC configuration via SPI needs to be done. The initial configuration:
●
starts with the writing of CLKCTRL clock divider register. Before writing CLKCTRL register, any writing of
restricted registers is ignored.
●
ends with setting ESECURE bit in SECURCTRL register. Once ESECURE bit is set, any writing of restricted
registers is ignored.
The ESECURE bit can only be set, if all other bits in SECURCTRL register are left unchanged. So the register has
to be written twice, if special IC features want to be selected.
Example 1: SECURCTRL = 0x01, only 1 SPI access to the register necessary (no special features selected)
Example 2: SECURCTRL = 0x18 (1st SPI access), SECURCTRL = 0x19 (2nd SPI access), analogue signal multiplexing and emergency shut-off selected
Reset conditions of ESECURE bit are:
●
Watchdog event (register watchdog or CLK watchdog)
●
Under voltage at VDD or VCC (at low battery voltage or short circuit)
●
Sleep state
The restriction of the dead time registers (section “Power FET Gate Driver”) and analogue / digital signal multiplexing registers can be released by writing SECURCTRL register accordingly.
Table 6.6: Register SECURCTRL (0x04), security configuration
MSB
LSB
Content
-
-
EDMUX
EACMUX
EMERGENCY
EDEADMULT
EDEADNEG
ESECURE
Reset value
0
0
0
0
0
0
0
0
Internal access
-
-
R
R
R
R
R
R
External access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
EDMUX: Enable write access to DMUX register in run mode
EACMUX: Enable write access to AMUX and CMUX registers in run mode
EMERGENCY: Enable emergency shut-off functionality of power FET gate driver at VIN pin
EDEADMULT: Enable write access to DEADTIME_LH and DEADTIME_HL registers in run
mode
EDEADNEG: Allow negative dead times in DEADTIME_LH and DEADTIME_HL registers
Security warning: Setting this bis is at own risk. The customer has to guarantee that no cross
currents occur at the half bridge. Damage of IC and external components are possible.
ESECURE: 1: Disables write access to all restricted registers (including ESECURE bit itself)
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
If EMERGENCY bit in SECURCTRL register is set, VIN pin is used as digital input to enable / disable the power
FET gate driver. If VIN pin is 'L', the power FET gate driver outputs are switched off.
Figure 21: IC states diagram, case VIN used for emergency shut-off
Note: To reset the IC after finishing the initial configuration, just write a false watchdog trigger command to the IC.
Note: It is recommended to check the configuration every few milliseconds. In case of bit failure detection, the
registers must be rewritten immediately. Therefore it is necessary to force an IC reset (e. g. a false watchdog trig ger), since register writing is blocked by ESECURE bit in SECURCTRL register in run and fail save mode.
Note: During final application, the use of a fuse is recommended to prevent the system from damage caused by
accidental bit changes in the IC or aging of PCB elements, e. g. power FETs.
Warning: During development of IC specific software, there is a higher risk of damaging IC and PCB elements due
to falsely written configuration. A current limited power supply should be used.
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
6.3 Power FET Gate Driver
The power FET gate driver contains 3 independent half bridge gate drivers with short circuit protection. Each half
bridge consists of a high side and a low side driver controlled by PWMH1-3 and PWML1-3 input pins.
The slew rate of the power FETs is adjusted by external gate resistors.
Note: The gate-drain capacitance of the power FET causes a positive gate-source voltage during motor phase transients. Additional PCB elements have to be inserted to prevent the half bridge from cross current:
●
Greater off- resistance than on-resistance of RGATE (2 resistors, 1 diode, refer to typical application diagram,
recommended)
●
Additional gate-source capacitor, increases the VG current consumption and power losses, not possible for
large power FETs
The high side supply voltage is done by bootstrap principle with external capacitors and diodes.
Figure 22: FET controller block diagram in half bridge configuration
Warning: The bootstrap principle and circuitry must be used even if a charge pump is inserted at PCB. It is not
allowed to connect D1-3 pins to any charge pump terminal on PCB.
Note: The bootstrap capacitors need to be recharged every PWM cycle. 100% duty cycle is not allowed. There is
no monitoring the bootstrap under voltage.
Emergency shut-off functionality: If EMERGENCY bit in SECURCTRL register is set and VIN pin is L, the power
FET gate driver outputs are switched off.
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
6.3.1 Control Modes for Half Bridge Applications
PWMH1-3 and PWML1-3 input pins can be used in 3 or 6 PWM input mode.
Table 6.7: PWMH1-3 and PWML1-3 input configuration
Mode
Register
Description
PWMH
input
pin
controls
the
high
side driver, PWML controls the low side
6 PWM input BRIDGEMODE = 0x7F,
driver independently.
GATECFG = 0x12
The dead time has to be generated in the microcontroller.
There is no digital latency of the PWMH / PWML input signals.
3 PWM input BRIDGEMODE = 0x6F, PWMH input pin controls the high side driver and the low side driver
inversely. PWML input pin enables the PWMH driver control. PWML = 'L'
GATECFG = 0x52
switches the motor phase to high-impedance, disregarding the level at
PWMH.
The dead time has to be written in the dead time registers DEADTIME_LH
and DEADTIME_HL.
The PWMH / PWML input signals are delayed (4 to 5 CLK clocks latency
to be considered).
Figure 23: 6 PWM input mode transfer characteristic timing diagram
Figure 24: 3 PWM input mode transfer characteristic timing diagram
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Note: In products E523.02 and E523.12 the power FET gate driver output stages GH3 and GL3 are not available.
6.3.2 Dead Time and CLK Input Clock
In 3 PWM input mode the dead time is generated in the IC. The dead time derives from the CLK input clock frequency and can be adjusted to the customer application.
In 6 PWM input mode there is no need to apply the input clock at CLK pin 1). CLKCTRL, DEADTIME_LH and DEADTIME_HL registers can be set to 0x00 and the next subsections descriptions can be skipped.
1)
Not if PWM duty cycle measurement special function is used.
6.3.2.1 CLK Input Clock
The CLK input clock - applied by the microcontroller - is mainly used for dead time generation. The accuracy of the
dead time is the same as the accuracy for the controller clock (quartz accuracy possible). The CLK input clock has
to be symmetrical.
The frequency of the applied CLK input clock must be written to CLKDIV register. The dead time clock f CLK,dead can
be divided or doubled additionally.
Security warning: The CLKCTRL register must be set very carefully in correlation with the CLK input clock frequency. Incorrectly set values may cause malfunction of the system.
Table 6.8: Register CLKCTRL (0x01), CLK input clock and clock divider configuration
MSB
LSB
Content
F2X
TDEADDIV2
TDEADDIV1
TDEADDIV0
CLKTEST CLKDIV2
CLKDIV1
CLKDIV0
Reset value
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
W
R
R
R
External access
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit Description
F2X: Use double frequency of CLK input clock to halve the dead time step size (only available
when TDEADDIV = 7)
TDEADDIV[2:0]: Dead time clock divider (see table below)
CLKTEST: Toggled on each SPI access to CLKCTRL register, if CLK is applied
CLKDIV[2:0]: CLK input clock frequency (see table below)
Table 6.9: CLK input clock frequency code table
fCLK
CLKDIV[2:0]
fCLKDIV (clock base)
32 MHz
0
4 MHz
30 MHz
2
5 MHz
28 MHz
1
4 MHz
25 MHz
3
5 MHz
24 MHz
2
4 MHz
20 MHz
3
4 MHz
18 MHz
5
6 MHz
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
fCLK
CLKDIV[2:0]
fCLKDIV (clock base)
16 MHz
4
4 MHz
15 MHz
5
5 MHz
12 MHz
5
4 MHz
10 MHz
6
5 MHz
8 MHz
6
4 MHz
6 MHz
7
6 MHz
5 MHz
7
5 MHz
4 MHz
7
4 MHz
Table 6.10: Dead time clock divider table
TDEADDIV[2:0]
Control clock to input clock ratio
7
1:1
6
1:2
5
1:3
4
1:4
3
1:5
2
1:6
1
1:7
0
1:8
6.3.2.2 Dead Time Generation
The dead time between off-switching of the activated and on-switching of the opposite FET is programmable in
DEADTIME_LH and DEADTIME_HL registers.
The dead time clock base is defined in CLKCTRL register:
T CLK ,dead =T CLK⋅8−CLKCTRL[6 : 4]
The dead time value calculation is:
case CLKCTRL[7] = 0:
case CLKCTRL[7] = 1:
t dead =DEADTIME _ xx [5 : 0]⋅T CLK , dead
t dead =0.5⋅DEADTIME _ xx [5: 0 ]⋅T CLK ,dead
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Table 6.11: Register DEADTIME_LH (0x24), low to high transition dead time
MSB
LSB
Content
NEG
PARITY
D5
D4
D3
D2
D1
D0
Reset value
0
0
1
1
1
1
1
1
Internal access
R
R
R
R
R
R
R
R
External access
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
NEG: On-switching before off-switching of the correspondent power FET (negative dead time
with D[5:0] value)
Security warning: Using small or negative dead times is on own risk due to the possibility of
driver damage.
PARITY: Even register parity (write only, read as 0)
D[5:0]: Dead time value.
Table 6.12: Register DEADTIME_HL (0x25), high to low transition dead time
MSB
LSB
Content
NEG
PARITY
D5
D4
D3
D2
D1
D0
Reset value
0
0
1
1
1
1
1
1
Internal access
R
R
R
R
R
R
R
R
External access
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
NEG: On-switching before off-switching of the correspondent power FET (negative dead time
with D[5:0] value)
Security warning: Using small or negative dead times is on own risk due to the possibility of
driver damage.
PARITY: Even register parity (write only, read as 0)
D[5:0]: Dead time value.
Note: Even parity means, the number of all 1 in the register must be even.
Note: The analogue delay of HS and LS driver may be different and has to be compensated by the dead time. It
has to be guaranteed by the software that no cross current occurs in the half bridges.
Example 1:
CLK input frequency fCLK = 4 MHz: CLK input clock frequency CLKDIV has to be set to 7.
Dead time clock divider TDEADDIV set to 7: Dead time resolution is TCLK,dead = 1 / 4MHz = 250ns.
DEADTIME register set to 0x43: tdead = 750ns
Example 2:
CLK input frequency fCLK = 18MHz: CLK input clock frequency CLKDIV has to be set to 5.
Dead time clock divider TDEADDIV set to 6: Dead time resolution is TCLK,dead = 1 / 6MHz * 2 = 333.3ns.
DEADTIME register set to 0x04: tdead = 1.333µs
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
6.3.3 Short Circuit Protection
The drain source voltage of the external low side and high side power FETs in on-state are monitored by the IC. If
the motor phase voltage M exceeds a programmable threshold, the gate driver switches the power FETs off immediately. Reference for the high side FETs is VBATS sense voltage, for the low side FETs ground.
Figure 25: Short circuit protection block diagram
The thresholds of high side and low side power FETs are programmable in SCTH register in low resolution mode. If
higher resolution is needed, registers SCTH_HS and SCTH_LS provide 128 equidistant steps derived from VDD
voltage for both high side and low side independently. If one of these registers is written, SCTH[2:0] will be ignored
for the corresponding side. The calculation of the threshold values is given in the following table.
Note: It is mandatory to write SCTH register, since the short circuit masking time has to be adjusted. SCTH_HS and
SCTH_LS registers have to be written after SCTH register access.
Table 6.13: Short circuit value calculation
Mode
Mean value
Tolerance (+/-)
Low resolution
SCTH [2: 0]
⋅3.3V
8
SCTH [2: 0]
⋅275mV24mV
8
High resolution
SCTH _ xS
⋅3.3V
127
SCTH _ xS
⋅275mV24mV
127
After on-switching of the power FET the error detection is masked for a programmable time. The masking time is
derived from the internal 1MHz oscillator:
t MT , SC =SCTH [6 : 4 ]⋅2µs
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Table 6.14: Register SCTH (0x26), short circuit threshold selection (low resolution mode) and masking time
MSB
LSB
Content
-
MT2
MT1
MT0
-
TH2
TH1
TH0
Reset value
0
0
0
0
0
0
0
0
Internal access
-
R
R
R
-
R
R
R
External access
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit Description
MT[2:0]: Short circuit initial masking time value
TH[2:0]: Short circuit threshold value
Table 6.15: Register SCTH_HS (0x28), high side short circuit threshold selection (high resolution mode)
MSB
LSB
Content
-
D6
D5
D4
D3
D2
D1
D0
Reset value
0
0
0
0
1
1
1
1
Internal access
-
R
R
R
R
R
R
R
External access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
D[6:0]: Short circuit threshold value. On write access TH[2:0] bits of SCTH register are set to
0xF
Table 6.16:Register SCTH_LS (0x29), low side short circuit threshold selection (high resolution mode)
MSB
LSB
Content
-
D6
D5
D4
D3
D2
D1
D0
Reset value
0
0
0
0
1
1
1
1
Internal access
-
R
R
R
R
R
R
R
External access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
D[6:0]: Short circuit threshold value On write access TH[2:0] bits of SCTH register are set to
0xF
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Figure 26: Examples of short circuit detection, timing diagram
6.3.3.1 Superior Short Circuit Failure Reaction
A superior reaction to a short circuit failure can be configured in SCPCTRL register.
Table 6.17: Register SCPCTRL (0x0B), superior short circuit protection control
MSB
LSB
Content
-
-
-
SCALL
-
-
SCFCT1
SCFCT0
Reset value
0
0
0
0
0
0
0
0
Internal access
-
-
-
R
-
-
R
R
External access
R
R
R
R/W
R
R
R/W
R/W
Bit Description
SCALL: 1: Switch off all power FETs on short circuit, 0: Switch off only correspondent FET on
short circuit
SCFCT[1:0]: See following table
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Table 6.18: Superior short circuit protection behaviour
SCFCT[1:0]
Description
Depiction
0
Re-try of power FET switching at every rising edge of the correspondent input control. Interrupt is thrown after first short circuit
failure detection
1
Drivers remain off until interrupt is cleared by the microcontroller
2
One re-try of power FET switching allowed, after that all drivers
remain off until interrupt is cleared by the microcontroller
3
Two re-tries of power FET switching allowed, after that all drivers
remain off until interrupt is cleared by the microcontroller
6.3.4 Divergent Usage of Power FET Gate Driver
The power FET gate driver can be used differently from half bridge applications for driving single power FETs or direct loads.
Each half bridge consisting of one high side and one low side driver can be configured in BRIDGEMODE and
GATECFG1-3 registers.
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Table 6.19: Register BRIDGEMODE (0x20), bridge mode configuration
MSB
LSB
Content
-
ASYNC
DM31
DM30
DM21
DM20
DM11
DM10
Reset value
0
0
0
0
0
0
0
0
Internal access
-
R
R
R
R
R
R
R
External access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
ASYNC: 1: PWMH1-3 and PWML1-3 are not synchronized (CLK input clock does not have ot
be applied), 0: PWMH1-3 and PWML1-3 are synchronized, CLK input clock must be applied
DM3[1:0]: Phase 3 driver mode, see below for coding
DM2[1:0]: Phase 2 driver mode, see below for coding
DM1[1:0]: Phase 1 driver mode, see below for coding
Table 6.20: Register GATECFG1-3 (0x21, 0x22, 0x23), motor phase gate driver control configuration
MSB
LSB
Content
GLSYNC
GLINV
GHHZ
GHPWM
GHLEVEL GLHZ
GLPWM
GLLEVEL
Reset value
0
0
0
1
0
0
1
0
Internal access
R
R
R
R
R
R
R
R
External access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
GLSYNC: Low side driver is controlled synchronous (non inverted) to high side driver (ignored if
DM = 3)
GLINV: Low side driver is controlled inverted to HS driver (ignored if DM != 3)
GHHZ: Switch GH to high impedance
GHPWM: Use PWMH input pin to control high side driver (ignored if GHHZ = 1)
GHLEVEL: High side driver output level, if GHHZ = 0 and GHPWM = 0 (control via SPI possible)
GLHZ: Switch GL to high impedance
GLPWM: Use internal high side driver control to control low side driver (ignored if GLHZ = 1,
depending on GLHZ, GLSYNC and GLINV), refer to
GLLEVEL: Low side driver output level, if GLHZ = 0 and GLPWM = 0 (control via SPI possible)
Note: GLINV = 1 and GLSYNC = 1: driver off due to security reasons
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Figure 27: Illustration of GATECFG register driver control configuration
Table 6.21: Gate driver applications
Divergent usage of Application DM (BRIDGEGATECFG
half bridge
MODE register) register recomrequirement
mendation
Half bridge (standard)
BLDC, EC,
DC motors
3
Depiction
“0-0--0--”
Note: recharge of
bootstrap capacitor
necessary
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Divergent usage of Application DM (BRIDGEGATECFG
half bridge
MODE register) register recomrequirement
mendation
1 NMOS high side
and 1 NMOS low
side FET
DC motors,
other loads
2
“000xx0xx”
2 NMOS low side
FETs
DC motors,
other loads
1
“000xx0xx”
2 direct loads
Small
1
motors, other
loads
“00xxxxxx”
Depiction
Note: recharge of
bootstrap capacitor
necessary
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Divergent usage of Application DM (BRIDGEGATECFG
half bridge
MODE register) register recomrequirement
mendation
1 direct load,
reduced on-resistance
Small
1
motors, other
loads
“10xxxx--”
Driving of external
charge pump
Active high 1
side reverse
polarity protection
“00010000”
-
-
-
0
Depiction
Disabled, GH and GL switched to ground
Security warning: DM1-3 set to 1 or 2: The short circuit protection is not or only partially available. In these cases
the over current detection may be used instead.
Security warning: DM1-3 set to 1 or 2: Both drivers operate independently, so the customer has to guaranty that
no cross current occurs from battery to ground.
Note: External loads, which are connected to VBAT directly, are on-switched during power-up, since the driver outputs are switched to ground.
Note: If using inductive loads in other than half bridge configuration, it is necessary to add free wheeling diodes to
prevent the IC from exceeding absolute maximum ratings.
Examples: Some gate control examples are given in the following table.
Table 6.22: Gate control configuration examples
Description
GATECFG register
PWMH input on HS driver, PWML input on LS driver
“00010010”
PWMH controls GH and GL inversely, PWML enables half bridge
“01010010”
PWMH input on HS driver, LS driver statically to level L
“0001000L”
HS driver statically to level L, PWML input on LS driver
“0000L001”
HS and LS driver high impedance
“00100100”
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
6.4 Measurement Functions
Measurement of motor current and internal analogue signals is available in the IC.
6.4.1 Motor Current Measurement Amplifier
An integrated low speed operational amplifier with external elements measures the motor current via a low side
shunt resistor. Common mode input voltage and gain of the amplifier have to be adjusted by external resistor values.
The amplifier output IO can be connected to an ADC input of the microcontroller. The maximum output voltage is
limited by the internal 3.3V supply VDD.
Figure 28: Motor current measurement amplifier circuitry
6.4.2 Analogue Signal Measurement
The IC is able to provide divided pin potentials and internal analogue signals to the microcontroller. The analogue
signals can be switched to IO pin via AMUX register. The observable voltage range at IO pin is limited from 0V to
VVDD.
Table 6.23: Register AMUX (0x17), analogue signal measurement selection
MSB
LSB
Content
-
-
-
S4
S3
S2
S1
S0
Reset value
0
0
0
0
0
0
0
0
Internal access
-
-
-
R
R
R
R
R
External access
R
R
R
R/W
R/W
R/W
R/W
R/W
Bit Description
S[4]: Reserved, bit must be 0
S[3:0]: Analogue signal selection. See below for coding.
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Table 6.24: Analogue signals measurement code table
AMUX
Analogue signal to IO pin
0
Current amplifier mode (standard)
1
VVIN
2
VIP
3
VTEMP
4
VVBAT / 12
5
VVG / 5
6
Over current comparator threshold (IOCOMPTHR)
7
Low side power FET short circuit threshold (SCTH, SCTH_LS)
8
VGL1
9
VGL2
10
VGL3
AMUX register write access is locked, if EACMUX bit in SECURCTRL register is 0.
Security warning: The switching of internal signals to IO pin disables the motor current measurement. The
absence of motor over current protection is completely at own risk.
Note: This functionality is disabled by default. The activation is subject to the security rules described in section Initial Configuration and Security (setting EACMUX bit in SECURCTRL register).
Example: A recommended scenario from over current measurement to apply an internal signal to the microcontroller is:
●
Set EN_OC bit in IRQMSK1 to 0 (disable interrupt flag)
●
Set IOCOMPTHR register to maximum value (63) to prevent the IC from false over current failure detection
●
Set AMUX register
Example: A recommended scenario to return to over current measurement is:
● Set AMUX register to 0
●
Set IOCOMPTHR register to proper value
●
Set EN_OC bit in IRQMSK1 to 1 (enable interrupt flag)
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
6.5 Monitoring and Safety
The IC provides several failure monitoring and protection functions:
●
Battery over voltage at VBAT pin
●
VG power FET supply under voltage
●
VCC microcontroller supply under voltage
●
Motor over current
●
IC over temperature
●
Watchdog
Table 6.25: Monitoring functions
Function
VBAT over
voltage
Failure condition
Failure actions
Reset condition
VVBAT > VVBAT,OV, Switch all high side
SAFECTRL[3] power FETs off
=1
Depiction
VVBAT < VVBAT,OV
cases SAFECTRL[7:6]:
0: Switch all low side
power FETs on
1: Switch all low side
power FETs off
2: allow switching of low
side power FETs
VG under
voltage
VVG < VVG,UV,
Switch all power FETs
SAFECTRL[2] off
=1
VVG > VVG,UV
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Function
Failure actions
Reset condition
Switch all power FETs
off, reset of external
microcontroller, reset of
internal registers except
IRQSTATx
VVCC >VVCC,UV,
restart of the
IC and
external
microcontroller
Motor over cur- VIO > VDAC,OC
rent
Switch all power FETs
off
VIO < VDAC,OC,
Over temperat- TJ > Totemp
ure with
SAFECTRL[1]
=1
Switch all power FETs,
VCC and VG regulator
off, disable BUS, reset
of external microcontroller, reset of internal
registers except
IRQSTATx
TJ < Totemp,
VCC under
voltage
Failure condition
VVCC < VVCC,UV
Depiction
cleared interrupt
restart of the
IC and
external
microcontroller
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Function
Failure condition
Over temperat- TJ > Totemp
ure with
SAFECTRL[1]
=0
Failure actions
Reset condition
Switch all power FETs
off, disable BUS,
Depiction
TJ < Totemp
Safety warning: The
microcontroller has to
switch into low power
mode immediately, else
the IC might be damaged.
Watchdog
event
No watchdog Switch all power FETs
trigger or false off, reset of external
trigger
microcontroller, reset of
internal registers except
IRQSTATx
Restart of the
IC and
external
microcontroller
The SAFECTRL safety functions register configures the failure reactions of the IC.
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Table 6.26: Register SAFECTRL (0x05), safety function configuration
MSB
LSB
Content
VBATOV_ VBATOV_ VGUV6V
FR1
FR0
SOC
SVBATO
SVG
OTVCCOFF
OTSLEEP
Reset value
0
0
0
1
1
1
1
0
Internal access
R
R
R
R
R
R
R
R
External access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
VBATOV_FR[1:0]: Refer to following table
VGUV6V: VVG under voltage threshold select for VVBAT > 7V (0) or VVBAT > 6V (1)
SOC: Safety function on over current
SVBATO: Safety function on VBAT over voltage
SVG: Safety function on VG over or under voltage
OTVCCOFF: Disable VCC supply on over temperature. This bit has no effect when OTSLEEP
is 1 (VCC is always off in sleep mode).
OTSLEEP: IC shut down on over temperature
Table 6.27: VBAT over voltage failure reaction code table
SAFECTRL[7:6]
VBAT over voltage failure reaction
0
All LS-FETs are switched on, all HS-FETs are switched off automatically
1
All FETs are switched off automatically
2
All HS-FETs are switched off automatically, switching of LS-FETs allowed
6.5.1 Motor Over Current
The motor current measurement amplifier output at IO pin is monitored by the IC. If the voltage exceeds a programmable threshold, a motor over current is detected. The threshold value is calculated to:
V th , OC =
IOCOMPTHR±8
⋅V VDD
64
Table 6.28: Register IOCOMPTHR (0x16), motor over current threshold
MSB
LSB
Content
-
-
D5
D4
D3
D2
D1
D0
Reset value
0
0
0
0
0
0
0
0
Internal access
-
-
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
External access R
Bit Description
D[5:0]: Motor over current threshold value
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Figure 29: Motor over current circuitry
If CMUX register is written accordingly, the motor over current functionality can be applied to other internal analogue
signals.
Security warning: The deactivation of motor over current monitoring is completely at own risk.
Note: This functionality is disabled by default. The activation is subject to the security rules described in section Initial Configuration and Security (setting EACMUX bit in SECURCTRL register).
Table 6.29: Register CMUX (0x18), motor over current comparator input signal selection
MSB
LSB
Content
-
-
-
S4
S3
S2
S1
S0
Reset value
0
0
0
0
0
0
0
0
Internal access
-
-
-
R
R
R
R
R
External access
R
R
R
R/W
R/W
R/W
R/W
R/W
Bit Description
S4: Reserved, bit must be 0
S3: Motor over current comparator configuration. See below for coding.
Table 6.30: Switch analogue signals to motor over current comparator code table
CMUX
Analogue signals
0
Motor over current comparator (standard)
1
VVIN
2
VIP
3
VTEMP
4
VVBAT / 12
5
VVG / 5
6
Over current comparator threshold (IOCOMPTHR)
7
Low side power FET short circuit threshold (SCTH, SCTH_LS)
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
CMUX
Analogue signals
8
VGL1
9
VGL2
10
VGL3
Note: CMUX register write access is locked, if EACMUX bit in SECURCTRL register is 0.
6.5.2 Watchdog
There are two watchdogs available:
●
Register watchdog: standard or window watchdog for monitoring of the external microcontroller
●
CLK watchdog: monitoring of the CLK input clock signal
Table 6.31: Register WDCTRL (0x10), watchdog control
MSB
LSB
Content
WDUSEC PINTRIG
W
WDTOW1 WDTOW0 WDFOW
WDTEST
REGWDEN
CLKWDEN
Reset value
1
0
1
1
-
-
1
1
Internal access
R
R
R
R
W
W
R
R
External access
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Bit Description
WDUSECW: Use closed window for register watchdog (WDT,CW )
PINTRIG: 1: Register watchdog is triggered on PWML3 rising edge, 0: Register watchdog is
triggered via WDTRIG register (SPI access)
WDTOW[1:0]: Register watchdog open window time (WDT,OW)
WDFOW: Register watchdog is in first open window
WDTEST: 1: Register watchdog is stopped (T pin = 'H'), 0: Register watchdog is running
REGWDEN: Enable register watchdog
CLKWDEN: Enable CLK watchdog
For debugging purposes and software upload only, the watchdog can be stopped by setting T pin to VCC level.
6.5.2.1 Register Watchdog
The register watchdog can be configured in WDCTRL register within the first open window. It can be triggered by
SPI access to WDTRIG register or a rising edge at PWML3 input pin.
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Table 6.32: Register WDTRIG (0x11), watchdog trigger
MSB
LSB
Content
-
-
-
-
-
-
-
TRIG
Reset value
0
0
0
0
0
0
0
0
Internal access
-
-
-
-
-
-
-
R
External access
R
R
R
R
R
R
R
R/W
Bit Description
TRIG: Value has to be toggled on each write access in order to trigger the watchdog
6.5.2.2 CLK Watchdog
If enabled in WDCTRL register, the CLK watchdog is running when the IC is in run mode. If the CLK input clock signal is missing, a watchdog failure event is created.
6.5.3 Interrupt
The interrupt bits in IRQSTAT1 and IRQSTAT2 registers are set in case of the accordant failure event. Although
there is no dedicated interrupt pin, an interrupt can be signalized to the microcontroller.
Table 6.33: Interrupt output configuration possibilities
Output Pin
Mode
Configuration
Signal direction
Shared functionality with
VSEL
1)
VVCC = 3.3V IOCFG[1] = 1, IOCFG[0] = 1
High active
VCC regulator voltage selection
VSEL
1)
VVCC = 5V
IOCFG[1] = 1, IOCFG[0] = 1
Low active
VCC regulator voltage selection
-
IOCFG[1] = 0, IOCFG[0] = 1
Low active
SPI interface
SO
2)
1)
Shared functionality with VSEL pin: Only available in run mode, since VSEL is used for VCC regulator voltage selection in power-up mode.
2)
Shared functionality with SO pin: If CSB = 'L', SO is used as SPI data output in any configuration.
An interrupt bit is cleared by writing 1 to the interrupt bit in IRQSTAT registers or power-up (applying battery
voltage). It is not clear during sleep mode.
The interrupt mask bits in IRQMSK1 and IRQMSK2 registers mask the effect of the interrupt bits in IRQSTAT
registers on the selected interrupt output pin (VSEL or SO).
Warning: If shared functionality at SO pin is used, a SPI command causes events at the interrupt line, to be
masked by the microcontroller.
Note: Even if the failure reaction is disabled in SAFECTRL register, the interrupt bits are set.
Note: A wired-or interrupt line at SO pin is not allowed.
Note: After finishing initial configuration the VG under voltage interrupt is likely set, since the VG voltage regulator
needs some time to power-up.
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Table 6.34: Register IRQMSK1 (0x12), interrupt mask register
MSB
LSB
Content
EN_OT
EN_OC
EN_SC_H EN_SC_H EN_SC_H EN_SC_L EN_SC_L EN_SC_L
S3
S2
S1
S3
S2
S1
Reset value
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
External access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
EN_OT: Enable over temperature interrupt
EN_OC: Enable motor over current interrupt / CMUX multiplexer interrupt
EN_SC_HS3: Enable HS 3 short circuit interrupt
EN_SC_HS2: Enable HS 2 short circuit interrupt
EN_SC_HS1: Enable HS 1 short circuit interrupt
EN_SC_LS3: Enable LS 3 short circuit interrupt
EN_SC_LS2: Enable LS 2 short circuit interrupt
EN_SC_LS1: Enable LS 1 short circuit interrupt
Table 6.35: Register IRQSTAT1 (0x13), interrupt status register
MSB
LSB
Content
OT
OC
SC_HS3
SC_HS2
SC_HS1
SC_LS3
SC_LS2
SC_LS1
Reset value
0
0
0
0
0
0
0
0
Internal access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
External access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
OT: Over temperature interrupt flag
OC:Motor over current interrupt flag / CMUX multiplexer interrupt flag
SC_HS3: HS 3 short circuit interrupt flag
SC_HS2: HS 2 short circuit interrupt flag
SC_HS1: HS 1 short circuit interrupt flag
SC_LS3: LS 3 short circuit interrupt flag
SC_LS2: LS 2 short circuit interrupt flag
SC_LS1: LS 1 short circuit interrupt flag
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Table 6.36: Register IRQMSK2 (0x14), interrupt mask register
MSB
LSB
Content
-
EN_CLK_ EN_REG_ EN_PWM EN_VBAT_ EN_VG_O EN_VG_U EN_VCC_
WD
WD
OV
V
V
UV
Reset value
0
0
0
0
0
0
0
0
Internal access
-
R
R
R
R
R
R
R
External access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
EN_CLK_WD: Enable clock watchdog interrupt
EN_REG_WD: Enable register watchdog interrupt
EN_PWM: Enable dedicated hardware at BUS pin (PWM mode) interrupt
EN_VBAT_OV: Enable VBAT over voltage interrupt
EN_VG_OV: Enable VG over voltage interrupt
EN_VG_UV: Enable VG under voltage interrupt
EN_VCC_UV: Enable VCC under voltage interrupt
Table 6.37: Register IRQSTAT2 (0x15), interrupt status register
MSB
LSB
Content
-
CLK_WD
REG_WD PWM
VBAT_OV VG_OV
VG_UV
VCC_UV
Reset value
0
0
0
0
0
0
0
0
Internal access
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
External access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
CLK_WD: Clock watchdog interrupt flag
REG_WD: Register watchdog interrupt flag
PWM: Dedicated hardware at BUS pin (PWM mode) interrupt flag
VBAT_OV: VBAT over voltage interrupt flag
VG_OV: VG over voltage interrupt flag
VG_UV: VG under voltage interrupt flag
VCC_UV: VCC under voltage interrupt flag
6.5.4 Internal Digital Signal Monitoring
Internal digital signals, e. g. monitoring comparator outputs or digital input pin levels, can be monitored by the microcontroller. They can be switched to SO pin transparently via DMUX register or read via SPI in DMON1-2 register.
DMUX register write access is locked, if EDMUX bit in SECURCTRL register is 0.
Table 6.38: Register DMUX (0x19), digital value output SO selection
MSB
LSB
Content
-
-
-
-
S3
S2
S1
S0
Reset value
0
0
0
0
0
0
0
0
Internal access
-
-
-
-
R
R
R
R
External access
R
R
R
R
R/W
R/W
R/W
R/W
Bit Description
S3:0 : SO pin digital signal output selection. See below for coding.
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Table 6.39: Digital signal output code table
Signal at SO pin 1)
DMUX
0
No internal digital signal output
1
VSEL pin level
2
S pin level
3
T pin level
4
Motor over current comparator level
5
Over temperature comparator level
6
On-state of low side gate driver output GL1
7
On-state of low side gate driver output GL2
8
On-state of low side gate driver output GL3
9
VG under voltage comparator level
1)
Shared functionality with SO pin: If CSB = 'L', SO is used as SPI data output in any configuration.
Table 6.40: Register DMON1 (0x1A), digital value monitoring
MSB
LSB
Content
OT
OC
SC_HS3
SC_HS2
SC_HS1
SC_LS3
SC_LS2
SC_LS1
Reset value
-
-
-
-
-
-
-
-
Internal access
W
W
W
W
W
W
W
W
External access
R
R
R
R
R
R
R
R
Bit Description
OT: Over temperature comparator level
OC: Motor over current comparator level
SC_HS3: High side 3 short circuit comparator level
SC_HS2: High side 2 short circuit comparator level
SC_HS1: High side 1 short circuit comparator level
SC_LS3: Low side 3 short circuit comparator level
SC_LS2: Low side 2 short circuit comparator level
SC_LS1: Low side 1 short circuit comparator level
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Table 6.41: Register DMON2 (0x1B), digital value monitoring
MSB
LSB
Content
S
VTHONLS VTHONLS VTHONLS VBAT_OV VG_OV
3
2
1
VG_UV
-
Reset value
-
-
-
-
-
-
-
0
Internal access
W
W
W
W
W
W
W
W
External access
R
R
R
R
R
R
R
R
Bit Description
S: Pin S input comparator level
VTHONLS3: Low side 3 on threshold comparator level
VTHONLS2: Low side 2 on threshold comparator level
VTHONLS1: Low side 1 on threshold comparator level
VBAT_OV: VBAT over voltage comparator level
VG_OV: VG over voltage comparator level
VG_UV: VG under voltage comparator level
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
6.6 Communication Interfaces
6.6.1 BUS interface (LIN or PWM mode)
The BUS interface is a bidirectional, single wired, high voltage, low active interface. It can be used as a transceiver
for LIN standard (523.01 and 523.02 only) or PWM control with error feedback.
Figure 30: BUS block diagram
The BUS interface can be used as master or slave. The transmission data on TXD pin is converted into the BUS
signal through a current limited, wave-shaping low side driver. The receiver converts the data stream from BUS to
RXD pin.
In recessive state, BUS is pulled to VBAT by an internal pull-up resistor (30kΩ typically) and a diode in series, so no
external pull-up components are required for slave applications. Master applications require an additional external
pull-up resistor and a series diode.
The BUS transceiver can handle a voltage swing from 40V down to ground and survive -27V. The device also prevents from back current through the BUS pin to the supply pin in case of a ground shift or loss or supply voltage disconnection.
Figure 31: BUS transceiver transmit timing
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Figure 32: BUS transceiver receive timing
6.6.2 Flash Mode and TXD Time-Out
A flash mode allows an increasing of the transmit baud rate up to 115 kBd and the receive baud rate up to 250kBd.
The flash mode can be activated by setting IOCFG[6] = 1.
In order to prevent the BUS from being permanent dominant in case of permanent low level at TXD pin, a TXD
time-out timer switches BUS to recessive mode after approximately 8ms. The timer is triggered by a negative TXD
edge and reset by a positive TXD edge. This function can be deactivated by writing IOCFG[7] = 0.
6.6.3 LIN Compatibility (523.01 and 523.02 only)
The IC fulfils LIN standard 2.2A (ISO 9141). LIN conformity is given at battery voltage 7V to 18V.
LIN2.2 transceivers are backward compatible down to LIN1.3 at physical layer. But not the other way around. A node
using LIN 2.2 physical layer can operate in a LIN 1.3 cluster. 1)
1)
Refer to LIN Specification Package Revision 2.2A December 31, 2010, Page 15
6.6.4 Communication Interfaces Configuration
BUS interface and interrupt output can be configured in IOCFG register.
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Table 6.42: Register IOCFG (0x06), interface configuration
MSB
LSB
Content
TXDTO_E LIN_FLAS PWMN
H
FREQ
BUSIF
PWMIF
-
VSELDIR
EINT
Reset value
1
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
-
R
R
External access
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Bit Description
TXDTO_EN: Enable TXD dominant clamping time-out
LIN_FLASH: Enable LIN flash mode
PWMFREQ: 1: 2 kHz mode (500 kHz sampling frequency), 0: 1 kHz mode (250 kHz sampling
frequency)
BUSIF: Enable dedicated hardware for duty cycle measurement
PWMIF: 1: Apply dedicated hardware for duty cycle measurement on S pin, 0: Apply dedicated
hardware for duty cycle measurement on BUS pin
VSELDIR: 1 VSEL is interrupt output, 0: SO is interrupt output
EINT: Enable shared functionality at VSEL or SO pin (interrupt output)
6.6.5 Dedicated Hardware for PWM Duty Cycle Measurement
Dedicated hardware can be used to support the external microcontroller in polling the RXD pin. The bus PWM interface uses the internal frequency f CLKDIV / 16 (refer to section CLK input clock):
●
4Mhz / 16 = 250kHz for 4MHz clock base
●
5Mhz / 16 = 312.5kHz for 5MHz clock base
●
6Mhz / 16 = 375kHz for 6MHz clock base
The registers are updated every 16 * 255 / fCLKDIV:
●
16 * 255 / 4MHz = 1.020ms for 4MHz clock base
●
16 * 255 / 5MHz = 816us for 5MHz clock base
●
16 * 255 / 6MHz = 680us for 6MHz clock base.
The PMW_LH and PWM_HL registers contain the time values of RXD edge events of the previous sample period.
Value 255 means, that there was no proper edge found.
To signalize the availability of new register values, an interrupt is generated. If the controller does not read the
register values within the current sample period, the old values will be overwritten by the new ones.
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Figure 33: PWM duty cycle measurement timing diagram
Table 6.43: Register PWM_LH (0x09), PWM rising edge position
MSB
LSB
Content
D7
D6
D5
D4
D3
D2
D1
D0
Reset value
0
0
0
0
0
0
0
0
Internal access
W
W
W
W
W
W
W
W
External access
R
R
R
R
R
R
R
R
Bit Description
D[7:0]: PWM rising edge position value
Table 6.44: Register PWM_HL (0x0A),PWM falling edge position
MSB
LSB
Content
D7
D6
D5
D4
D3
D2
D1
D0
Reset value
0
0
0
0
0
0
0
0
Internal access
W
W
W
W
W
W
W
W
External access
R
R
R
R
R
R
R
R
Bit Description
D[7:0]: PWM falling edge position value
Note: The sampling clock is not depending on the PWM-frequency of the interface. So, with slow PWM interfaces it
may take a number of readouts by the µC to be able to calculate the information which is transferred by the PWM
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
interface. The advantage of this "open" solution is, that the controller is able to analyse even special PWM coding
with additional information hidden inside the cycle.
6.6.6 SPI
The SPI clock is high active (CPOL = 0). The data is sampled with second clock edge (CPHA = 1). The SPI output
pin SO is high resistive, if CSB = 'H' (SPI inactive).
Note: It is recommended to re-read every SPI write command to ensure a correct configuration of the IC.
Figure 34: SPI write command
Figure 35: SPI read command
A[6:0]: register address, D[7:0]: register data
Figure 36: SPI timing diagram
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
6.9 Register Table
Table 6.47: Registers
Register Name
Address
Description
CLKCTRL
0x01
CLK input clock and clock divider configuration
CHIPCTRL
0x02
Wake-up configuration
SLEEPCTRL
0x03
Sleep mode control
SECURCTRL
0x04
Security configuration
SAFECTRL
0x05
Safety function configuration
IOCFG
0x06
Interface configuration
VREGCTRL
0x07
VCC and VG supply control
PWM_LH
0x09
PWM rising edge position
PWM_HL
0x0A
PWM falling edge position
SCPCTRL
0x0B
Superior short circuit protection control
WDCTRL
0x10
Watchdog control
WDTRIG
0x11
Watchdog trigger
IRQMSK1
0x12
Interrupt mask register
IRQSTAT1
0x13
Interrupt status register
IRQMSK2
0x14
Interrupt mask register
IRQSTAT2
0x15
Interrupt status register
IOCOMPTHR
0x16
IO Comparator threshold
AMUX
0x17
Analogue signal measurement selection
CMUX
0x18
Motor over current comparator input signal selection
DMUX
0x19
Digital value output SO selection
DMON1
0x1A
Digital value monitoring
DMON2
0x1B
Digital value monitoring
BRIDGEMODE
0x20
Bridge mode configuration
GATECFG1
0x21
Motor phase gate driver control configuration, half bridge 1
GATECFG2
0x22
Motor phase gate driver control configuration, half bridge 2
GATECFG3
0x23
Motor phase gate driver control configuration, half bridge 3
DEADTIME_LH
0x24
Low to high transition dead time
DEADTIME_HL
0x25
High to low transition dead time
SCTH
0x26
Short circuit threshold selection (low resolution mode) and masking time
SCTH_HS
0x28
High side short circuit threshold selection (high resolution mode)
SCTH_LS
0x29
Low side short circuit threshold selection (high resolution mode)
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
After setting ESECURE bit in SECURCTRL register, the registers listed in the table below are read-only.
Table 6.48: Restricted registers
Restriced Register Name
Comment
CLKCTRL
BRIDGEMODE
GATECFG1-3[7:3]
DEADTIME_LH
Writeable if bit EDEADMULT in register SECURCTRL is set.
DEADTIME_HL
Writeable if bit EDEADMULT in register SECURCTRL is set.
SECURCTRL
SAFECTRL
SCPCTRL
WDCTRL
IOCFG[7:1]
VREGCTRL
CHIPCTRL
AMUX
Writeable if bit EACMUX in register SECURCTRL is set.
CMUX
Writeable if bit EACMUX in register SECURCTRL is set.
DMUX
Writeable if bit EDMUX in register SECURCTRL is set.
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
7 Package Reference
7.1 QFN44L7
Package Outline and Dimensions are according JEDEC MO-220 K, variant VKKD-3
Note: The mm values are valid, the inch values contain rounding errors.
Note: For assembler specific pin1 identification please see QM document 08SP0363.xx (Pin 1 specification)
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
7.2 QFN48L7
Package Outline and Dimensions are according JEDEC MO-220 K, variant VKKD-6, except reduced terminal length
of 0.4mm.
Note: The mm values are valid, the inch values contain rounding errors.
Note: For assembler specific pin1 identification please see QM document 08SP0363.xx (Pin 1 specification)
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
7.3 QSOP44
Package Outline and Dimensions: No special JEDEC specification available for 300mil QSOP. Package dimensions
are according JEDEC MS-013-E, variant AE (SO28). Differences are e (pitch) and b (terminal lead width, is within
JEDEC MS-013-E but, in general, more at the lower limit).
Note: The mm values are valid, the inch values contain rounding errors.
Note: For assembler specific pin1 identification please see QM document 08SP0363.xx (Pin 1 specification)
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
8 Typical Application
Figure 37: Typical application
Note: Do not insert filter capacitors between battery and the positive terminal of shunt resistor.
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B6 Bridge FET Driver with LIN/PWM Interface
E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Table 8.1: External Components
External Components
VBAT capacitance
Condition
Symbol
CVBAT
6)
ceramic
Min
Typ
Max
Unit
33
47
-
μF
80
100
-
μF
Battery input capacitance, close to battery
and ground PCB input 6)
CVBAT,EMC
-
10
-
nF
Bridge supply storage capacitance 6)
CVBAT,storage
-
2)
-
mF
CVG
8
10
50
μF
80
100
120
nF
8
3)
50
μF
80
100
120
nF
CVDD
RVSEL
RINT
80
4.7
-
330
56
500
6.8
-
nF
kΩ
kΩ
CBST
80
330
4)
nF
-
-
-
-
VG capacitance
6)
RESR > 0.8Ω
ceramic
VCC capacitance
CVCC
ceramic
VDD capacitance
VSEL pull resistance
Interrupt series resistor
ceramic
VSEL used as
interrupt output
Bootstrap capacitance
Bootstrap diode
RESR > 3Ω (series DBST
resistance might
be added alternatively), Ipeak > 4A
Series gate resistances of power FETs
RGate
20
-
-
Ω
Power FET gate-source pull resistance
RGS
-
100
-
kΩ
fPWM = 25kHz, 12V QFET
-
-
250
nC
fPWM = 50kHz, 12V
-
-
100
nC
Case no reverse
RSC,HS
polarity protection
at power FET
stage
80
-
-
Ω
Capacitive gate charge of power FETs
High side short circuit reference protection series resistance, comparator
threshold is increased by ISC,HS * RSC,HS
Current measurement amplifier resistances
RSH, RFP, RFN, RPP, RG
5)
-
-
T pull down resistance, short distance to
ground
RT
-
1.2
kΩ
0
No other components than buffer capacitors allowed
Depending on application
Depending on load transients
4)
Depending on CVG
5)
Amplifier to be designed by customer
6)
For ISO pulse and load dump >50V required
1)
2)
3)
To avoid EMC problems at PCB level, the clock lines on PCB – particularly the CLK line at high frequency (>6MHz)
- must be designed very carefully:
●
Make short connection between microcontroller and IC at clock and ground line
●
Avoid ground loops
●
Insert 100Ω ... 120Ω resistors close to clock driver output for line matching reasons
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E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
9 Revision History
Rev. ID
.00
Author
H. Hauswald
Date
07.05.2014
Description of changes
Initial version (based on E523.01B data sheet)
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E523.01C, 02C, 11C, 12C
PRELIMINARY INFORMATION – May, 7, 2014
Table of Content
1 Absolute Maximum Ratings...................................................................................................................................... 7
2 ESD Protection....................................................................................................................................................... 10
3 Recommended Operating Conditions..................................................................................................................... 11
4 Electrical Characteristics........................................................................................................................................ 13
4.1 Power Supply and Management.................................................................................................................... 13
4.2 Power FET Gate Driver.................................................................................................................................. 15
4.3 Measurement Functions................................................................................................................................. 15
4.4 Monitoring and Safety.................................................................................................................................... 16
4.5 Communication Interfaces............................................................................................................................. 17
5 Typical Operating Characteristics........................................................................................................................... 20
6 Detailed functional description............................................................................................................................... 22
6.1 Power Supply and Management.................................................................................................................... 23
6.1.1 VCC Microcontroller Supply................................................................................................................... 23
6.1.2 Power FET Gate Voltage Supply VG...................................................................................................... 26
6.1.3 Internal Supply VDD............................................................................................................................... 26
6.1.4 Reset...................................................................................................................................................... 26
6.1.5 IC State Control...................................................................................................................................... 26
6.1.5.1 Power Up....................................................................................................................................... 27
6.1.5.2 Shut-down and Sleep Mode........................................................................................................... 29
6.1.5.3 Wake Up........................................................................................................................................ 30
6.1.6 Board Level Protection........................................................................................................................... 32
6.2 Initial Configuration and Security.................................................................................................................... 33
6.3 Power FET Gate Driver.................................................................................................................................. 35
6.3.1 Control Modes for Half Bridge Applications............................................................................................ 36
6.3.2 Dead Time and CLK Input Clock............................................................................................................ 37
6.3.2.1 CLK Input Clock............................................................................................................................. 37
6.3.2.2 Dead Time Generation................................................................................................................... 38
6.3.3 Short Circuit Protection.......................................................................................................................... 40
6.3.3.1 Superior Short Circuit Failure Reaction ......................................................................................... 42
6.3.4 Divergent Usage of Power FET Gate Driver........................................................................................... 43
6.4 Measurement Functions................................................................................................................................. 48
6.4.1 Motor Current Measurement Amplifier................................................................................................... 48
6.4.2 Analogue Signal Measurement.............................................................................................................. 48
6.5 Monitoring and Safety.................................................................................................................................... 50
6.5.1 Motor Over Current................................................................................................................................ 53
6.5.2 Watchdog............................................................................................................................................... 55
6.5.2.1 Register Watchdog......................................................................................................................... 55
6.5.2.2 CLK Watchdog............................................................................................................................... 56
6.5.3 Interrupt.................................................................................................................................................. 56
6.5.4 Internal Digital Signal Monitoring............................................................................................................ 58
6.6 Communication Interfaces............................................................................................................................. 61
6.6.1 BUS interface (LIN or PWM mode)........................................................................................................ 61
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B6 Bridge FET Driver with LIN/PWM Interface
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PRELIMINARY INFORMATION – May, 7, 2014
6.6.2 Flash Mode and TXD Time-Out............................................................................................................. 62
6.6.3 LIN Compatibility (523.01 and 523.02 only)............................................................................................ 62
6.6.4 Communication Interfaces Configuration............................................................................................... 62
6.6.5 Dedicated Hardware for PWM Duty Cycle Measurement.......................................................................63
6.6.6 SPI......................................................................................................................................................... 65
6.9 Register Table................................................................................................................................................ 66
7 Package Reference................................................................................................................................................ 68
7.1 QFN44L7 ...................................................................................................................................................... 68
7.2 QFN48L7....................................................................................................................................................... 69
7.3 QSOP44......................................................................................................................................................... 70
8 Typical Application.................................................................................................................................................. 71
9 Revision History..................................................................................................................................................... 73
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PRELIMINARY INFORMATION – May, 7, 2014
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