MP18021
100V High Frequency
Half-Bridge Gate Driver
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP18021 is a high frequency, 100V half
bridge N-channel power MOSFET driver. Its low
side and high side driver channels are
independently controlled and matched with less
than 5ns in time delay. Under voltage lock-out on
both high side and low side supplies force their
outputs low in case of insufficient supply. The
integrated bootstrap diode reduces external
component count.
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
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

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Drives N-channel MOSFET half bridge
100V VBST voltage range
On-chip bootstrap diode
Typical 16ns propagation delay time
Less than 5ns gate drive matching
Drive 1nF load with 12ns/9ns rise/fall times
with 12V VDD
TTL compatible input
Less than 150A quiescent current
UVLO for both high side and low side
In SOIC8 EPAD and 3×3mm QFN8
Packages
APPLICATIONS




Telecom half bridge power supplies
Avionics DC-DC converters
Two-switch forward converters
Active clamp forward converters
All MPS parts are lead-free, halogen free, and adhere to the RoHS
directive. For MPS green status, please visit MPS website under Quality
Assurance.
“MPS” and “The Future of Analog IC Technology” are Registered
Trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
+12V
48V
SECONDARY
SIDE
CIRCUIT
VDD
BST
PWM
CONTROLLER
INL
CONTROL
INH
DRIVE
HI
DRVH
DRIVE
LO
DRVL
SW
MP18021
VSS
ISOLATION
AND
FEEDBACK
MP18021 Rev. 1.11
www.MonolithicPower.com
10/20/2015
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
1
MP18021―100V HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
ORDERING INFORMATION
Part Number*
Top Marking
Free Air Temperature (TA)
MP18021HN
Package
SOIC8EP
MP18021HN
-40C to + 125C
MP18021HQ
QFN8 (3x 3mm)
ABN
-40C to + 125C
* For Tape & Reel, add suffix –Z (e.g. MP18021HN–Z);
For RoHS compliant packaging, add suffix –LF; (e.g. MP18021HN–LF–Z)
For Tape & Reel, add suffix –Z (e.g. MP18021HQ–Z);
For RoHS compliant packaging, add suffix –LF; (e.g. MP18021HQ–LF–Z)
PACKAGE REFERENCE
TOP VIEW
TOP VIEW
VDD
1
8
DRVL
VDD 1
8 DRVL
BST
2
7
VSS
BST 2
7 VSS
DRVH
3
6
INL
DRVH 3
6 INL
INH
SW 4
5 INH
SW
4
5
EXPOSED PAD
ON BACKSIDE
SOIC8EP
QFN8
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
Supply Voltage (VDD).....................-0.3V to +18V
SW Voltage (VSW) .........................-5.0V to 100V
BST Voltage (VBST) .......................-0.3V to 100V
BST to SW ....................................-0.3V to +18V
DRVH to SW .................................-0.3V to +18V
All Other Pins ...................... -0.3V to (VDD+0.3V)
(2)
Continuous Power Dissipation (TA =+25°C)
SOIC8 (Exposed Pad) ............................... 2.6W
QFN8 (3x3) ................................................ 2.5W
Junction Temperature ...............................150C
Lead Temperature ....................................260C
Storage Temperature............... -65°C to +150C
SOIC8 (Exposed Pad) ............ 48 ...... 10... C/W
QFN8 (3x3)............................. 50 ...... 12... C/W
Recommended Operating Conditions
(3)
(4)
θJA
θJC
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
Supply Voltage VDD .....................+9.0V to 16.0V
SW Voltage (VSW) ..................-1.0V to 100V-VDD
SW slew rate......................................<50V/nsec
Operating Junct. Temp (TJ)...... -40C to +140C
MP18021 Rev. 1.11
www.MonolithicPower.com
10/20/2015
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
2
MP18021―100V HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
ELECTRICAL CHARACTERISTICS
VDD = VBST-VSW=12V, VSS=VSW = 0V, No load at DRVH and DRVL, TA= +25C, unless otherwise
noted.
Parameter
Symbol Condition
Supply Currents
VDD quiescent current
IDDQ
INL=INH=0
VDD operating current
IDDO
fsw=500kHz
Floating driver quiescent current
IBSTQ
INL=INH=0
Floating driver operating current
IBSTO
fsw=500kHz
Leakage Current
ILK
BST=SW=100V
Inputs
INL/INH High
INL/INH Low
INL/INH
internal
pull-down
RIN
resistance
Under Voltage Protection
VDD rising threshold
VDDR
VDD hysteresis
VDDH
(BST-SW) rising threshold
VBSTR
(BST-SW) hysteresis
VBSTH
Bootstrap Diode
Bootstrap diode VF @ 100uA
VF1
Bootstrap diode VF @ 100mA
VF2
Bootstrap diode dynamic R
RD
@ 100mA
Low Side Gate Driver
Low level output voltage
VOLL
IO=100mA
High level output voltage to rail
VOHL
IO=-100mA
VDRVL=0V, VDD=12V
Peak pull-up current
IOHL
VDRVL=0V, VDD=16V
VDRVL=VDD=12V
Peak pull-down current
IOLL
VDRVL=VDD=16V
Floating Gate Driver
Low level output voltage
VOLH
IO=100mA
High level output voltage to rail
VOHH IO=-100mA
VDRVH=0V, VDD=12V
Peak pull-up current
IOHH
VDRVH=0V, VDD=16V
VDRVH=VDD=12V
Peak pull-down current
IOLH
VDRVH=VDD=16V
Min
1
Typ
Max
Units
100
2.8
60
2.1
0.05
150
3.5
90
3
1
µA
mA
µA
mA
A
2
1.4
2.4
V
V
185
7.7
6.7
8.1
0.5
7.1
0.55
k
8.5
7.5
0.5
0.9
2.5
V
V
V
V
V
V

0.15
0.45
1.5
2.5
2.5
3.5
0.22
0.6
V
V
A
A
A
A
0.15
0.45
1.5
2.5
2.5
3.5
0.22
0.6
V
V
A
A
A
A
MP18021 Rev. 1.11
www.MonolithicPower.com
10/20/2015
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
3
MP18021―100V HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
ELECTRICAL CHARACTERISTICS (continued)
VDD = VBST-VSW=12V, VSS=VSW = 0V, No load at DRVH and DRVL, TA= +25C, unless otherwise
noted.
Parameter
Symbol
Switching Spec. --- Low Side Gate Driver
Turn-off propagation delay
TDLFF
INL falling to DRVL falling
Turn-on propagation delay
TDLRR
INL rising to DRVL rising
DRVL rise time
DRVL fall time
Switching Spec. --- Floating Gate Driver
Turn-off propagation delay
TDHFF
INL falling to DRVH falling
Turn-on propagation delay
TDHRR
INL rising to DRVH rising
DRVH rise time
DRVH fall time
Switching Spec. --- Matching
Floating driver turn-off to low
TMON
side drive turn-on
Low side driver turn-off to floating
TMOFF
driver turn-on
Minimum input pulse width that
TPW
changes the output
Bootstrap diode turn-on or turnTBS
off time
(5)
Over Temperature Protection OTP entry threshold OTP recovery threshold OTP hysteresis Condition
Min
Typ
Max
16
Units
ns
16
CL=1nF
CL=1nF
CL=1nF
CL=1nF
12
9
ns
ns
16
ns
16
ns
12
9
ns
ns
1
5
ns
1
5
ns
50(5)
ns
10(5)
ns
160
140
20
C
Note:
5) Derived from bench characterization. Not tested in production.
MP18021 Rev. 1.11
www.MonolithicPower.com
10/20/2015
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
4
MP18021―100V HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
PIN FUNCTIONS
Pin #
Name
1
VDD
2
BST
3
4
5
6
7
8
Description
Supply input. This pin supplies power to all the internal circuitry. A decoupling capacitor to
ground must be placed close to this pin to ensure stable and clean supply.
Bootstrap. This is the positive power supply for the internal floating high-side MOSFET driver.
Connect a bypass capacitor between this pin and SW pin.
Floating driver output.
Switching node.
Control signal input for the floating driver.
Control signal input for the low side driver.
DRVH
SW
INH
INL
VSS,
Exposed Chip ground. Connect to Exposed pad to VSS for proper thermal operation.
Pad
DRVL Low side driver output.
MP18021 Rev. 1.11
www.MonolithicPower.com
10/20/2015
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
5
MP18021―100V HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
TYPICAL PERFORMANCE CHARACTERISTICS
VDD =12V, VSS=VSW = 0V, TA= +25C, unless otherwise noted.
IDDO Operation Current vs.
Frequency
IBSTO Operation Current vs.
Frequency
4
6
IBSTO (mA)
3
3
T=25oC
2
T=125oC
T=125oC
2
T=-40oC
T=0oC
1
1
0.5
VBST=VDD=12V
VBST=VDD=14V
0.4
0.3
0.2
0.1
0
0
200
400
600
800
0
0
1000
Low Level Output Voltage vs.
Temperature
200
400
600
800
0
-50
1000
Undervoltage Lockout
Threshold vs.Temperature
0
50
100
150
Undervoltage Lockout
Hysteresis vs.Temperature
560
8.5
0.3
550
0.25
VBST=VDD=12V
0.15
VBST=VDD=14V
0.1
VDDR
VBSTH,VDDH (mV)
0.2 VBST=VDD=9V
VBSTR,VDDR (V)
8
VOLL,VOLH (V)
VBST=VDD=9V
0.6
T=25oC
VOHL,VOHH (V)
T=-40oC
T=0oC
4
IDDO (mA)
0.8
0.7
5
7.5
VBSTR
7
0.05
540
VBSTH
530
520
510
VDDH
500
0
50
100
6.5
-50
150
Propagation Delay vs.
Temperature
50
100
0
50
100
150
Peak Pull-down Current vs.
Output Voltage
2
3
TDHRR
19
2.5
1.5
IOHH,IOHL (A)
18
TDLFF
TDLRR
16
TDHFF
15
1
2
1.5
1
0.5
0.5
14
13
-50
490
-50
150
Peak Pull-up Current vs.
Output Voltage
20
17
0
IOLH,IOLL (A)
0
-50
TDHRR,TDLRR,TDHFF,TDLFF ( ns )
High Level Output
Voltage vs.Temperature
0
50
100
150
0
0
2
4
6
8
VDRVH,VDRVL (V)
10
12
0
0
2
4
6
8
10
12
VDRVH,VDRVL (V)
MP18021 Rev. 1.11
www.MonolithicPower.com
10/20/2015
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
6
MP18021―100V HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VDD =12V, VSS=VSW = 0V, TA= +25C, unless otherwise noted.
Quiescent Current vs.
Voltage
Bootstrap Diode I-V
Characteristics
100
IDDQ vs. VDD
120
0.1
0.01
0.001
VSW TO VSS VOLTAGE (V)
140
IDDQ,IBSTQ (uA)
FORWARD CURRENT (A)
1
Maximum V SW Voltage vs.
V DD Voltage
100
IBSTQ vs. V BST
80
60
0.0001
0.5
0.6
0.7
0.8
0.9
1
40
80
60
40
20
0
5
7.5
10
12.5
15
17.5
12
20
VDD,VBST (V)
FORWARD VOLTAGE (V)
Turn-on Propagation Delay
13
14
15
16
V DD TO V SS VOLTAGE (V)
Gate Drive Matching TMOFF
Drive Rise Time (1nF Load)
10V/div.
10V/div.
10V/div.
5V/div.
10V/div.
5V/div.
10V/div.
10V/div.
10V/div.
Turn-off Propagation Delay
Gate Drive Matching TMON
Drive Fall Time (1nF Load)
10V/div.
10V/div.
10V/div.
5V/div.
10V/div.
10V/div.
5V/div.
10V/div.
10V/div.
MP18021 Rev. 1.11
www.MonolithicPower.com
10/20/2015
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
7
MP18021―100V HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
BLOCK DIAGRAM
BST
VDD
UNDER
VOLTAGE
DRVH
LEVEL SHIFT
DRIVER
SW
INH
UNDER
VOLTAGE
DRVL
DRIVER
INL
VSS
Figure 1—Function Block Diagram
INL
INPUT
(INH, INL)
INH
TDHRR, TDLRR
TDHFF, TDLFF
OUTPUT
(DRVH,
DRVL)
DRVL
TMON
TMOFF
DRVH
Figure 2—Timing Diagram
MP18021 Rev. 1.11
www.MonolithicPower.com
10/20/2015
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
8
MP18021―100V HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
PACKAGE INFORMATION
SOIC8 (EXPOSED PAD)
0.189(4.80)
0.197(5.00)
0.124(3.15)
0.136(3.45)
8
5
0.150(3.80)
0.157(4.00)
PIN 1 ID
1
0.228(5.80)
0.244(6.20)
0.089(2.26)
0.101(2.56)
4
TOP VIEW
BOTTOM VIEW
SEE DETAIL "A"
0.051(1.30)
0.067(1.70)
SEATING PLANE
0.000(0.00)
0.006(0.15)
0.013(0.33)
0.020(0.51)
0.0075(0.19)
0.0098(0.25)
SIDE VIEW
0.050(1.27)
BSC
FRONT VIEW
0.010(0.25)
x 45o
0.020(0.50)
GAUGE PLANE
0.010(0.25) BSC
0.050(1.27)
0.024(0.61)
0o-8o
0.016(0.41)
0.050(1.27)
0.063(1.60)
DETAIL "A"
0.103(2.62)
0.138(3.51)
RECOMMENDED LAND PATTERN
0.213(5.40)
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION BA.
6) DRAWING IS NOT TO SCALE.
MP18021 Rev. 1.11
www.MonolithicPower.com
10/20/2015
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
9
MP18021―100V HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
QFN8 (3mm×3mm)
2.90
3.10
0.30
0.50
PIN 1 ID
MARKING
0.20
0.30
2.90
3.10
PIN 1 ID
INDEX AREA
1.45
1.75
PIN 1 ID
SEE DETAIL A
8
1
2.25
2.55
0.65
BSC
4
5
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A
0.30x45º TYP.
PIN 1 ID OPTION B
R0.20 TYP.
0.80
1.00
0.20 REF
0.00
0.05
SIDE VIEW
DETAIL A
NOTE:
2.90
0.70
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEEC-2.
5) DRAWING IS NOT TO SCALE.
1.70
0.25
2.50
0.65
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP18021 Rev. 1.11
www.MonolithicPower.com
10/20/2015
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
10