ESA strategy
ASICs and FPGAs for space
A. Fernandez Leon / B. Glass
ESA TEC-EDM
19/03/2013
ESA UNCLASSIFIED – For Official Use
Outline
1. European Space Agency
2. ESA technology budgets, procurement process
3. ESA microelectronics teams , activity overview
4. ASIC/FPGA in space: where, special concerns
5. Radiation effects, mitigation techniques
6. ASIC/FPGA technologies in use / development
7. Next Generation technology developments
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 2
ESA UNCLASSIFIED – For Official Use
PURPOSE OF ESA
VIDEO: http://spaceinvideos.esa.int/Videos/2012/10/Meet_ESA_the_space_agency_for_Europe
“To provide for and promote, for exclusively peaceful purposes,
cooperation among European states in space research and
technology and their space applications.”
Article 2 of ESA Convention
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 3
ESA UNCLASSIFIED – For Official Use
ESA FACTS AND FIGURES
•
Over 40 years of experience
•
20 Member States
•
Five establishments in Europe,
about 2200 staff
•
4 billion Euro budget (2012)
•
Over 70 satellites designed, tested
and operated in flight
•
17 scientific satellites in operation
•
Six types of launcher developed
•
Celebrated the 200th launch of
Ariane in February 2011
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 4
ESA UNCLASSIFIED – For Official Use
20 MEMBER STATES AND GROWING
ESA has 20 Member States: 17
states of the EU (AT, BE, CZ, DE,
DK, ES, FI, FR, IT, GR, IE, LU, NL,
PO, PT, RO, SE, UK) plus Norway
and Switzerland.
Eight other EU states have
Cooperation Agreements with ESA:
Estonia, Slovenia, Hungary, Cyprus,
Latvia, Lithuania, Malta and the Slovak
Republic.
Bulgaria is negotiating a Cooperation
Agreement.
Canada takes part in some programs
under a Cooperation Agreement.
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 5
ESA UNCLASSIFIED – For Official Use
ESA sites, offices, ground stations
EAC
ESTEC
(Noordwijk) (Cologne)
Salmijaervi
(Kiruna)
Harwell
ESA HQ
(Paris)
ESA sites/facilities
Offices
ESOC
(Darmstadt)
Brussels
Redu
Toulouse
Oberpfaffenhofen
Cebreros,
Villafranca
ESA ground stations
ESAC
(Madrid)
ESRIN
(Rome)
Moscow
Santa Maria
Washington
Kourou
Houston
Maspalomas
Malargüe
New Norcia
Perth
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 6
ESA UNCLASSIFIED – For Official Use
ESA – ESTEC establishment
European Space Research and Technology Centre (ESTEC)
http://www.esa.int/SPECIALS/ESTEC/index.html
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 7
ESA UNCLASSIFIED – For Official Use
Missions
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 8
ESA UNCLASSIFIED – For Official Use
Outline
1. European Space Agency
2. ESA technology budgets, procurement process
3. ESA microelectronics teams , activity overview
4. ASIC/FPGA in space: where, special concerns
5. Radiation effects, mitigation techniques
6. ASIC/FPGA technologies in use / development
7. Next Generation technology developments
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 9
ESA UNCLASSIFIED – For Official Use
ESA Technology development programs:
ESA member states (delegations) fund multiple
technology programmes:
 Mandatory
•
•
•
•
•
TRP
ECI
GSP
ITI
LET-SME
Basic Technology Research Programme
European Component Initiative
General Studies Programme
Innovation Triangle Initiative
Leading-Edge Technologies from Small and Medium sized Enterprises
 Optional
• GSTP
• ARTES
(ESA delegates have to support / co-fund)
Technology General Support Technology Programme
Advanced Research in Telecommunications Systems
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 10
ESA UNCLASSIFIED – For Official Use
10
ESA activities: from ideas to results
ESA staff
activity
ideas
Technology development ideas and priorities are “HARMONISED” with Industry,
Vendors and Agencies ( => “TECHNOLOGY DOSIERS” with “roadmaps”)
ESA mandatory
programs (e.g.
TRP)
ESA optional
Programs (e.g.
GSTP)
ESA Technical & Contract
Officers
ESA
delegates
approve
ESA
Workplans
ESA
Invitation
To Tender
(“EMITS”
on-line)
ESA staff
Tender
Evaluation
Board
Industry
bids
Industry
activity
unsolicited
proposals
Executive Summaries in
ESA microelectronics website
Contract
negotiation
& Kick-Off
Contract
Execution
performed
by
Industry
consortium
deliverables
ESA Final Presentation
Days & ESA Workshops
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 11
ESA UNCLASSIFIED – For Official Use
11
Timeline from R&D to Commercialization
TRP, GSTP, FP7, ARTES
Typ 2-3 years
R&D
Phase
European Components
Initiative
Up to 2-3 years
Extended
Development/
contingencies
Typ 1-2 y
Evaluation /
Qualification
Initial Investment
TRL 2- TRL3/4
(Technology
developed )
Typ 5 -20 years
Technology
Readiness
Levels
Product in Service
Return on Investment
TRL 4- TRL6
(Technology evaluated
and qualified)
TRL 8 (System
test , launch
and operation)
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 12
ESA UNCLASSIFIED – For Official Use
12
Outline
1. European Space Agency
2. ESA technology budgets, procurement process
3. ESA microelectronics teams , activity overview
4. ASIC/FPGA in space: where, special concerns
5. Radiation effects, mitigation techniques
6. ASIC/FPGA technologies in use / development
7. Next Generation technology developments
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 13
ESA UNCLASSIFIED – For Official Use
ESA groups involved in ASIC & FPGA
Microelectronics
Section, TEC-EDM
LAUNCHERS
HUMAN SPACEFLIGHT
PFL
NAVIGATION
HSO
NAV
TELECOM
TEC
SCIENCE
Departments
EARTH OBSERVATION
DIRECTORATES
Components Technology +
Space Environment & Effects
Space Evaluation & Rad Effects
ESA strategy ASIC & FPGA for space
| A. Fernandez-Leon
/ B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 14
Section,
TEC-EEE
Sections. TEC-QTC, QEC
ESA UNCLASSIFIED – For Official Use
ESA groups involved in EEE components
Directorate of Technical and Quality Management (471 staff)
-
Electrical Engineering Department
-
-
-
Microelectronics Section – Agustin Fernandez Leon
-
Payload & Data Processing Section – Martin Suess
-
On-board computers Data Handling Section – Giorgio Magistrati
Processors
RF IC, MMICs,
GaN…
- Other divisions: Control Systems, Electromagnetics & Space Environment, RF Payload
Systems, Power & Energy conversion, etc
IC devices,
technologies
&
Product Assurance and Safety Department
qualification
- Materials and Components Technology Division – Mikko Nikulainen
(custom,
passives,
Components Technology Section – Laurent Marchand
detectors, MEMS)
Component Space Evaluation and Radiation Effects Section- Ali Zadeh
-
-
Data Systems Division – Philippe Armbruster
ASIC, FPGA
design and
technologies
Other divisions: Quality management, Standards, etc
Mechanical Engineering Department
-
Opto-electronics Section – E. Armandillo
Radiation effects
and tests,
Materials &
Components lab
Opto-electronics
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 15
ESA UNCLASSIFIED – For Official Use
European Space Technology Harmonisation Technical Dossier
MICROELECTRONICS: ASIC and FPGA
V2.2a Jan 2012
https://harmostrat.esa.int/dmsapp/getfile?proj_id=2&docno=0002559&docrev=2.2a2
https://harmostrat.esa.int/dmsapp/getfile?proj_id=2&docno=0002559&docrev=2
CAD tools
.2a2
Covered in dossier
IC Design Methodology
(from specs to prototype/ FM tests)
IC Design
House
(ASIC , FPGA)
Lightly covered
IP Cores
Rad Hard ASIC Libraries
or
Not covered
Space specific design requirements
(radiation & reliability hardening
techniques)
FPGA
Design Kit
Silicon Wafer
ASIC foundry
Packaging
technology
ASIC Assembly &
Test House
Memories
Space specific test requirements
(ESCC)
Evaluation and Qualification test houses
(electrical, mechanical, thermal, radiation, life
time)
IC power supply
PCB technology
Programmed Proprietary
ASICs
FPGAs
Standard
ASICs
ADC
and
DACs
Micro
processors
Micro
controllers
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 16
ESA UNCLASSIFIED – For Official Use
DSP
Proposed Development approach
The proposed roadmaps have been grouped into 6 AIMs, for simplicity:
AIM A Digital ASIC Technologies
AIM B ASIC/FPGA Design Methodology & IP Cores
AIM C Analogue and mixed-signal ASICs, ADC/DAC
AIM D FPGA
AIM E Microprocessors, Standard and proprietary ASICs
AIM F ASIC/FPGA Evaluation , Qualification, packaging, memories
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 17
ESA UNCLASSIFIED – For Official Use
Typical ASIC / FPGA technology activities
50-250K€ small studies, tools, IP Cores (~1yr)
500K€ ASIC design & prototype (1-2yrs)
500-1000K€ new ASIC / FPGA technology + radiation tests,
…(2-4yrs)
ASIC/FPGA techno developments consume all budget lines.
Very fragmented: TRP, GSTP and ECI. Occasionally ARTES, ITI,
…. EU FP7 and other Space Agencies (France, Germany) in
parallel / complement
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 18
ESA UNCLASSIFIED – For Official Use
Budget (K€) spent (2007-2012) and proposed (2013-2015),
in ASIC/FPGA activities
Breakdown per ESA programme Approved
TRP 15650
GSTP 1000
ARTES 500
OTHER 24515
Addition
al
2500
1600
2000
5700
TOTAL 41665 11800
Other:
•Incentive Schemes
(Greek, Portugal)
•ECI
•ESA corporate (labs)
•CNES roadmaps
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 19
ESA UNCLASSIFIED – For Official Use
Budget (K€) spent (2007-2012) and proposed (2013-2015),
in ASIC/FPGA activities
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 20
ESA UNCLASSIFIED – For Official Use
Outline
1. European Space Agency
2. ESA technology budgets, procurement process
3. ESA microelectronics teams , activity overview
4. ASIC/FPGA in space: where, special concerns
5. Radiation effects, mitigation techniques
6. ASIC/FPGA technologies in use / development
7. Next Generation technology developments
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 21
ESA UNCLASSIFIED – For Official Use
Spacecraft types
Space Station
ISS
Space Probe
Voyager
Transfer Vehicle
ATV
Satellite
Hubble Space Telescope
Space Suit
Mars Rover
Curiosity
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 22
ESA UNCLASSIFIED – For Official Use
Launcher
Ariane 5
Spacecraft Sub-Systems
PLATFORM
Structures
Power
Thermal Control
Attitude Control
Guidance
Command and Data Handling
Propulsion
Harness
PAYLOAD Instruments
Life Support
Launcher
Ground Segment
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 23
ESA UNCLASSIFIED – For Official Use
ASICs and FPGAs in space:
what are they used for?
Contain CONTROL and DATA PROCESSING functions, most of the time
CRITICAL for the PAYLOAD and the PLATFORM.
High speed point-to-point SpaceWire
routers
Intelligent remote terminal controllers
Co-processors,
DSP functions,
multichannel space and time mux,
De-modulation in transponders
Autocorrelators,
DAC and ADC broadband low power
converters
32bit Sparc Microprocessors
Telecommand decoding and
telemmetry encoding
CCSDS image compression
System-on-Chip hosting sparc
microprocessor, TMTC, data bus
bridges, etc.
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 24
ESA UNCLASSIFIED – For Official Use
ASICs and FPGAs in space: in what quantities?
Used in large (increasing) quantities
in both PLATFORM avionics and PLAYLOAD instruments
One recent example: SENTINEL 2
IC type
where
quantity
ASIC
P/F
59
ASIC
P/L
0
FPGA
P/F
112
FPGA
P/L
37
uP
P/F
21
uP
P/L
0
Std ASIC
P/F
10
Std ASIC
P/L
0
TOTAL: 249 high complexity integrated circuits in Sentinel-2
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 25
ESA UNCLASSIFIED – For Official Use
ASICs and FPGAs in space: in what quantities?
Used in large (increasing) quantities
in both PLATFORM avionics and PLAYLOAD instruments
450
Number of high complexity (>40pins) ASIC and FPGAs in recent ESA
missions
400
Number of parts
350
300
250
200
ASIC
FPGA
150
100
50
0
1997
Ariane5
2004
Rosetta
2005
VenusX
2009
GOCE
2010
Hylas
2011
2012
Galileo Proba2
IOV
Launch date - mission name
2012
Vega
2013
Sentinel2
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 26
ESA UNCLASSIFIED – For Official Use
2014
BepiC
Spacecraft Design
Mass
Volume
Power
Cost
Performance
RELIABILITY
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 27
ESA UNCLASSIFIED – For Official Use
AVIC
2012 - Oct
Boris Glass
27
Repairs in Space
• Normally not possible
• Extremely costly
• Example for successful
repair and maintenance in Space:
Hubble Space Telescope
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 28
ESA UNCLASSIFIED – For Official Use
ASICs and FPGAs in space: why can they fail?
1.Designer mistake
a.
Some nominal or corner cases never simulated, etc.
2.Manufacturing problem or error
a.
Silicon wafer defects
b.
badly calibrated machine
c.
operator error
d.
poor, insufficient error screening, etc.
3.System environment
a.
out-of-spec use (wrong bias, pin load, clock…)
b.
signal integrity problems at PCB, etc.
4.Aging effects – technology wear-out
a.
Electro migration
b.
Channel hot carriers
c.
Negative bias temperature instability (NBTI), etc, etc.
5.Space environment effects
a.
Vibration, mechanical shock (bonding, solder points failures)
b.
Extreme temperatures
c.
Contamination effects
d.
Radiation effects
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 29
ESA UNCLASSIFIED – For Official Use
ASICs and FPGAs in space:
built to last and endure
Life times of 20 years
-55°C to 125°C, extreme thermal cycles
Total ionising doses of 100Krad to Mrads,
Heavy ions, charged particles hits
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 30
ESA UNCLASSIFIED – For Official Use
Outline
1. European Space Agency
2. ESA technology budgets, procurement process
3. ESA microelectronics teams , activity overview
4. ASIC/FPGA in space: where, special concerns
5. Radiation effects, mitigation techniques
6. ASIC/FPGA technologies in use
7. Next Generation technology developments
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 31
ESA UNCLASSIFIED – For Official Use
Radiation Sources
1. Solar Flares
Sudden release of magnetic energy
2. Solar Energetic Particles
Short duration bursts (hours to days)
3. Solar Wind
Expanding from Sun’s outer atmospherer
4. Galactic Cosmic Rays
High Energy highly penetrating charged
particles from outside the solar system.
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 32
ESA UNCLASSIFIED – For Official Use
Trapped radiation: the Van Allen Belts
• Discovered during first space missions.
• Electrons and protons trapped in Earth Magnetic field (Lorentz force)
INNER BELT:
-- Mostly energetic protons up to
~400 MeV
– Product of Cosmic-Ray Neutron
Decay
– South Atlantic Anomaly (SAA)
– ISS and LEO orbits
OUTER BELT:
-- Mostly energetic electrons up to 7
MeV;
– affected by storms and solar flares
– GEO and Navigation (Galileo, GPS)
orbits
-- highly elliptic orbits (XMM-Newton,
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN
| 19/03/2013
| Slide
INTEGRAL,
Proba
3).33
ESA UNCLASSIFIED – For Official Use
Why are radiation effects in ASICs
and FPGAs a concern?
unprotected
+
can be
- temporary or permanent IC
malfunctions
- risk of mission failure or loss
- on-board IC replacement or
repair not an option!
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 34
ESA UNCLASSIFIED – For Official Use
i ng
Radiation propagat
EFFECTS
effects in
semiconductor
elements
effects in
basic
analogue
and digital
cells
failing
devices,
components
failing
units, subsystems
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 35
ESA UNCLASSIFIED – For Official Use
failing
onboard
experiments,
spacecrafts!!
Radiation Effects in semiconductor devices
Terrestrial, Nuclear energy,
Atmospheric (secondary particles)
X-rays
γ-rays
Electromagnetic radiation
Thermal
Neutrons
TOTAL IONISING DOSE
EFFECTS
♦ effects in
semiconductor
elements
→effects in
basic
analogue
and digital
cells
♦Creation of electron-hole pairs
♦Charge build-up, excitation, transport
♦Charge trapped in oxide and MOS
junctions
→Threshold voltage negative shift in
n-channel
→Threshold voltage shift in parasitic
transistors in bulk or thick epi layers
→Reduction of mobility in channel
conductance and transconductance
→Increase of standby / off-state /
leakage current
→changes in circuit parameters:
operating point, gain, impedance, drive
Galactic cosmic rays , Solar particles
Trapped particles in Van Allen Belts
Electrons
Protons
DISPLACEMENT DAMAGE
EFFECTS
♦Atomic dislocation, nuclear
displacement in lattice
♦Reduction in mobility
♦Reduction in carrier concentration
♦Increase in dangling bonds / free
radicals
♦Increased defect concentration
♦“rapid annealing” of minority carrier
lifetime
♦More defects, accelerated aging
(shorter life time)
→changes in circuit parameters:
operating point, gain, impedance, drive
α-rays
Heavy
ions
High energy photons
SINGLE EVENT
EFFECTS
♦Local Ionisation (volume effects)
Single Event Latch-Up (SEL)
activation of parasitic npnp/pnpn structures
causing anomalous switching behaviour of
main transistor and large draw currents.
Possible permanent failure.
Single Event Upset (SEU) temporary
“bit-flip” in memory element caused by
internal charge deposition
Single Event Transient (SET)
transient current or voltage spike. If
propagated and latched by memory element,
may result in “bit-flip”
Single Hard Errors (SHE) such as
gate/dielectric rupture, burn-out, in high V
junctions transversed by heavy ions
→
→
→
→
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 36
ESA UNCLASSIFIED – For Official Use
Rad Effects in ASICs and FPGAs:
Countermeasures
How to classify them?
Power cycling
WHO implements them?
At which LEVEL are they applied?
- system HW and SW designer
- system (PCB, software, case)
- IC designer (IC Design Kit user)
- IC architecture (netlist)
- IC design (CAD) tools developer
Al Shielding
- IC library / Design Kit / layout designer
- Foundry process & manufacturing engineer
D3
D
D1
D2
FF1
FF2
FF3
TMR, EDAC,
parity, time
redundancy
clk
Q2
scrubbing, TMR, current
limiters
Enclosed
transistors
, hard FF,
hard clock
trees
- logic cell, layout level (libraries,
reset/clock lines)
- foundry process (wafer
substrates, conductive, dielectric
and isolating materials and
sizes)
SOI, epi,
thin OX,
wells, STI,
guardbands
Q1
Q3
Majority
Voter
Q
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 37
ESA UNCLASSIFIED – For Official Use
Radiation Hardened by Design (RHbD) of
memory cells
Examples of European ASIC libraries which include RHbD
memory cells
 ATMEL MH1RT (350 nm), ATC18RHA (180 nm) & 150nmSOI (under
development)
http://www.atmel.com
 DARE (Design Against Radiation Effects) library for UMC 180 nm and 90 nm
(under development), IMEC(B)
http://microelectronics.esa.int/mpd2010/day1/MPD-IMEC-DARE-30March2010.pdf
 ST Microelectronics library for 65 nm (under development)
http://microelectronics.esa.int/mpd2010/day2/DSM65nm.pdf
 Xfab 180nm & IHP 130nm rad hard libs under development with DRL/TESAT
and Thales ETCA/IMEC
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 38
ESA UNCLASSIFIED – For Official Use
Radiation Hardened by Design (RHbD) of
memory cells
Other examples of ASIC libraries which include RHbD
memory cells
 Ramon Chips library for 180 nm Tower Semiconductors (130 nm under
development)
http://nepp.nasa.gov/mapld_2008/presentations/i/05%20%20Ginosar_Ran_mapld08_pres_1.pdf
 Aeroflex (600, 250, 130, 90 nm) – http://www.aeroflex.com/RadHardASIC
 Honeywell 90nm
 HIREC/JAXA - Fujitsu 0.18, OKI 0.15 SOI (NSREC2005)
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 39
ESA UNCLASSIFIED – For Official Use
Outline
1. European Space Agency
2. ESA technology budgets, procurement process
3. ESA microelectronics teams , activity overview
4. ASIC/FPGA in space: where, special concerns
5. Radiation effects, mitigation techniques
6. ASIC/FPGA technologies in use / development
7. Next Generation technology developments
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 40
ESA UNCLASSIFIED – For Official Use
rad hard ASIC in use / development (1/2)
ASIC Rad Hard libraries based on commercial processes
vendor
Lib name
MG2RT MH1RT
0.35µm
ATC18RHA
0.18µm
RH-CMOS65LP
65nm
DARE
(design against rad effects)
Techno node
0.5µm
180nm, 90nm
Library developer
ATMEL (F), co-funded by ESA
and CNES
STM(F,I) co-funded by ESA
and CNES
IMEC(B) funded by ESA
Semiconductor Manufacturer
MG2RT => MHS(F) Nantes,
STMicroelectronics (F)
Crolles
UMC (Taiwan)
rad tests on test vehicles for
terrestrial radiation (20062007). Deep Sub-micron 1st
phase launched end 2008.
Feasibility and definition of rad
hard lib done. Several test
vehicles manufactured and
tested, including High Speed
Serial Link. Alpha Design Kit
release April 2012. New ESA
contracts, to complete libraries
, CAD flow, HSSL IP: 2012-14
180nm Design Kit available
since 2004. Activities in
progress to add lib elements,
fix memory compilers, mixedsignal DK and consolidate
end-to-end space ASIC flow.
MH1RT & ATC18RHA =>
LFOUNDRY (F) Rousset
Status
MG2RT => Discontinued, 2010
last time buy
MH1RT => Discontinued, 2011
last time buy
ATC18RHA => stable, ESCC
certified
1st porting efforts to 90nm
concluded successfully in
2011. No funds to continue.
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 41
ESA UNCLASSIFIED – For Official Use
rad hard ASIC in use / development (2/2)
ASIC Rad Hard libraries based on commercial processes
Library developer
Lib name
SEL (LETth
Preliminary info
MG2RT, MH1RT, ATC18RHA
in
80,
>70,
90(T=125C)
RH-CMOS65LP (TBC)
DARE (design against rad
effects) 180nm
> 85 (Deep-N-Well)
> 55.9
TBD
No SETs up to LET of 55.9
MeV.cm2/mg and total fluence
MeV/mg/cm2)
SET
SEU (FF, SRAM, saturated
cross section for Heavy Ions
and Protons, cm2/bit
or
GEO/LEO SEU/bit/day,
CREME96, solar min, 100mm
Al)
more SETs with higher clock
frequencies, yet SEU are
predominant
MG2RT (0.5µm) =>
5E-7,
LETth = 15 MeV/mg/cm2
MH1RT (0.35µm) => 2.5E-7,
LETth = 15 MeV/mg/cm2
of 5E+6 #/cm2
1.3 - 2E-7 (HI, 25C-125C,
HFF)
1.2E-13 (protons, HFF)
7.3E-9 (GEO, HI, HFF)
3.6E-9 (GEO, protons, HFF)
6.2E-7 (LEO, protons, HFF)
LETth = 3.2 MeV/mg/cm2
No SEUs on RH-FF up to LET
of 55.9 MeV.cm2/mg and
fluence of 5E+6 #/cm2 (HI)
3E-5 (SRAM, HI)
ATC18RHA (0.18µm) => 4E-8
LETth = 30 MeV/mg/cm2
(e.g. <1E-5 errors/device/day
for GEO, for LEON2FT
microprocessor)
8.8 10-6 (RT-FF, HI)
3.4E-7 (std FF, GEO, HI+P)
1.44E-6 (std SRAM, GEO,
HI+P)
LETth = 3.2 MeV/mg/cm2
No SEUs up to 150 MeV and
fluence of 5E+11 p/cm2
(protons)
3.4 E-11 (SRAM, protons)
TID (Krad(Si))
300, 300 , 300 (tested)
100 tested, goal is 300
1000
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 42
ESA UNCLASSIFIED – For Official Use
rad hard FPGA solutions used in ESA missions
90%
Vendor
XILINX
Characteristics
Reprogrammability
Unlimited
MICROSEMI (ACTEL)
Anti-fuse based: One-timeprogrammable
ATMEL
Unlimited
FLASH-based: Unlimited
Technology
SRAM-based, .35-.065
Vendor HQ
USA
Anti-fuse based: (ONO and M2M),
0.8-0.15µm
FLASH-based: Floating gate 0.13
µm
USA
Wafers fabricated in
TSMC, UMC (Taiwan), IBM (USA)
MEC (Japan), UMC (Taiwan)
Assembly and Test
Asia & USA
Kyocera, NTK(Japan), BAE(USA)
Hardened SRAM-based, .35, .18
USA
LFoundry Rousset (France), Lapis
(Japan)
E2V (Grenoble, France),
Atmel (Nantes, France)
Virtex4: No TID, SEL effects;
No TID, SEL effects; Rad-hard anti- No TID, SEL effects ; Rad hardened
configuration logic is SEU sensitive fuse
SRAM, CMOS libraries
Radiation Hardness
Space Qualification levels
Approx Max Capacity (in
ASIC equivalent gates)
ITAR restrictions
Virtex5-SIRF: No TID, SEL effects ;
FLASH-based: Low TID effects. SEL 450Kgates: No TID, SEL effects ;
Rad hardened SRAM, CMOS
Rad hardened SRAM, SOI libraries
at high speed (tbc);
libraries
QML-Q/V
Anti-fuse based: QML-Q, QML-V ,
E-flow
not qualified: non-hermetic >1500
FLASH-based: tbc
pin packages.
1-2Mgates
32-72-250-500Kgates
Use of TMR will result in 2/3 less
gates approx.
yes
yes
QML-Q/V. ESCC qualification
pursued
40Kgates
280Kgates (2011)
450Kgates (2013)
no
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 43
ESA UNCLASSIFIED – For Official Use
Radiation Resilience Space FPGAs
vendor
Device type
datasheet
QPro™
Virtex™-II
Virtex-5QV
RTproASIC3
RTAX-S/SL
AT40KEL040
TID (Krads(Si))
200
>1000
>100; >45 if
reprogramming
300
300
SEL
> 160
>125
>64
> 117
80
GEO upsets <
1.5E-6 per device
day (with TMR+
SRAM scrubbing)
Conf. bits 4.85
Upsets/Device/Ye
ar ; SEFI static
9,930 U/D/Y
BlockRAM ~2.5E11 U/D/D ;
dynamic blocks
~2.7E-4 U/b/day
2E-7 cm2 per flipflop; 4E-8 cm2 per
SRAM memory
bit; none for
FLASH
< 1E-10 WorstCase GEO
2.5E-8 (*)
2.5E-7 (**)
Very low
>96 (FLASH),
>6(FF),
>1(SRAM)
>37
16 (*)
15 (**)
(MeV/mg/cm2)
SEU sat cross
section
(cm2/bit)
Or
GEO
(Errors/BitDay)
SEU LETth
(MeV/mg/cm2)
2E-6 cm2 per
No Anomalies up
global
to 150
MHz
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM
| visitclock
to CERN | 19/03/2013
| Slide
44
network, per IO
ESA UNCLASSIFIED – For Official Use
bank, low LETth
SET
31 May 2010
IV WERICE
44
As MH1RT ASICs
Rad-Hard FPGA Capacity Overview
NG-FPGA
(65nm)
AT450F (0.15
um SOI)
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 45
ESA UNCLASSIFIED – For Official Use
Outline
1. European Space Agency
2. ESA technology budgets, procurement process
3. ESA microelectronics teams , activity overview
4. ASIC/FPGA in space: where, special concerns
5. Radiation effects, mitigation techniques
6. ASIC/FPGA technologies in use / development
7. Next Generation technology developments:
a.
DSM (65nm)
b.
NG-FPGA
c.
Mixed-signal ASIC & DARE
d.
NG-Microprocessor
e.
NG-DSP
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 46
ESA UNCLASSIFIED – For Official Use
Deep Sub Micron (DSM)
Why:
•
The lack of space qualified DSM (65nm) technologies in Europe is leading to
performance limitations and increasing the procurement risks for navigation/
telecommunication satellite applications.
Criticality:
•
European space primes require unrestricted access to space qualified advanced
digital technologies (ITAR free) to compete in the digital telecom payload
market.
Objective by 2015:
•
To develop and maintain a supply of space qualified advanced digital
technologies based on the 65nm process starting with:
•
DSM radiation-hardened ASIC libraries.
•
High speed serial links (HSSLs) between components.
Achievements:
•
Feasibility, ASIC library definition and first 65nm (STMicroelectronics) test
vehicles completed in the context of KIPSAT Phase 1.
•
ASIC library consolidation and release to 1st alpha customers in KIPSAT Phase
2 (TRP, ECI 3, GSTP funding) and LibEval (CNES).
What still needs to be done:
•
ESCC Qualification of the 65nm Process and associated product lines (HSSL)
(No funding identified).
•
Note : Parallel development of flip chip high pin count packages is required for
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 47
many devices such as telecom ASICs, NG FPGA, Microprocessor and DSP that
ESArely
UNCLASSIFIED
For DSM.
Official Use
as well –on
Deep Submicron ASIC:
“KIPSAT” (ESA)+ “LibEval” (CNES)
space ASIC library/DK (Rad hard) with STMicroelectronics(F) CMOS
65nm-LP
15 seq, 58 comb, memory rad hardened cells (SEU rate improved by ÷80 to ÷500)
high speed serial link IP rad hardened (6.25 Gbps , BER<10 -14)
PLL (input 20-200Mz, output 200-1200MHz)
Total Ionising Dose characterised up to 300Krads, Single Event Latch-up free up to
60MeV LET
20 years (extended) lifetime models at Tjmax 110°C
Multiple test vehicles developed and under test
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 48
ESA UNCLASSIFIED – For Official Use
ST 65nm test vehicles already characterised
ESA-CNES contracts
TC1 (rad hard library):
TC2 (Rad-hard 1,2Ghz PLL + I/O):
TC3 (high speed serial link / HSSL):
• SKYROB65 ALLCELL blocks
• SKYROB65/CORE65 ROs
• FF shifters SKYROB65LP
• SRAM compilers
• Application digital blocks
• high performance multiphase hardened PLL
covering frequency range from
50MHz … 1.2 GHz (6 phases)
• special IOs
• cold spare CMOS
• cold spare LVDS
• Signal
• I2C
• Quatuor / 4 x 6.25 Gbps
TC4 (commercial library - CORELIB):
• commercial library full set (~ 1000 cells)
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 49
ESA UNCLASSIFIED – For Official Use
ST 65nm commercial process
•
•
•
65nm-LP CMOS from ST France : European technology, ITAR free
65nm CMOS commercially qualified in 2007
65nm CMOS Core Process :
– Dual / Triple Gate Oxides
– Dual / Triple Threshold Voltages for MOS Transistors
– 7-9 Full Copper Dual Interconnect Levels
– Low K
•
performances:
– 750 kgates/mm2
– 2GHz stdcells
– 5.7nW/(MHz x gates)
– 1.25-7.5GBit/s HSSL modules
 ST Rad Hard offer based on CMOS 65nm-LP commercial process
 Reliability and Radiation maximisation performed at design stages
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 50
ESA UNCLASSIFIED – For Official Use
Radiation Hard FPGA
(Field Programmable Gate Array)
Why :
• FPGAs offer shorter development times ,simpler, less expensive design and
manufacturing phases than Application Specific Integrated Circuits (ASICs) .
• Almost 100% of high performance FPGAs are ITAR controlled devices (Microsemi,
XILINX).
Criticality:
•
FPGAs are required in all electronic units offering digital functionality across ESA
missions in Science, Exploration, Earth Observation, Telecom and Navigation.
(Identified on the EC-ESA-EDA Urgent Action List )
Objective by 2017:
•
Development and qualification of a European product line of radiation hard
FPGAs without export restrictions.
Achievements:
•
•
•
European space qualified low gate capacity (40K, 280K) FPGAs. (CNES, ECI 3)
Development and qualification of a European medium gate capacity FPGAs
(450Kgate) on SOI process (rad hard by nature),(CNES, ECI 3).
Development started (2013) on a Large FPGA prototype with increased
logic capacity and performance.(>2Mgate) (TRP, ECI 3, CNES).
What still needs to be done:
•
•
ESCC space qualification 450Kgate FPGA (funding established in ECI 3).
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 51
Rad hard design of the large FPGA and ESCC qualification (no funding identified).
ESA UNCLASSIFIED – For Official Use
51
FPGA: “MUSE”
Microsemi
Xilinx
Atmel MUSE
XQR4VLX200
XQR5VFX130
POLYMNIE
CLIO
130 nm, anti
65 nm flash
fuse
90 nm
65 nm
65 nm
65 nm
Availability
Y
2013
Y
2012
2014
2016
Reprogramming
N
Y & NV
Y
Y
Y
Y
RHBD
Y
Y
N
Y
Y
Y
LUTs
40,320
155
(x inputs)
-4
-4
200,448
120
124.416
124.416
DFFs
40,320
190
178,176
120
124.416
124.416
Memory
540Kb
5.5M
6Mb
12Mb
5.8Mb
5.8Mb
588
96
320
>324
>324
(18x18)
(18x18)
(25x18)
(24x24)
(24x24)
840
644
960
836
620
620
SerDes
N
Y
N
Y
(TBD)
Y
Hermetic package
Y
Y
N
N
Y
Y
Device
RTAX4000
Process node
DSP
(multipliers)
I/O (single
Ended)
N
RT4P-16M
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 52
ESA UNCLASSIFIED – For Official Use
Next Generation MicroProcessor
(NGMP)
Why:
• To satisfy the high data processing power requirements (> 400MIPS) of, mostly,
(Earth Observation, Science and Exploration) future missions where the present
state of the art 100MIPS processors fall short of processing power.
Criticality:
• Recent ESA missions (e.g. GAIA) had to turn to ITAR solutions where on-board high
processing power was needed. Several European RoundTables (2006, 2010) to
discuss requirements for the Next Generation multipurpose microprocessor for future
SCI/EO payloads.
Objective by 2016:
• Development and Commercialization as a standard product (DSM process) of a space
qualified rad-hard Next Generation Microprocessor quad-core LEON4FT , L2 cache,
high demand space I/O i/fs , performance target 1.7 DMIPS/MHz, 0.6 Wheatstone
MFLOPS/MHz
Achievements:
• Specs and RTL design stable, several prototypes in Xilinx(65nm) and eASIC (45nm
FPGA-like), also development boards with functional prototypes (TRP)
What still needs to be done:
• Detailed design to be mapped (synthesised) with space rad hard DSM technology.
ST65nm is baseline, but there is bottle neck with 1st alpha customers. ASIC
prototyping and validation. (1M€ TRP on hold until technology is accessible).
• Engineering prototypes, flight models, and ASSP qualification and product
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide
commercialization (no funding identified).
ESA UNCLASSIFIED – For Official Use
53
53
Digital Signal Processor (DSP)
Why:
• High Performance Digital Signal Processors are more power efficient, and offer
higher performance for signal processing, and real-time applications than
general purpose processors (Earth Observation, Science and Exploration).
Criticality:
• The only existing European DSP is now completely out-dated , it provides less than
6% of the performance required today, consequently Europe is currently reliant
upon using a combination of FPGAs from USA (ITAR) and US sourced COTS
components with limited reliability and significant added mass / complexity / power
consumption.
Objective by 2016:
• Development and Commercialization as a standard ASIC product (DSM process) of a
space qualified rad-hard Digital Signal Processor with a performance of at least 1000
MFLOPS.
Achievements:
• European DSP tradeoff and definition study completed in 2012 (TRP)
• Low maturity R&D activity on floating point DSP IP on going (FP7)
What still needs to be done:
• Feasibility and design adaptation of the commercial IP (proposed to be launched
under ECI phase 4).
• Engineering prototypes, flight models, and ASSP qualification and product
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide
commercialization (no funding identified).
ESA UNCLASSIFIED – For Official Use
54
54
Mixed Signal
Why:
• Integration of digital and analogue functions into single devices, is an essential
contributor to the overall system miniaturization and performance increase (Earth
Observation, Science and exploration, Telecoms, Navigation).
• Single device mixed signal solutions improve the total functionality, performance ,
weight, volume and power consumption.
Criticality:
• Very heterogenic subject due the large spread of end user requirements , resulting in
the need to harmonise on a limited number of space qualified mixed signal processes.
(Identified on the EC-ESA-EDA Urgent Action List )
Objective by 2015/16:
• Qualification of European mixed signal technology process for Space Applications to
enable the development of new products (RF, Power, Telemetry, System on Chip…).
Achievements:
• Multiple European foundries/libraries already supplying mixed-signal ASICs for space:
AMS(A), X-FAB(UK,D), Infineon(D), IHP (D), ON-Semi(B), IMEC(B)-DAREUMC(Taiwan).
• Mixed signal process and new libraries evaluations on going with ATMEL-LFoundry
(CNES), IHP (ECI 3, DLR), IMEC-UMC-XFab (TRP,ARTES), TESAT-Xfab (DLR).
What still needs to be done:
• ESCC qualification of European mixed signal ASIC offers (start 2015 ). (no funding
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 55
identified).
ESA UNCLASSIFIED – For Official Use
55
DARE
Design Against Radiation Effects
Radiation Hardened Digital Standard Cell Libraries
Why:
Iccsb Core (1,8V)
SN003
45
SN087
SN089
40
SN122
35
SN138
30
I (mA)
• To guarantee the availability of portable and flexible radiation hardened digital
standard cell libraries for digital and mixed-signal applications.
SN125-REF
50
25
20
15
10
5
1000+168h
ageing
1000+24h
annealing
1000+168h
annealing
1000+12h
annealing
700
Dose (krad (Si))
1000
500
300
70
100
0
0
50
Objective by 2013:
• Provide a mature and reliable solution for platform and payload elements of
spacecrafts on Jovian missions. Demonstration of the maturity of the existing 180 nm
library for applications in very harsh radiation environments up to 1 Mrad TID(Si).
Achievements:
• The library has reached and demonstrated a high level of maturity. Two flight models
underwent the complete ECSS evaluation exercise.
What still needs to be done:
• Porting to Dare / Xfab 180 nm with HV and non-volatile RAM options
• Completion and characterization of DARE / UMC 90 nm library
• Amendments to the existing DARE / UMC 180 nm library, i.e. ‘light’ memory and core
cells without ELT for more common space environments up to 300 krad TID(Si).
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 56
ESA UNCLASSIFIED – For Official Use
56
Design Against Radiation Effects (DARE)
How and why got DARE started?
- late 90’s ASIC Foundries used for space components were scarce, expensive and were
discontinuing rad hard processes (ABB-HAFO & SOS).
The dependence on commercial, high volume ASIC processes was evident.
- 1999: First Technology Research Programme (TRP) funds were dedicated to Harden-byDesign ASIC libraries based on a commercial technology: UMC 180nm available on
Europractice MPW.
- 2000/2001After 1st proof of concept, new contracts launched to improve and add library
elements, and develop a 1st customer design (DROM).
- 2006/07 new contracts launched to do a second customer design (LEON3), including ESCC
evaluation and a maintenance contract, to start porting DARE to 90nm.
- Feb 2011 : DARE user day is
http://microelectronics.esa.int/dare/15-Feb-2011/
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 57
:
ESA UNCLASSIFIED – For Official Use
DARE+
• Core Library
• I/O Library
– Clock gating
•
•
•
•
•
•
– 3.3 V flavor
• RAM compiler
– Problem fix
–
Dual port
5V tolerant
Pull-up / pull-down
Improved LVDS
Improved ESD protection
Multi fan-out
IBIS Models
• PLL
– Full characterization
•
3.3 V -> 1.8 V voltage regulator
•
Demonstration ASIC (DSP)
• Re-characterization for
mixed-mode technology flavor
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 58
ESA UNCLASSIFIED – For Official Use
Test Vehicles (1/2)
(1)
Analogue Characterization
Contains active and passive devices for characterization,
including radiation tolerance
(2)
Digital Characterization
Contains all new or modified digital cell elements for (re-)
characterization,
including radiation tolerance
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 59
ESA UNCLASSIFIED – For Official Use
Test Vehicles (2/2)
(3)
DSP
- Xentium VLIW DSP Core
- Network on chip
- SpaceWire I/F w/ RMAP
- Bridges for external ADC/DAC
Demonstration of Development
Flow and tool compatibility
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 60
ESA UNCLASSIFIED – For Official Use
More info:
• European Space Technology Harmonisation Technical Dossier
MICROELECTRONICS: ASIC and FPGA V2.2a Jan 2012
https://harmostrat.esa.int/dmsapp/getfile?proj_id=2&docno=0002559&docrev=2.2a2
• ESA Microelectronics web page:
http://microelectronics.esa.int
ESCC:
ECSS:
ESCIES:
European Space Components Coordination https://spacecomponents.org
European Cooperation for Space Standardization http://www.ecss.nl/
European Space Components Information Exchange System https://escies.org/
ESA strategy ASIC & FPGA for space | A. Fernandez-Leon / B. Glass | TEC-EDM | visit to CERN | 19/03/2013 | Slide 61
ESA UNCLASSIFIED – For Official Use