A Power Regulation and Harmonic Current Elimination …
1
http://dx.doi.org/10.6113/JPE.2012.12.4.000
JPE 00-0-00
A Power Regulation and Harmonic Current
Elimination Approach of Parallel Multi-Inverter for
Supplying IPT Systems
Ruikun Mai†,Yong Li*, Liwen Lu* and Zhengyou He*
*†
Key Laboratory of Magnetic Suspension Technology and Maglev Vehicle Ministry of Education, Chengdu, China
Abstract
The single resonant inverter is widely employed in the typical Inductive Power Transfer (IPT) system to generate a high frequency
current in the primary side. However, the power capacity of a single resonant inverter is limited by the constraints of power
electronic devices and the cost, so that IPT systems may hardly meet the need of some high-power application requirements, such as
rail application. At the same time, the Total Harmonic Distortion (THD) may violate the EMI standard requirement with phase shift
control under light load condition. A power regulation approach with selective harmonic elimination is proposed based on parallel
multi-inverter to upgrade the power level of the IPT system and to suppress the THD under light load conditions by changing the
output voltage pulse width and the phase shift angle among parallel multi-inverters. The validity of the proposed control approach is
verified by using a 1412.3W prototype system, which achieves a maximum transfer efficiency of 90.602%. The output power level
can be dramatically improved with the same capacity of semiconductor and the distortion can be effectively suppressed under
various load conditions.
Key words: Inductive power transfer (IPT), Parallel multi-inverter, Power regulation, Selective harmonic elimination
R0 The reflected resistance of the secondary circuit.
NOMENCLATURE
E
Lk
DC input voltage of each H-bridge inverter.
Link inductance of each inverter.
n
The number of parallel inverters.
The output current of each H-bridge inverter.
ik
CP The compensation capacitance of the primary circuit.
ip
The current in the primary coil.
L p The inductance of the primary coil.
M
LS
The mutual inductance between the primary and the
secondary coils.
The inductance of the secondary coil.
CS The compensation capacitance of the secondary coil.
iS
The current in the secondary coil.
RL Equivalent load resistance.
U out The output voltage across the load.
Manuscript received Jan. 20, 2015; revised May 26, 2015
Recommended for publication by Associate Editor Hyung-Min Ryu.
†
Corresponding Author: mairk@swjtu.cn
Tel: +86-028-87602445, Southwest Jiaotong University
*Key Laboratory of Magnetic Suspension Technology and Maglev
Vehicle Ministry of Education, China
( A)* The conjugate operation of A.
I. INTRODUCTION
Inductive Power Transfer (IPT) systems are employed in
many ultra-clean, ultra-dirty environment as a power provider
to transfer power from primary side to secondary load side over
a moderate air-gap distance through magnetic coupling [1]-[9]
as per the applications’ requirement. Potential advantages of
IPT systems include immunity of affecting by ice, water, and
other chemicals, and environment friendly and maintenance
free. Besides, IPT systems have been adopted in a number of
applications including wireless charging of biomedical
implants [10], mining applications [11], under-water power
supply [12], electric vehicles [13]-[20], and railway
applications[21] due to its ease-of-use, and environmental
sustainability and as well as low lifecycle cost.
The high frequency AC power supply, resonance tank,
magnetic structures for inductive coupling, a pickup in the
secondary side and a rectifier load compose the basic of an IPT
system. The power supply produces an alternating electric
current in the primary coil, which, in turn, produces a
time-changing magnetic field. This variable magnetic field
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Journal of Power Electronics, Vol. 00, No. 0, July 2016
induces an electric current (producing a magnetic field) in the
secondary solenoid windings. The induced AC and voltage are
then rectified to Direct Current (DC) (in an inverter) to
recharge the battery or/and the load.
Unlike the consumer-electronic devices, some particular
applications, such as electric vehicles and rail transit systems,
are required to be fed with large amount of power. The
transferred power capacity of single inverter based IPT systems
[22]-[23] is restricted with the constraints of power electronic
devices, which may not be available in the market or be too
expansive to pursue.
In order to enhance the capacity of the resonant inverter
source, multiple inverters connected in parallel is proposed in
[24]-[27]. A parallel connected system for induction heating
based on high frequency LCL resonant inverter was described
in [24]. It requires no additional device for connecting inverters
in parallel, and the flexible power levels can be achieved by
choosing the number of parallel inverters. A phase-shift control
power regulation approach for multiple LLC resonant inverters
for induction heating was presented in [25] in order to regulate
the output power of the paralleled inverters by controlling the
phases among the inverters. A novel soft-switching
high-frequency resonant inverter comprised of twin half-bridge
connected in parallel was described in [26]. By employing a
new current phasor control of changing the phase shift angle
between two half-bridge inverter units, the output power can be
regulated continuously under the condition of wide-range
soft-switching operations. A parallel topology, which can
achieve high output power levels in a cost effective manner for
IPT systems with LCL-T resonant inverters, is proposed in [27]
with high reliability of functioning even that a faulty parallel
H-bridge inverter is electronically shut down.
However, the low order harmonic will dramatically degrade
the performance of some IPT systems, and unfortunately the
harmonic issue was not paid much attention to by the
aforementioned approaches. Safe levels of magnetic field
exposure is one of the major strict requirement that IPT
systems should meet and the public are intensively concerning
with. The maximum allowable field intensity at a given
frequency related to the track current in IPT systems with
operating frequency normally at 20-100kHz is provided by the
guard-line [28] and does not vary with frequency. At the same
time, the harmonics in the track current may increase the peak
value of the track current, especially in the light load condition,
which will in turn enhance the field intensity so as to violate
the standards. Therefore, harmonic reduction approach should
be paid careful attention to, so that the magnetic field intensity
can be maintained within the safe levels.
A novel parallel multi-inverter IPT system is presented in
this paper to upgrade the power level of IPT system. Phase
Shift Pulse Width Modulation (PS-PWM) method employed in
parallel inverters is proposed to realize the power regulation
and selective harmonic elimination. The explicit solutions
against phase shift angle and pulse width are given according
to the constraint of selective harmonic elimination equation and
required power avoiding solving non-liner transcendental
equation. Thus, the proposed method is suitable for real-time
applications, especially for IPT systems with high operation
frequency.
The remainder of this paper is organized as follows. The
basic principle of the parallel multi-inverter IPT system is
described in section II. An analysis of selective harmonic
elimination and the output power regulation is demonstrated by
using equivalent circuit of the proposed parallel multi-inverter
IPT system in the section II. The experimental verifications on
selective harmonic elimination, circulating current and wide
range power regulation are carried out by using the 1412.3W
20kHz prototype of an IPT system in section III. The
conclusion is finally drawn in Section IV.
II. BASIC PRINCIPLE OF PARALLEL
MULTI-INVERTER
A. Topology Analysis of Parallel Multi-Inverter
The schematic diagram of the proposed parallel
multi-inverter Series-Series (S-S) tuned IPT system with
voltage-fed H-bridge inverters is illustrated in Fig. 1. The
inverter is composed of N identical H-bridge inverters
connected in parallel. Each H-bridge inverter is connected in
series with a link inductor Ln .The resonant and compensation
capacitor CP is then connected in series with the parallel
H-bridge inverter. The synthesized current flowing through
the primary coil LP establishes magnetic coupling with the
secondary coil. The secondary circuit consists of the pick-up
coil LS , the compensation capacitor CS and the load RL .
The H-bridge inverters H1 - H n produce the output voltages
u1 - un which are controlled by changing the phase shift
angles and the pulse widths in the gate pulse signals.
Accordingly, the output power of each H-bridge inverters can
be regulated individually. Each inverter is equipped with a
protection device composed of two anti-series connected
semiconductor [29] in order to isolate the fault inverter from
the system.
A Power Regulation and Harmonic Current Elimination …
3
Z=
(k ) Z=
jk
ω L Z (k ) .
=
=
1(k ) Z N
n (k )
H1
Q11
Q12
·
i1
E1
The current of each branch and the track current can be
derived by
L1
u1
N
·
Q13
Protection
device 1
Q14
In (k ) =
Hk
Qk1
Qk2
·
ik
Ek
CP
·
Lk
uk
LP
·
Qk3
Qk4
Dr1
·
M iS
LS
·
Qn1
Qn2
·
(5)
=
I p (k )
·
Dr4
=
In (k )
∑
n =1
n =1
Dead time
Q12
Protection
device n
Q13
ωt
Q14
θL
The S-S tuned IPT system based on parallel
multi-inverter with protection devices
i1
(6)
Z (k ) + N ⋅ Z 0 (k )
un
Qn4
Fig. 1.
∑ U n (k )
N
Q11
·
Qn3
N
RL Uout
Ln
in
En
n =1
Z (k )2 + N ⋅ Z (k ) ⋅ Z 0 (k )
Dr3
Cr
Dr2
Protection
device k
Hn
CS
[ N ⋅ Z0 (k ) + Z (k )] ⋅ U n (k ) − Z 0 ⋅ ∑ U n (k )
i2
u1
P11
iP
in
u1(1)
0
ωt
P11=−θ∆−θL
P12 = θL−θ∆
ωt
i1
P12
CP
L1
Z1
L2
Ln
Z2
Q21
Zn
Z0 LP
u1
u2
u0
Q22
un
u2(1)
P21=θ∆−θL
P22=θL+θ∆
u2
Fig. 2.
The equivalent circuit of the IPT system with parallel
multi-inverter
Herein, In Fig. 2, the equivalent circuit is demonstrated and
its resonant angular frequency is defined by
=
ω
1
=
L0CP
1
LS CS
 N 1 
L0 =LP +  ∑

 n =1 Ln 
(1)
−1
(2)
For simplifying the analysis of the operating principle of
the proposed parallel multi-inverter system, letting Ln = L
and substituting (2) into (1), the operating angular frequency
of the inverter can be expressed by
ω=
where
1
( L N + LP ) CP
 U1 (k ) = I1 (k ) ⋅ Z1 (k ) + U 0 (k )




U N (k ) = IN (k ) ⋅ Z N (k ) + U 0 (k )

N
 U=
(k ) Z 0 (k ) ⋅ ∑ IN (k )
 0
n =1

Z 0 (k ) =+
R0 jkω LP + 1（jkωCP）
= R0 + jω ( NLP k 2 − L − NLP ) / ( Nk )
(3)
P21 0
x
Fig. 3.
ωt
Q24
2 θ∆
R0
Q23
i2
P22
ωt
ωt
The output voltage and current waveform of the
inverters.
Under resonant condition, according to [22], the reflected
impedance of the secondary circuit becomes purely resistive,
which can be derived by
R0 =
ω 2 M 2π 2
8 RL
(7)
B. Topology Analysis of Parallel Multi-Inverter
1) Waveform analysis of voltage source
The operating waveforms of the output voltages of the two
H-bridge inverters are two identical staircases with a phase
shift as depicted in Fig. 3. A coordinate system is constructed
accordingly. Line x is the symmetrical center line of the
staircase waveform. The origin is chosen at the point where
line x and the abscissa ( ωt ) intersect. To simplify notation,
the pulse width of the staircase is 2θ L , and the phase shift
(4)
angle between the two staircases is denoted by 2θ ∆ . TS is
and
the period of the fundamental voltage. Current changing rate
caused by two parallel inverters with opposite output voltages
will be twice as large as that with one inverter with zero
output as per the following equation.
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Journal of Power Electronics, Vol. 00, No. 0, July 2016
di u1 − u2
E
=
= ±
dt L1 + L2
L
(8)
Therefore, θ ∆ and θ L have to meet the restriction.
θ∆ + θ L ≤
π
(9)
(I) θ L = π 3 , (II) θ ∆ = π 6 . That is to say, when satisfying one
of the two conditions, the 3rd order harmonic current can be
eliminated theoretically with the same DC bus voltage.
Similarly，say α =0 ，applying (11) to (6), we have
2
The output voltage ui (t ) ( i = 1, 2 ) of each H-bridge
(10)
After applying Fourier Transformation to (10), the kth order
harmonic phasor is given by
2
=
U i (k )
TS
+
θ L + ( −1)i θ ∆
⋅TS
2π
∫
(
E ⋅e
− j 2π kx
TS
dx
−θ L + ( −1)i θ ∆
⋅TS
2π
θ L + ( −1)i θ ∆ +π
⋅TS
2π
∫
−E ⋅ e
− j 2π kx
TS
dx)
−θ L + ( −1)i θ ∆ +π
⋅TS
2π

− jk ( −1)i θ ∆
 2 2 E sin(kθ L ) ⋅ e
( k is an odd number )
=
kπ

( k is an even number )
0
(11)
2) Harmonic Analysis
The DC bus voltage is not guaranteed to be the same in
practice. Say that E2 =E , E1 =(1+α )E ，N=2，applying (11) to
(6), we have
2 2 E sin(kθ L )[(α + 2)cos(kθ ∆ ) + iα sin(kθ ∆ )]
I p (k ) =
kπ [ Z (k ) + 2 Z 0 (k )]
(12)
Let k = 1 , then
2 2 E sin(θ L )[(α + 2)cos(θ ∆ ) + iα sin(θ ∆ )]
IP (1) =
π ( jω L + 2 R0 )
(13)
Let k = 3 , then
2 2 E sin(3θ L )[(α + 2)cos(3θ ∆ ) + iα sin(3θ ∆ )]
IP (3) =
3π ( j 3ω L + 2 R0 )
(17)
2 2 E sin(θ L ) ⋅ e − jθ∆
I p′ (1) =
π R0
(18)
2 2 E sin(3θ L ) ⋅ e − j 3θ∆
I p′ (3) =
3π R0
(19)
Let k = 1 , then
inverter in one operation cycle is defined by
 E , ωt ∈ [−θ L ,θ L ] − (−1)i θ ∆


ui (t ) = − E , ωt ∈ [−θ L ,θ L ] − (−1)i θ ∆ + π
0, otherwise.

2 2 E sin(kθ L ) ⋅ e − jkθ∆
I p′ (k ) =
kπ R0
(14)
This research focuses mainly on eliminating the 3rd order
harmonics as low harmonics contribute more influence on the
load with the merit of resonant filter characteristics, that is to
say, letting the 3rd order harmonic phasor be equal to zero.
Thus, the harmonic elimination equation is provided by
2 2 E sin(3θ L )[(α + 2)cos(3θ ∆ ) + iα sin(3θ ∆ )]
= 0 (15)
kπ ( j 3ω L + 2 R0 )
When the DC bus voltages are the same, i.e. α =0 ，
obviously, the solution for (15) is given by
(16)
cos(3θ ∆ )sin(3θ L ) = 0
Two solutions are derived by (16), which are given as
Let k = 3 , then
Under condition (I), the 3rd order harmonic can be
eliminated even the DC bus voltage difference according to
(15). In the meantime, the amplitude of 3rd order harmonic is
a function against α under condition (II).
Here the detail performance analysis of the 3rd order
harmonic elimination is provided by setting α =5% and
α =10% .
The design specifications of the experimental setup are
listed in Table I. In the experimental evaluation, it is assumed
that the H-bridge inverters have the identical circuit
parameters and the same power rating.
TABLE. I
DESIGN SPECIFICATIONS AND CIRCUIT PARAMETERS OF IPT
PROTOTYPE
Parameters
Value
DC voltage of the H-bridge inverter E/V
150
Inverter frequency f/kHz
20
Inductance of the primary coil L P /uH
186.78
The link inductance of H 1 L 1 /uH
304.12
The link inductance of H 2 L 2 /uH
303.87
Resonant compensation capacitance of primary
219.54
circuit for two inverters C P /nF
Resonant compensation capacitance of primary
441.86
circuit for single inverter C’ P /nF
Mutual inductance of the primary and secondary
60.04
coils M/uH
Inductance of the secondary coil L S /uH
506.47
Resonant compensation capacitance of secondary
124.81
circuit C S /nF
10
Equivalent resistance of the load R L /Ω
It is obvious that the 3rd order harmonic amplitude of the
proposed algorithm is much smaller than that of single
inverter approach that just changes the pulse width as shown
in Fig. 4 with the configuration of Table I and (13) , (14) , (18)
and (19). The 3rd order harmonic’s amplitude (maximum
0.7A) of the single inverter approach is much larger than that
of the proposed algorithm (maximum 0.02A). And the
influence of DC bus voltage difference on the 3rd order
harmonic elimination is ignorable.
A Power Regulation and Harmonic Current Elimination …
3rd harm onic current amplitude
with the proposed approach /A
0.7
0.025
0.6
0.02
0.5
0.4
0.015
0.3
0.01
0.2
0.005
0.1
0
0
0
2
4
6
8
10
12
14
Fundamental current amplitude in the primary coil /A
3rd harmonic current amplitude with
0.8
the single inverter approach /A
α =10%
α =5%
α =0
single inverter approach
0.03
16
power of the IPT system Pout can be continuously regulated
from zero to 48E 2 RL π 4ω 2 M 2 with harmonic elimination
and
go
2 2 E cos(θ ∆ )sin(θ L )
IP (1) =
π R0
=
u1(1)
i1
u1
0
P11
ωt
P12
0
u3(1)
i3
0
P31
2θ∆+2θ∆1
Pout can be given by
36 E 2 RL
(23)
π 4ω 2 M 2
Similarly, by fixing θ L = π 3 , the range of θ ∆ will be
expressed by
π
(24)
6
Consequently, under this condition, the range of Pout
with harmonic elimination under various settings is provided
by
36 E 2 RL
≤ Pout ≤
48 E 2 RL
(25)
π ω M
π ω M
When more power is required, the inverters will generate
pulse width ( 2θ L ) more than 2π / 3 with the same phase to
4 2
2
4 2
2
increase the output power with the cost of disability of
harmonic elimination. By setting θ L = π and θ ∆ = 0 , the
output power will go up to
Pout =
P41= θ∆1+θ∆−θL
P42 = θ∆1+θ∆+θL
i4
P42
ωt
(22)
3
Substituting θ ∆ = π 6 into(21), the range of output power
0 ≤ θ∆ ≤
ωt
P32
u4(1)
P41 0
0 ≤ Pout ≤
P31= θ∆1−θ∆−θL
P32 = θ∆1−θ∆+θL
u4
be
0 ≤ θL ≤
ωt
P22
u3
π 4ω 2 M 2
When fixing θ ∆ = π 6 , the 3rd order harmonic will be
π
P21= −θ∆1+θ∆−θL
P22 = −θ∆1+θ∆+θL
i2
P21
64 E 2 RL cos 2 (θ ∆ )sin 2 (θ L )
eliminated. Under the restriction of (9), the range of θ L will
harmonic
P11= −θ∆1−θ∆−θL
P12 = −θ∆1−θ∆+θL
u2
2θ∆1
(21)
without
u2(1)
2 θ∆
ω 2 M 2π 2 IP (1) ⋅ ( IP (1) )
8 RL
64 E 2 RL π 4ω 2 M 2
θL
*
Pout =
to
C. Multi-Inverter Case Study
On the basis of two-inverter case study, another
two-inverter is employed to form a four-inverter base system
here. The output voltage waveforms are shown in Fig. 5.
(20)
According to [22], the output power of the IPT system can
be expressed by
up
elimination.
Fig. 4. The comparison of 3rd order harmonic current of the
primary coil current of two approaches
3) Power Regulation of IPT System
From (12), the fundamental phasor of the primary coil
current is denoted by
5
64 E 2 RL
(26)
π 4ω 2 M 2
By changing the value of θ L and/or θ ∆ , the output
Fig. 5.
The output voltage waveform of four-inverter approach
Similarly to (12), the Fourier Transformation of each
output voltage are described by
2


U1 (k ) = 
0

2

U 2 (k ) = 
0

2

U 3 (k ) = 
0

2


U 4 (k ) = 
0

2 E sin(kθ L ) ⋅ e
kπ
− jk [θ ∆ −θ ∆1]
( k is an even number )
2 E sin(kθ L ) ⋅ e
kπ
2 E sin(kθ L ) ⋅ e
kπ
( k is an odd number )
− jk [ −θ ∆ −θ ∆1]
( k is an even number )
− jk [θ ∆ +θ ∆1]
2 E sin(kθ L ) ⋅ e
kπ
( k is an odd number )
( k is an odd number )
( k is an even number )
− jk [ −θ ∆ +θ ∆1]
( k is an odd number )
( k is an even number )
(27)
where U1(k ) and U 2 (k ) are the output voltage of the first
two inverters, while U 3 (k ) and U 4 (k ) are that of the
others. 2θ ∆1 is the radian difference between the output
voltages of the two-inverter system as shown in Fig. 5. The
phasor of the primary coil current can be derived from (6).
6
Journal of Power Electronics, Vol. 00, No. 0, July 2016
8 2 E sin(kθ L ) ⋅ cos(kθ ∆ )cos(kθ ∆1 )
I p (k ) =
π [ Z (k ) + N ⋅ Z 0 (k )]
(28)
Of course, θ ∆1 can be simply set to zero to double the
output power compared to that of the two-inverter system.
Besides, as discussed before, as long as θ L and θ ∆ meet
the restriction of the 3rd order harmonic elimination, the
output current of four-inverter system will not exhibit the 3rd
order harmonic. With careful design, another order harmonic
can be eliminated as well. Taking the 5th order harmonic for
example, the harmonic elimination equation is given by
(29)
sin(5θ L ) ⋅ cos(5θ ∆ )cos(5θ ∆1 ) =
0
paper, it at less needs 2 N ′ inverters to eliminate N ′ orders of
harmonic.
D.Analysis of the circulating current
Take the two-inverter based model for example,
according to [30], the circulating current between the first and
the second H-bridge inverter is shown in Fig. 7 can be
expressed by
I (k ) − I2 (k )
Ic (k ) = 1
2
(30)
Normalized value(current over Imax)/p.u.
Combining (16) and considering the changing rate of the
branch current, the track current of proposed approach
against various settings is shown in Fig. 6.
1
⑤
Imax
0.87
④
0.75
③
0.58
0.55
②
①Fix θΔ=π/6 ,θΔ1=π/10 and
alter θL between [0,7π/30]
②Fix θL=7π/30 ,θΔ=π/6 and
alter θΔ1 between [0,π/10]
③Fix θΔ=π/6 ,θΔ1=0 and
alter θL between [7π/30,π/3]
①
⑤Fix θΔ=0 ,θΔ1=0 and
alter θL between [π/3,π/2]
00
π/10
π/6
7π/30
θ/rad
π/2
π/3
Fig. 6. Primary coil current response of proposed approach
against θ L , θ ∆ and θ ∆1
①Setting θ ∆ = π / 6 and θ ∆1 = π / 10 , let θ L change from
0 to 7π / 30 with the 3rd order and the 5th order harmonic
elimination.
② setting θ ∆ = π / 6 and θ L = 7π / 30 , let θ ∆1 go down
from π / 10 to 0 with the 3rd order harmonic elimination.
③ setting θ ∆ = π / 6 and θ ∆1 = 0 , let θ L
Fig. 7. The circulating current between two inverters.
Substituting (5) into (30), the fundamental circulating
current phasor can be expressed by
④Fix θL=π/3 ,θΔ1=0 and
alter θΔ between [0,π/6]
2 2 E sin(θ ∆ )sin(θ L )
Ic (1) =
πω L
From (31), the circulating current Ic (1) obviously relates
to the operating angular frequency ω , the link inductance of
the H-bridge inverter L , the DC voltage source E and the
phases θ L and θ ∆ . When satisfying the elimination
conditions ( θ ∆ = π 6 or θ L = π 3 ), the circulating current
phasor derived from (31) will be varying in the range of
0 ≤ Ic (1) ≤
change from
7π / 30 to π / 3 with the 3rd order harmonic elimination.
④ setting θ L = π / 3 and θ ∆1 = 0 , let θ ∆ go down from
π / 6 to 0 with the 3rd order harmonic elimination.
⑤setting θ ∆ = 0 and θ ∆1 = 0 , let θ L go up from π / 3 to
π / 2 without any harmonic elimination. The output power
increase to the maximum.
What needs to be clarified is that the number of parallel
inverters to be used is determined by the following factors.
1. The capacity ( Seach ) of each inverters should be a little
bit greater than (not just the same as) 1 / N
of
the power demand required by the load by considering the
circulating current flowing amongst inverters. N is the
number of the parallel inverters. Therefore, if the larger each
inverter’s capacity is, the less number of inverters is needed
with the same power required.
2. The number of the parallel inverters is also decided by
the number of harmonic to be eliminated. As discussed in this
(31)
6E
2πω L
(32)
Therefore, by choosing proper link inductors, the
circulating current between the two inverters will be
effectively controlled by enlarging the value of link
inductance.
E. Control diagram
The control block diagram is shown in Fig. 8. The
DC load voltage is sent to the primary side controller via
wireless data sender. The load voltage and the reference
voltage is treated as input to the PI controller to yield the
control parameters θ L and θ ∆ , which is used to generate
the pulse width for the H-bridge inverter.
If any inverter occurs a fault, its fault signal is sent to
controller to isolate this branch to make sure other parts of
the system work continuously, so that the reliability can be
improved dramatically. The inverters will not perform the
harmonic elimination strategy and work under the
condition that the output voltages of each inverter are
A Power Regulation and Harmonic Current Elimination …
7
controlled to be in phase with the same pulse width.
Fault signal
H-bridge #1
u1
5.6cm
Secondary
coil
Wireless U
out
data
receiver
Primary
coil
u2
Protection
device 2
Link
inductance L2
i2
Cr
RL
10cm
Uout
Pulse
H-bridge #2
Rectifier
Air
gap
Uout
Wireless
data
sender
DSP
25.5cm
Uout
+ U
- out
PI
31.1cm
θL
θ∆
24cm
Transmitter
i1
*
Pulse
Pulse
modulator
Protection
device 1
Link
inductance L1
Voltage
sensor
Fault signal
32cm
5.6cm
Fig. 8. The control block diagram
III. EXPERIMENTAL RESULTS
Power analyzer
Rectifier
LS
CS
DC source E
DC source E
Inductor L2
Inverter2 H2
Inverter1 H1
DSP
LP
CP
Inductor L1
Electronic load RL
Auxilary sourcr
Fig. 9. The exterior appearance of the proposed IPT prototype.
Fig. 10.
The primary and the secondary coils wound with Litz
wire.
B. Experimental results
To provide clear comparison of different operating
conditions, the experimental values of the output power, the
load consumption and the transmission efficiency of IPT
system against output power are given in Fig. 11 .
Input DC Power /W
1800
PDC1
PDC2
PDC
η1
η2
0.95
1600
0.9
1400
0.85
1200
1000
Alter θL′∈[0, π/2]
Zone1
Fix θ∆=π/6
Alter θL∈[0, π/3]
0.75
Zone2
Fix θL=π/3
Alter θ∆∈[0, π/6]
800
600
0.7
0.65
Zone3
Fix θ∆=0
Alter θL∈[π/3, π/2]
400
200
0
0.8
250
Fig. 11.
450
650
Efficiency
A. Prototype system
To validate the proposed approach, an experimental IPT
prototype was constructed in the laboratory settings with two
identical H-bridge inverters connected in parallel. The
prototype is designed to operate up to 1412.3W in the
experiment with the functionality of selective harmonic
elimination and power regulation by changing the output
voltage pulse width and phase shift angles.
The exterior appearance of the experimental setup is
portrayed in Fig. 9 and Fig. 10. The TMS320F28335 Digital
Signal Processing unit (DSP, Texas Instrument) are used to
generate the gate pulse signals for the semi-conductors. The
primary coil(L:32cm,W: 31.1cm) on the bottom and the
secondary coils (L:24cm,W:31.1cm) on the top are both with
the U-shape ferrite. The distance between the primary coil
and the secondary coil is about 10cm. The two coils are both
mounted to the acrylic board so as to attain mechanical
support. MOSFETs (AP80N30W) and the gate driver
(CONCEPT-2SC0108T2A0-17) are adopted by the H-Bridge
inverters. The DSP is employed as the controller of IPT
system to perform the functionality of control and protection,
etc.
The two H-bridge inverters are separately powered by two
isolated DC supplies, and the AC output of the two H-bridge
inverters are connected in parallel to provide transmitting
current in the primary coil compensated by a series capacitor.
An electronic load is employed as the secondary load
connected with the rectifier.
The experimental waveforms are measured and displayed
by Agilent MSO-X 4034A scope, which provides built-in
harmonic analysis. The efficiency of the system is analyzed
by YOKOGAW WT1800 power analyzer.
850
1050
Output Power Pout/W
1250
1450
0.6
0.55
0.5
The input power and the overall system efficiency
against the output power
It is clearly proven that the wide-range output power
regulation can be achieved by changing the phase shift angle
and pulse width of the proposed approach and by changing
the pulse width of the single inverter approach as shown in
Fig. 11. The output power of the two inverters are
approximately the same as each other (about half of that of
single inverter approach), even though they are not identical
to each other as there is a phase shift between them. As a
consequence, the circulating current exists between two
inverters so that the loss occurs and the efficiency decreases
as shown in Zone 1 and Zone 2. At Zone 3, as the output
power goes up, the overall efficiency of the proposed
approach increases up to 90.602% at output power of
1412.3W, which is nearly the same as that of single inverter
approach.
The THD distortion of the proposed algorithm is much
smaller than that of the single inverter approach and the 3rd
order harmonic of the proposed approach is dramatically
suppressed under various output power conditions as shown
in Fig. 12. Especially, in Zone 1 and Zone 2, the track current
THD of proposed approach is kept within 2%, while the THD
goes up as the proposed approach cannot eliminate the 3rd
order harmonic in Zone 3. The blue line (THD1) represents
8
Journal of Power Electronics, Vol. 00, No. 0, July 2016
0.12
THD1
THD2
Alter θL′∈[0, π /2]
0.1
THD
0.08
0.06
0.04
Zone1
Fix θ∆=π /6
Alter θL∈[0, π /3]
Zone2
Fix θL=π /3
Alter θ∆∈[0, π /6]
Zone3
Fix θ∆=0
Alter θL∈[π /3, π /2]
650
850
1050
Output Power Pout/W
(a)
5th harmonic
3rd harmonic
1250
Normalized RMS Harmonic Current
0.03
7th harmonic
0.04
0.03
0.02
Zone2
Fix θL=π /3
Alter θ∆∈[0, π /6]
0.01
250
450
650
850
1050
1250
1450
Output Power Pout/W
(b)
3rd harmonic
5th harmonic
7th harmonic
Zone3
Fix θ∆=0
Alter θL∈[π /3, π /2]
Zone2
Fix θL=π /3
Alter θ∆∈[0, π /6]
0.02
0.01
Zone1
Fix θ∆=π /6
Alter θL∈[0, π /3]
550
650
750
850
Output Power Pout/W
950
1050
1150
Zone3
Fix θ∆=0
Alter θL∈[π/3, π/2]
1000
800
Zone2
Fix θL=π/3
Alter θ∆∈[0, π/6]
Zone1
Fix θ∆=π/6
Alter θL∈[0, π/3]
600
400
0
450
0
π/6 0.6
π/3 1.2
θL and θ∆ /rad
π/2
1.8
Fig. 14. The output power against θ ∆ and θ L .
It is obvious that the 3rd order harmonic of the experiment
can be suppressed dramatically by the proposed algorithm
even with different DC bus voltages compared to that of
single inverter approach as shown in Fig. 13. The output
power of the experiment measured by prototype is provided
in Fig. 14. The output power can be continuously regulated
from almost 0W to 1400W by changing the value of θ L
and/or θ ∆ . After comparing the waveforms of the two
0.005
250
450
1200
0
0.025
0.015
350
200
0.01
0.03
single inverter
approach
proposed approach
0.02
1400
0
Normalized RMS Harmonic Current
Zone1
Fix θ∆=π /6
Alter θL∈[0, π /3]
1450
Output Power Pout/W
450
Alter θL′∈[0, π /2]
0.035
α =10%
Fig. 13. The comparison of normalized RMS 3rd order harmonic
current of the primary coil current of two approaches
0.05
250
α =5%
0.04
1600
250
α =0
Alter θL′∈[0, π /2]
0
0.02
0
single inverter approach
0.05
Normalized RMS 3rd Harmonic Current
the THD value of the single inverter approach and the red
line (THD2) represents that of the proposed algorithm. The
3rd order, 5th order and 7th order harmonics are suppressed
by the proposed algorithm in Zone 1 and Zone 2 but not in
Zone 3 as shown in Fig. 12(b) and (c).
650
850
1050
Output Power Pout/W
1250
1450
Fig. 12. The comparison of THD and normalized RMS of the
primary coil current of two approaches: (a) THD comparison of
two approaches, and (b) normalized RMS of the primary coil
current of the single inverter approach, and (c) normalized RMS
of the primary coil current of the proposed approach.
approaches, the harmonic is dramatically suppressed by the
proposed approach and the 3rd order harmonic is nearly
eliminated, which is coincide with the theoretical analysis.
The overall efficiency of the proposed approach is about
82.9% as shown in Fig. 15. When under the maximum output
power point(1412.3W), the waveforms of the current and the
voltage of IPT system as well as the overall
efficiency(90.602%) are shown in Fig. 16. more working
points are referred to Fig. 11.
A Power Regulation and Harmonic Current Elimination …
u(100V/div) ip(10A/div)
FFT of ip(100mA/div)
FFT of ip
9
u
ip
5th
0.53A
7th
3rd
0.09A
0.06A
u1
u2
ip
i1
Uout(30V/div) i1,i2(10A/div) iP(20A/div)
0.03A
7th
5th
3rd
0.05A
0.02A
t(20us/div)
(b)
(c)
Fig. 15. Measurement of the key system waveforms for two
approaches at P out = 388.4W (a) waveforms of output voltage ,
the primary track current and the harmonic analysis of the single
inverter approach. (a) waveforms of output voltage , the primary
track current and the harmonic analysis of the proposed approach
and (c) the overall efficiency of the proposed approach measured
by power analyzer.
u1
u1,u2(100V/div) i1,ip(10A/div)
FFT of ip(100mA/div)
FFT of ip
u2
ip
i1
5
th
7th
0.35A
3rd
0.12A
0.05A
t(20us/div)
(a)
(b)
Fig. 16.
Measurement of the key system waveforms for two
approaches at P out = 1412.3W(a) waveforms of output voltage ,
the primary track current and the harmonic analysis of the single
inverter approach. (a) waveforms of output voltage , the primary
track current and the harmonic analysis of the proposed approach
and (c) the overall efficiency of the proposed approach measured
by power analyzer.
Uout(20V/div) i1,i2(5A/div) iP(10A/div)
FFT of ip
18ms
17.5ms
Uout
70V
50V
50V
i1=12A
i1=16A
i1=12A
i2=8.5A
i2=11A
i2=8.5A
iP=19A
iP=26A
iP=19A
RL=10Ω
16ms
t(50ms/div)
(a)
RL=8Ω
RL=10Ω
17ms
50V
Uout
50V
50V
i1=11.2A
i1=11.2A
i1=11.2A
i2=7.4A
i2=7.4A
i2=7.4A
iP=8.8A
iP=8.8A
iP=8.8A
t(20ms/div)
(b)
Fig. 17. System response with step change (a) step change of
reference voltage from 50V to 70V and then back to 50V (b)
step change of load resistance from 8Ω to 10 Ω and then back to
8Ω
Uout(10V/div) i1,ip(10A/div) i2(5A/div)
u1,u2(100V/div) i1,ip(10A/div)
FFT of ip(100mA/div)
t(20us/div)
(a)
Uout
17ms
30V
30V
i1=7.3A
i1=11A
fault
i2=5.7A
0A
iP=11A
iP=11A
t(20ms/div)
Fig. 18. The waveforms when a fault occurred in H-bridge
inverter 2
10
Journal of Power Electronics, Vol. 00, No. 0, July 2016
The dynamic response is provided in Fig. 17. The
reference voltage of the load is change from 50 V to 70V and
then back to 50V as shown in Fig. 17(a). The response of the
proposed algorithm is fast and it takes about 18ms to reach
70V and 17.5ms back to 50V.
The load resistance change test is performed and the
dynamic response of proposed algorithm is given in Fig.
17(b). It takes 16ms for the proposed algorithm to converge
to 50V with load resistance change from 10Ω to 8Ω and
17ms with load resistance change from 8Ω to 10Ω.
The waveforms of the current and voltage of the IPT
system are shown in Fig. 18 with the operation of protection
device of inverter 2. At the beginning, the voltage of the load
at the secondary side is set to 30V. When a fault occurs in
inverter 2, inverter 2 is cut off by the protection device and
Inverter 1 is still continuously working. After 17ms, the load
voltage comes back to 30V despite of a voltage drop
happened. It is clear that the fault H-bridge inverter can be
removed by the proposed algorithm and the reliability of the
system is promoted by the proposed algorithm.
IV. CONCLUSIONS
The novel power regulation control approach with selective
harmonic elimination based on parallel multi-inverter for IPT
systems is proposed in this paper. The operating principle of
harmonic elimination and power regulation has been explained
and described in detail. By changing the output voltage pulse
width and the phase shift angle of the inverters, the 3rd order
harmonic current of the primary coil could be eliminated and
the IPT output power could be continuously regulated,
simultaneously. A 1412.3W experimental prototype is set up
and tested. The experimental results verified the performance
of the proposed control approach which is suitable for high
power IPT applications with various power requirements and
has output with a lower harmonic distortion under light load
conditions compared to one inverter approach. A protection
scheme is provided to improve the reliability of the proposed
system. The test results also show the output voltage can be
maintained to the desired value even with occurrence of a fault
which is removed by the protection device.9
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
ACKNOWLEDGMENT
This work was supported by The National Science Fund
for Distinguished Young Scholars (N0.51525702) ,Scientific
R&D Program of China Railway Corporation (2014J013-B)
and the Fundamental Research Funds for the Central
Universities(2682015CX021).
[13]
[14]
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11
Ruikun Mai was born in Guangdong, China,
in 1980. He received the B.Sc. and Ph.D.
degrees from the School of Electrical
Engineering in Southwest Jiaotong University,
Sichuan, China, in 2004 and 2010,
respectively. He was with AREVA T&D U.K.
Ltd. for two years from 2007 to 2009. He was
a research associate at The Hong Kong Polytechnic University
from 2010 to 2012. He is currently an associate professor with the
School of Electrical Engineering, Southwest Jiaotong University.
His research interest includes wireless power transfer and its
application in railway, the power system stability and control,
phasor estimator algorithm and its application in PMUs.
Yong Li was born in Chongqing, China, in
1990. He received his B.S. in Electrical
Engineering and Automation from Southwest
Jiaotong University (SWJTU), Chengdu,
China, in 2013, where he is currently
working toward a Ph.D. degree at the
School of Electrical Engineering. His
research interests include wireless power transfer, modular
multilevel converter supplying IPT systems for high applications.
Liwen Lu was born in Jiangsu, China, in 1990.
He received his B.S. in Electronics and
Information Engineering from Southwest
Jiaotong University (SWJTU), Chengdu, China,
in 2014, where he is currently working toward
the master degree. His research interests
include inductive power transfer and power
conversion in rail transit applications.
Zhengyou He was born in Sichuan, China, in
1970. He received his B.S. B.S. degree and M.
Sc. degree in computational mechanics from
Chongqing University, Chongqing, China, in
1992 and 1995, respectively. He received the
Ph.D. degree in electrical engineering from
Southwest Jiaotong University in 2001.
Currently, he is a professor in the same institute. His research
interests include signal process and information theory applied to
power system, and application of wavelet transforms in power
system.