A multi-band PLL based tuning circuitry for the super-regenerative IR-UWB receiver system Prakash.E.Thoppay*, Catherine Dehollain*, Michel J.Declercq* and Michael.M.Green+ *EPFL-EL, +Department of EECS, University of California, Irvine. Cluster 2 Abstract 1 The possibility of using the super-regenerative receiver architecture for ultra wide-band (UWB) reception was demostrated in . The core block in the super-regenerative receiver is an oscillator. One of the parameters which influence the selectivity of super-regenerative receiver is the center frequency of the oscillator. And thus, to maximize the selectivity and henceforth to increase the receiver sensitivity it is necessary that the super-regenerative receiver oscillator is tuned to the transmitter center frequency. In this poster, the implementation of a multi-band PLL to achieve the above purpose is shown. An integer-N type PLL architecture is designed and a multi-modulus counter is used as a divider to tune the oscillator for various bands. To reduce the average power consumption, the various blocks of the PLL are switched off once the oscillator is tuned to the desired center frequency. The PLL is implemented in a UMC 0.18um technology and the supply voltage is 1.5 V. Implementation details of the Integer-N PLL 2 The PLL consists of an oscillator, the divider, the PFD block, the charge-pump circutry and the low pass filter. An on-chip inductor is used as a resonant element for the core oscillator. The frequency selection is acheived by coarse and fine tuning. Once the desired oscillating frequency is known, corresponding capacitors are enabled and by varying the control voltage acorss the reverse bias diode fine tuning is achieved. The reference frequency (31.2 MHz) is chosen based on the specifications given in the WPAN standard. To tune the oscillator to 3.494 and 3.993 GHz the required division ratios are 112, 128 respectively. To achieve this division ratio, a fixed divider and a multi-modulus counter is used. The second order low pass filter is used in this PLL, the capacitor values are chosen to achieve a PLL bandwidth of 60 kHz. Since settling time is important in UWB application, the bandwidth is chosen relatively higher in comparison to other standard PLL. Results PFD 31.2 MHz VCO CP R1 C1 Core Oscillator C2 CP Var div MMC 7, 16 8 Fixed divider 3 Block diagram of the core oscillator tuning circuitry Chip microphotograph of the core oscillator tuning circuitry -15.89 dBm 3.49431062 GHz Ref Lvl -10 dBm VBW SWT 1 kHz 2 s Unit Typical Specifications: dBm 1 Technology Supply voltage Reference freqeuncy PLL bandwidth Frequencies A 1AP 10% of f Divider Specifications: Fixed divider MMC 15us Center 3.494310621 GHz Date: 3.FEB.2009 14:31:56 1 MHz/ Span 10 MHz Core oscillator output spectrum at 3.494 GHz Settling time behaviour of the core oscillator at 3.993 GHz CMOS 0.18um 1.5 V 31.2 MHz 60 kHz 3.494 GHz, 3.993 GHz CML logic and TSPC Digital logic Static current consumption Charge pump Divider VCO (Q=8 at 3.993 GHz) 370uA 4.7mA 3.2mA PLL order Low pass filter External, IInd order 4 Reference     “A 7.5 mA 500 MHz UWB receiver based on super-regenerative principle” , P.Thoppay et al, ESSCIRC 2008, pp 382-385. “A multi-band PLL based tuning circuitry for the super-regenerative IR-UWB receiver system” , P.Thoppay et al, To be presented at ICUWB 2009. “Noise analysis in super-regenerative receiver systems” , P.Thoppay et al, PRIME 2008, pp 189-192. “An automatic pulse alignment method for slope controlled super-regenerative receiver systems” , P.Thoppay et al, PRIME 2007, pp 125-128.