Series Parallel Switched Multilevel DC Link Inverter Fed Induction

Advance in Electronic and Electric Engineering.
ISSN 2231-1297, Volume 4, Number 4 (2014), pp. 327-332
© Research India Publications
Series Parallel Switched Multilevel DC
Link Inverter Fed Induction Motor
N. Saikumar1, Mr. G. Durga Prasad2 and Dr. V. Jagathesan3
P.G. Student, 1,2 Swarnandhra College of Engg.& tech.(SCET), Narsapur,
Andhra Pradesh, JNTU (Kakinada), INDIA.
Assistant Professor,1,2EEE Department, Karunya University,
Karunya Nagar, Coimbatore, T.N, INDIA.
In recent days multilevel inverters has become very popular for motor
drive applications of industry. Multilevel pulse width modulation
inversion is an effective solution for increases the level number of the
output wave form and thereby dramatically reduced to the harmonics
and total harmonic distortion.
The MLDCL provides a dc voltage with the shape of a staircase, with
or without pulse width modulation, to the bridge inverter, which in turn
alternates the polarity to produce an ac voltage.
This paper orients to develop a series parallel switched multilevel dclink inverter (SPMLDCLI) with a primary objective to arrive at
reduced component count for a particular voltage and the THD in
output voltage of inverters is significantly improved compared with
already existing topologies.
Finally this paper presents SPSMLDCLI fed single phase induction
motor drive. The performance of the topology is investigated through
MATLAB based simulation.
1. Introduction
Multilevel inverters have very important development for high power medium voltage
AC drives. Quite a lot of topologies have found industrial approval; Neutral Point
Clamped, flying capacitor, H-bridge, cascaded with separated DC source, several
control and modulation strategies have been developed Pulse Width Modulation
N. Saikumar et al
(PWM), Sinusoidal PWM, Space Vector PWM and Selective harmonic
Eliminations[1]. Multilevel converters are mainly controlled with sinusoidal PWM
extended to multiple carrier arrangements of two types: Level Shifted (LS-PWM),
which includes Phase Disposition (PD-PWM), Phase Opposition Disposition (PODPWM) and Alternative Phase Opposition Disposition (APOD-PWM) or they can be
Phase Shifted (PS-PWM) [2] this paper presents a new class of multilevel inverters
based on a multilevel dc link (MLDCL). Single phase Induction Motor has good
efficiency and moderate starting torque.
This paper presents a new variety of MLDCLI which uses lower number of
sources, power switches and eliminates the necessity of capacitors. The proposed
topology coined as series parallel switched multilevel dc-link inverter (SPSMLDCLI)
synthesizes a nearly distortion less sinusoidal output voltage owing to its inherent
ability to increase the number of levels. The performance of this SPMLDCLI is
investigated through MATLAB based simulation over a range of viable modulation
2. Circuit Topology
The power circuit of the inverter consists of a number of voltage sources in the ratio
V0:Vn with switches and a diode is connected across the H-bridge. The voltage sources
are connected in series parallel manner for generating desired level of output voltage
.To increase the number of levels further, an external cell is required which contains
two voltage sources and diodes along with a switch as shown in fig.1.
Hence when a dc link voltage from power circuit is fed to the full bridge inverter, a
Nearly high quality sinusoidal output voltage will be obtained. Therefore with less
number of switches better THD output is obtained when compared with existing
The operating modes of the fifteen level SPSMLDCLI topology are explained with
individual figures for each level shown below figures(2-3).
Fig. 1: Generalized structure of SPSMLDCLI.
Series Parallel Switched Multilevel DC Link Inverter Fed Induction Motor
Fig. 2: SPSMLDCLI operating mode-level 1(±50 V).
Fig. 3: SPSMLDCLI operating mode-level 2(±100 V).
3. Simulation Results
The SPSMLDCLI topology has been implemented and simulated for R,RL and
Induction Motor as loads. The output voltage and current waveforms for fifteen level
topology and stator current, torque and speed characteristics are shown in figures
(figure9-figure 14)
Fig. 4: Simulation Circuit for SPSMLDCLI FED induction motor.
N. Saikumar et al
Fig. 5: Output voltage waveform of
SPSMDCLI with RL-load
Fig. 6: Output voltage of DBMDCLI with
Fig. 7: FFT Analysis (SPSMLDCLI)
Fig. 8: Torque and speed waveform of
SPSMLDCLI fed single phase induction
Fig. 9: Stator current waveform of SPSMLDCLI fed single phase induction motor.
Series Parallel Switched Multilevel DC Link Inverter Fed Induction Motor
4. Conclusion
A series parallel switched multilevel dc link inverter fed induction motor drive has
been implemented using mat lab and simulation results are presented.
Due to reduced switch count of this topology compared with existing topologies, the cost will be
reduced and less THD output voltage will be obtained.
A modified PD-MC PWM method is presented for SPSMLDCLI Fed induction motor drive. The
proposed method combines PD-MC PWM and LS-PWM, which are high quality output voltages and
input currents respectively.
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