Self-Referenced, Trimmed and Compensated RF
CMOS Harmonic Oscillators as Monolithic
Frequency Generators
Integrating Time
Michael S. McCorquodale, Ph.D.
Founder and CTO, Mobius Microsystems, Inc.
2008 IEEE International Frequency Control Symposium
Honolulu, HI
Session B3L-A: Novel Oscillators and Modeling
Tuesday, May 20, 2008
Outline
• A brief history of frequency synthesis
• Emerging integration technologies
• Self-referenced, trimmed and compensated RF
CMOS harmonic (LC) oscillators (CHOs)
– Motivation and concepts
– Simplified architecture
– Published implementations
• Performance benchmarking
– Total frequency error
– Single sideband phase noise power spectral density
– Period and cycle-to-cycle timing jitter
• Conclusions
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 2 of 41
A brief history of frequency synthesis
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 3 of 41
A brief history of frequency synthesis
• Crystal oscillators (past – present)
–
–
–
–
1880: piezoelectricity discovered by the Curies
1917: XTAL resonance explored by Langevin for SONAR
1919: frequency control using XTALs by Nicholson and Cady
1919 – present: XOs proliferate
• Phase-locked frequency synthesizers (present)
– 1980s – present: PLLs developed to allow for multiple and
rational frequencies to be synthesized from one XTAL reference
– Degraded phase noise and jitter relative to fundamental mode
XOs, but silicon integration becomes paramount
• Integrated frequency references (future?)
– Significant work toward realizing integrated frequency references
begins a “race” to replace quartz
– 1990’s – present: MEMS microresonators
– 2000’s – present: CMOS harmonic oscillators (this work)
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 4 of 41
Emerging integration technologies
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 5 of 41
Emerging integration technologies
• Surface and bulk MEMS microresonators have
emerged as possible replacement for quartz
technology as a frequency reference
– Objective is integration: smaller form-factor, lower cost, etc.
– Integration may enable advanced timing or carrier
synthesis architectures as references become “free”
[Discera]
History
Emerging
[SiTime]
CHOs
Benchmarking
Conclusions
Slide 6 of 41
Emerging integration technologies
• Fundamental challenges
–
–
–
–
–
–
–
New process technology
Hermetic packaging
Relatively high freq. temperature coefficient (fTC)
Scaling resonator frequency
Power handling
High motional resistance complicates circuit design
Nonlinear transduction incurs noise penalty
• Current MEMS-referenced implementations
– Low frequency MEMS resonator with fractional-N PLL
where divider is dithered based on input of a
temperature sensor for compensation of fTC
– Synthesizes frequencies in the 10’s of MHz band
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 7 of 41
Self-referenced, trimmed and compensated RF
CMOS harmonic (LC) oscillators (CHOs)
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 8 of 41
CHOs: Motivation and concepts
• Achieve integration with a solid-state technology to
realize monolithic timing references
– Leverage advances in RF CMOS
– Explore performance limits of CMOS oscillators
• Conceive an architecture to achieve:
– Low frequency error, low phase noise and low timing jitter
• Develop with an eye toward consumer timing
– Clock references for serial wire interfaces such as USB
(±500ppm), S-ATA (±350ppm) and PCI (±300ppm)
– Here bit error rate (BER) is paramount and dominated by
eye closure due to total frequency error and timing jitter
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 9 of 41
CHOs: Motivation and concepts
Measured
eye-opening
Specification
template
Period jitter determines the eye-opening and
eye-opening determines the BER
Commercial serial-wire
interfaces have eye-opening
specifications
(USB test shown here)
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 10 of 41
CHOs: Motivation and concepts
• Key concepts
– Far-from-carrier phase noise is the most
significant contributor to timing jitter
– Linear frequency multiplication/division
increases/decreases phase noise power
quadratically
– Total timing error is dominated by jitter, not
frequency error
• With these concepts is it possible to
develop a monolithic low-Q RF LC
oscillator and achieve low timing jitter as
well as low frequency error?
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 11 of 41
CHOs: Motivation and concepts
SSB
phase noise
PSD
(dBc/Hz)
8
σp =
ωo2
∫
∞
0
⎛ No ⎞
⎜⎜
⎟⎟ sin 2 πf mTo df m
⎝ Po ⎠ f m
How does
phase noise
manifest into
period jitter?
σp = RMS period jitter
ωo = fundamental radian frequency
To = fundamental period
fm = offset frequency from fundamental
(No/Po)fm= phase noise at offset fm from fundamental
sine
square
Offset from
fundamental
(Hz)
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 12 of 41
CHOs: Motivation and concepts
Peak at
fm = ½ fo
-50dB
at 10kHz
Period Jitter sin2(πf To) Integration Mask
Period Jitter sin2(πf To) Integration Mask
Consider 10MHz
reference
1
0.8
0.6
Linear to log
0.4
0.2
0
0
1
2
3
4
5
6
7
8
9
Offset Frequency (Hz)
Null at fo
(fm = 0)
History
Emerging
10
0
10
-5
10
-10
10
-15
10
0
10
6
CHOs
4
10
6
10
8
10
Offset Frequency (Hz)
x 10
Null at 2fo
(fm = fo)
2
10
Close-to-carrier phase noise
(<10kHz) is significantly attenuated
when converting to period jitter
Benchmarking
Conclusions
Slide 13 of 41
CHOs: Motivation and concepts
Visualizing frequency multiplication and division
effects and the typical net performance degradation
in a phase-locked loop relative to the reference
PLL VCO
(unlocked)
Close-to-carrier
phase noise is
attenuated and
far-from carrier
phase noise is
amplified
+20log10(N)
-20log10(N)
Phase noise PSD (dBc/Hz)
Phase noise PSD (dBc/Hz)
×N
Reference ÷N
+10log10(N 2)
XO/MEMS
reference
Period jitter
integration mask
sin2(πfmTo)
PLL
output
path
PLL
loop BW
fm (Hz)
fm (Hz)
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 14 of 41
CHOs: Simplified architecture
• Free-run a CMOS RF LC oscillator near 1GHz
• Frequency divide by a large ratio
• Implement high-resolution process trimming
• Implement open-loop temperature compensation
• Implement closed-loop long-term drift stabilization
• Actively regulate the power supply
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 15 of 41
CHOs: Simplified architecture
High-swing pMOS
cascode bias
2.5
2.5
vac
2.5
+
_
vbias
Fixed thin film
caps trim nominal
frequency
Cv(vctrl(T))
compensates
LCO over T
Amplitude
detector
Cf [12:0]
Cf [12:0]
MR[12:0]
TR[12:0]
MR[12:0]
Cv [5:0]
TC[5:0]
TR[12:0]
Common
mode
detector
Cv [5:0]
TC[5:0]
TC[5:0]
vctrl(T) 2.5
History
Control
loops
mitigate drift
Emerging
TC[5:0]
+
_
vcmc
2.5 vctrl(T)
CHOs
Benchmarking
Conclusions
Slide 16 of 41
CHOs: Simplified architecture
3.3
3.3
vBG
vBG _
+
2.5
3.3
+
_
vctrl(T)
IPTAT
To trimming
switches and
programmable
logic
Emerging
96-bit
MTP
NVM
I2C
FLL
SSCG
NVM Control
SDL
SDA
Logic for I2C interface, trimming,
spread-spectrum clock generation and NVM
Programmable T-dependent
compensating analog voltage
History
CLK
D2S
CHO
ICTAT
Differential to
single-ended converter,
programmable divider
and configurable output
Regulated supply via
bandgap-referenced
LDO
CHOs
Benchmarking
Conclusions
Slide 17 of 41
Recently published implementations
1500µm
400µm
Config.
Dividers
Test
Structures
vctrl(T)
Generator
I2C, FLL, SSCG,
NVM Control
LDO
I/O
+
ESD
2.5-to-3.3V
Level Shift
Bias
96-bit MTP NVM
Michael S. McCorquodale, et al., “A 0.5–480MHz Self-Referenced CMOS Clock
Generator with 90ppm Total Frequency Error and Spread Spectrum Capability,”
IEEE Int. Solid State Circuits Conf. Dig. of Tech. Papers, San Francisco, CA 2008.
History
Emerging
CHOs
–gm
amplifier
fTC cal. bus
Bias
POR
½ fo discrete
calibration array
CB<7:0>
fTC open-loop
temp. comp.
A-MOS varactors
D2S
½ fo discrete
calibration array
Cf [12:0] and M[12:0]
2 x Cv [5:0] and TC[5:0]
Bias Generation
& Distribution
fTC open-loop
temp. comp.
A-MOS varactors
I/O
+
ESD
–gm Amplifier,
Amplitude and
Common Mode
Control Loops
Band-Gap Reference
550µm
1500µm
Cf [12:0] and M[12:0]
Process Control Structures
Frequency
dividers
Michael S. McCorquodale, et al., “A Monolithic and Self-Referenced
RF LC Clock Generator Compliant with USB 2.0,” IEEE J. of Solid
State Circuits, vol. 42, no. 2, Feb. 2007, pp. 385-399.
Benchmarking
Conclusions
Slide 18 of 41
Performance benchmarking
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 19 of 41
Performance benchmarking
• Existing (XO/XO-PLL)
– 24MHz 4-pin can crystal oscillator (XO)
– 24MHz 2-pin passive crystal-referenced phase-locked loop (XO-PLL)
– 12MHz 2-pin passive ceramic resonator + sustaining circuit
• Emerging (MEMS-PLL)
– 20MHz MEMS-referenced PLL (vendor #1)
– 12MHz MEMS-referenced PLL (vendor #2)
• This work (CHO)
– 12MHz, 1.536GHz LC-referenced CHO
– 12MHz, 960MHz LC-referenced CHO
• Benchmarks
–
–
–
–
History
Total frequency inaccuracy (due to trimming, power supply and temp.)
SSB phase noise PSD
Period and cycle-to-cycle jitter
Total timing error
Emerging
CHOs
Benchmarking
Conclusions
Slide 20 of 41
Total frequency inaccuracy
3500
CHO trim
occurs at
35°C
Best CHO
performance in Si to
date shown
Typical production
yield is ±150ppm
25.0
1750
0.0
0
24MHz XO
20MHz MEMS-PLL
12MHz MEMS-PLL
12MHz CHO VDD + 10%
12MHz CHO nominal VDD
12MHz CHO VDD -10%
12MHz Ceramic
-25.0
-1750
-50.0
Normalized frequency innacuracy, δf /f o (ppm)
Normalized frequency innacuracy, δ f /f o (ppm)
50.0
-3500
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature (°C)
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 21 of 41
Single sideband phase noise PSD
0
24MHz XO
m
SSB phase noise PSD, (N /P ) (dBc/Hz)
o o f
-20
-40
-60
-80
-100
-120
-140
-160
1
10
2
10
3
10
4
10
5
10
6
10
Offset frequency (Hz), f (Hz)
m
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 22 of 41
Single sideband phase noise PSD
0
24MHz XO
12MHz Ceramic Oscillator
m
SSB phase noise PSD, (N /P ) (dBc/Hz)
o o f
-20
Ceramic resonator is
lower Q than XO so
close-to-carrier phase
noise is higher
-40
-60
-80
-100
-120
-140
-160
1
10
2
10
3
10
4
10
5
10
6
10
Offset frequency (Hz), f (Hz)
m
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 23 of 41
Single sideband phase noise PSD
0
24MHz XO
12MHz Ceramic Oscillator
24MHz XO-PLL
m
SSB phase noise PSD, (N /P ) (dBc/Hz)
o o f
-20
Outside PLL loop BW,
phase noise tracks VCO
(note PLL loop mult. is 1)
-40
-60
-80
-100
-120
-140
-160
1
10
2
10
3
10
4
10
5
10
6
10
Offset frequency (Hz), f (Hz)
m
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 24 of 41
Single sideband phase noise PSD
0
24MHz
12MHz
24MHz
12MHz
m
SSB phase noise PSD, (N /P ) (dBc/Hz)
o o f
-20
XO
Ceramic Oscillator
XO-PLL
MEMS-PLL
-40
-60
-80
-100
-120
-140
-160
1
10
2
10
3
10
4
10
5
10
6
10
Offset frequency (Hz), f (Hz)
m
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 25 of 41
Single sideband phase noise PSD
0
24MHz
12MHz
24MHz
12MHz
20MHz
m
SSB phase noise PSD, (N /P ) (dBc/Hz)
o o f
-20
XO
Ceramic Oscillator
XO-PLL
MEMS-PLL
MEMS-PLL
MEMS-PLL frequency
multiplication
increases phase noise
inside PLL loop BW
-40
-60
-80
-100
-120
-140
Outside PLL loop BW,
phase noise tracks VCO
-160
1
10
2
10
3
10
4
10
5
10
6
10
Offset frequency (Hz), f (Hz)
m
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 26 of 41
Single sideband phase noise PSD
0
24MHz
12MHz
24MHz
12MHz
20MHz
12MHz
m
SSB phase noise PSD, (N /P ) (dBc/Hz)
o o f
-20
XO
Ceramic Oscillator
XO-PLL
MEMS-PLL
MEMS-PLL
CHO
-40
-60
-80
-100
-120
-140
-160
1
10
2
10
3
10
4
10
5
10
6
10
Offset frequency (Hz), f (Hz)
m
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 27 of 41
Single sideband phase noise PSD
0
24MHz
12MHz
24MHz
12MHz
20MHz
12MHz
12MHz
m
SSB phase noise PSD, (N /P ) (dBc/Hz)
o o f
-20
XO
Ceramic Oscillator
XO-PLL
MEMS-PLL
MEMS-PLL
CHO
CHO
-40
Close-to-carrier
phase noise is
higher in CHO but
comparable to
MEMS-PLL
-60
-80
-100
-120
-140
CHOs have much lower
far-from-carrier phase
noise than PLLs
-160
1
10
2
10
3
10
4
10
5
10
6
10
Offset frequency (Hz), f (Hz)
m
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 28 of 41
Single sideband phase noise PSD
-100
24MHz
12MHz
24MHz
12MHz
20MHz
12MHz
12MHz
m
SSB phase noise PSD, (N /P ) (dBc/Hz)
o o f
-20
XO
Ceramic Oscillator
XO-PLL
MEMS-PLL
MEMS-PLL
CHO
CHO
-40
-60
Project onto sin2(πfmTo)
-80
-100
-120
-140
SSB phase noise PSD × sin2(πf To) (dBc/Hz)
m
0
From ~30kHz
all PLL implementations
are noisier than CHOs
-120
-140
-160
-180
-200
24MHz
12MHz
24MHz
12MHz
20MHz
12MHz
12MHz
-220
-160
1
10
2
10
3
10
4
10
5
10
6
10
1
10
Offset frequency (Hz), f (Hz)
Emerging
3
10
4
10
5
6
10
10
Offset frequency (Hz), f (Hz)
m
History
2
10
XO
Ceramic Oscillator
XO-PLL
MEMS-PLL
MEMS-PLL
CHO
CHO
m
CHOs
Benchmarking
Conclusions
Slide 29 of 41
Single sideband phase noise PSD
-100
-120
CHO, XO and Ceramic
Oscillator all exhibit similar
far-from-carrier noise
-140
-160
Visualize on linear scale
-180
-200
24MHz
12MHz
24MHz
12MHz
20MHz
12MHz
12MHz
-220
1
10
2
10
3
10
4
10
XO
Ceramic Oscillator
XO-PLL
MEMS-PLL
MEMS-PLL
CHO
CHO
5
10
6
10
SSB phase noise PSD × sin2(πf To) (dBc/Hz)
m
SSB phase noise PSD × sin2(πf To) (dBc/Hz)
m
-130
-120
-140
-150
>15dB
-160
-170
Projected CHO noise approaches XO
noise but XO is at twice the frequency
-180
24MHz
12MHz
24MHz
12MHz
20MHz
12MHz
12MHz
-190
-200
0
3
4
5
m
m
Emerging
2
Offset frequency (MHz), f (Hz)
Offset frequency (Hz), f (Hz)
History
1
XO
Ceramic Oscillator
XO-PLL
MEMS-PLL
MEMS-PLL
CHO
CHO
CHOs
Benchmarking
Conclusions
Slide 30 of 41
Period and cycle-to-cycle jitter
• Phase noise measurements show that
far-from-carrier phase noise is very similar for
XO, ceramic oscillator and CHO
• Far-from-carrier phase noise for CHO appears
lower than all implementations, except XO, due
to higher power in LCO (but XO at double freq.)
• Theory predicts that these three
implementations should exhibit similar period
jitter and CHO should exhibit the lowest jitter
• Theory also predicts that the PLL
implementations should exhibit comparatively
higher period jitter
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 31 of 41
Period and cycle-to-cycle jitter
24MHz XO
σp = 6.52psrms
σcc = 11.48psrms
24MHz XO-PLL
σp = 10.38psrms
σcc = 18.89psrms
Ceramic oscillator and XO have similar jitter;
1x multiplier in PLL degraded jitter in XO-PLL
History
Emerging
CHOs
Benchmarking
Conclusions
12MHz Ceramic
σp = 6.52psrms
σcc = 11.01psrms
Slide 32 of 41
Period and cycle-to-cycle jitter
20MHz MEMS-PLL
σp = 12.16psrms
σcc = 17.60psrms
Jitter for both
implementations is much
higher than XO and XO-PLL
as expected
History
Emerging
12MHz MEMS-PLL
σp = 36.40psrms
σcc = 46.99psrms
CHOs
Benchmarking
Conclusions
Slide 33 of 41
Period and cycle-to-cycle jitter
12MHz CHO
σp = 6.41psrms
σcc = 11.25psrms
CHO has lowest jitter and is
directly comparable to high-Q
XO because CHO has low
far-from-carrier phase noise
History
Emerging
12MHz CHO
σp = 5.73psrms
σcc = 9.32psrms
CHOs
Benchmarking
Conclusions
Slide 34 of 41
Period and cycle-to-cycle jitter
MEMS-PLL is
>6x higher
CHO has the
lowest jitter
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 35 of 41
Fractional total timing error
Introduce the concept of the fractional total
timing error, or the maximum error in any period
Basically, consider
due to frequency inaccuracy and jitter the
sum of the total
v
To
⎛ δT ⎞
⎟⎟
max⎜⎜
⎝ To ⎠
frequency error
AND the maximum
period jitter as a
metric which is
relevant to eye
closure
t
⎛ δT ⎞
⎟⎟ = (To × max(δf f o ) + ασ p ) To
max⎜⎜
⎝ To ⎠
Maximum
period error
History
Emerging
Ideal
period
Maximum jitter for a
bounding cycle count
CHOs
Benchmarking
Conclusions
Slide 36 of 41
This is the worst-case
fractional period error
and determines eye
opening and BER
fo
max(δf/fo) max(|f-1|)
(ps)
(ppm)
(MHz)
XO
XO + PLL
24
8
0.33
Total timing error
σp
(ps)
ασp
α = 14.1
(ps)
max(δT/To)
(ppm)
ασp /max(δT/To)
(%)
6.53
92.07
2218
99.6
8.51
120.00
2888
99.7
MEMS + PLL
24
8
0.33
12
α = 14.1 is for 10 cycles
(a common specification)
20
37
1.85
12.16
171.46
3466
98.9
MEMS + PLL
12
9
0.75
36.42
513.52
6171
99.9
CHO
12
400
33.33
6.41
90.38
1485
73.1
CHO
12
26
2.17
5.83
82.20
1012
97.4
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 37 of 41
Period jitter summary
• A low-Q LCO can achieve period jitter much lower than
high-Q implementations (including XOs and MEMS) by:
– Exploiting frequency division
– Exhibiting low far-from-carrier phase noise
• High-Q MEMS oscillators do not achieve low jitter and
phase noise due to loop multiplication and PLL VCO
• A low-Q LCO can be implemented in a standard solid state
process technology and achieve period jitter performance
directly comparable high-Q oscillators
• Power dissipation in the CHO is comparable to the
XO-PLL and MEMS-PLL implementations
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 38 of 41
Conclusions
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 39 of 41
Conclusions
• Self-referenced, trimmed and compensated RF
CMOS harmonic oscillators (CHOs) were
introduced as monolithic frequency generators
realized entirely in a solid-state process
technology
• CHO implementations were benchmarked
against incumbent XOs/XO-PLLs and emerging
MEMS-PLLs where it was shown that frequency
error was comparable and period jitter was
superior for the CHO
• CHOs are now entering the production phase
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 40 of 41
Questions are welcome
History
Emerging
CHOs
Benchmarking
Conclusions
Slide 41 of 41