Frequency synthesis a in mobile phone
Kalle Asikainen
NMP
Tampere
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 1
The local oscillator in a radio transceiver
•
The local oscillator (LO) is needed in every radio transceiver irrespective of the RF
architecture
•
The LO is used to mix the wanted frequency down to IF (or baseband) and vice
verse
•
The LO has to be tunable across the wanted frequency band and the frequency
resolution has to be equal to the channel spacing.
•
•
This kind of LO is called frequency synthesizer!
•
In microvawe radio at least one LO is running at microwave frequency
In a superheterodyne transceiver there are several LO:s and thus several frequency
synthesizers
Antenna
RF_Filter_1
LNA
RF_Filter_2
1st Mixer
1st IF
2nd Mixer
2nd IF
Demodulator
1st LO
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 2
2nd LO
Frequency synthesis methods
•
In LO generation there are basically two possible methods:
• Direct Digital Synthesis DDS
• Indirect synthesis = Phase Locked Loop PLL
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 3
Direct digital synthesis DDS
•
Digital samples of sinewaves of different frequencies are converted to analog by
DAC and often mixed with additional LO to RF/ microwave band
+ Immediate settling to frequency hop
- Spurioses
- Power consumption
- Needs extra LO and mixer to cover RF/microwave frequencies
© NOKIA
•
At the moment not very practical for a mobile phone !
•
Used in base stations (fast settling time) and signal generators/spectrum
analysers
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 4
Indirect synthesis = PLL
•
RF/microwave frequency is generated by multiplying a stable reference
frequency
•
PLL is used as a multiplier
+ Small power consumption
+ Spurioses controllable by PLL design
- Settling time limited by control theory !
•
© NOKIA
The most widely used LO generation method in all kinds of different transceivers
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 5
PLL synthesizer basics
•
The phase detector PD compares the reference frequency to the frequency from a
feedback divider N
•
PD controls the frequency of a voltage controlled oscillator VCO according to the
phase/frequency difference of its inputs
•
•
•
•
The output of the PD is pulsed and is translated to dc by the action the of loop filter
The VCO frequency is divided back down to reference frequency by N divider
By changing the N divider the output frequency can be controlled
The output frequency resolution equals reference frequency (channel spacing)
Reference freq
Loop filter
Output
PhaseDetector
Divider
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 6
What is a control system ?
Reference
commands
Disturbances
Control
forces
Controlled system
or plant
Controller
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 7
Output or
controlled
variables
PLL Synthesizer as a control system
•
PLL obeys basic control theory and can be analyzed accurately to certain extent !!
PLL design is not black magic !
PLL can be made to work by trial and error easily...
...but to make it work reliably…
...and to find out the performance limits...
The underlying theory should be known!
•
•
PLL can be simulated using basically any circuit or system simulator
But to make the simulation smart is a challenging task
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 8
Synthesizer as a sampled system
•
Due to sampled nature of the phase detector and the loop divider the loop cannot be
treated as a continuous time system in it’s strictest sense
•
In addition to that all the loop components e.g. phase detector and VCO are not
exactly linear
•
Still if the loop bandwidth is less than tenth of the phase detector sampling frequency
and all the components can be approximated by linear functions the continuos time
Laplace domain representation can be used
•
If the loop BW gets closer to the phase detector sampling frequency the discrete time
effects should be taken into account in order to to get accurate simulation results
•
The discrete time z-domain analyses should be used
•
The sampling introduces inherent sampling delay which tends to decrease phase
margins compared to continuos time analyzes
•
Sampling also causes aliasing of the noise at the offset of sampling frequency to the
baseband frequencies
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 9
Basic PLL control system in Laplace
domain
Θ r ( s)
+
Θ e ( s)
Kd
Vd ( s)
F(s)
Vc ( s)
Ko / s
Θ o ( s)
Θ f ( s)
1/N
Forward gain
Open loop gain
K d K o F ( s)
G fwd ( s ) =
s
Closed loop transfer function
K d K o F ( s)
Gol ( s ) =
sN
Θ o ( s) G fwd ( s )
K d Ko F (s)
H (s) =
=
=
Θ r ( s ) 1 + Gol ( s) s + K d K o F ( s )
N
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 10
Order of the control system
•
The order of the system refers to the highest degree of the polynomial expression
1 + Gol = 0 ≅ C.E
•
•
Which is called the Characteristic Equation (C.E.)
•
Even the simplest PLL is of second order, but in practice they are of 3rd to 5th order
The roots of the C.E. become the closed-loop poles of the overall transfer function
H(s)
Θ o ( s ) G fwd ( s )
K d K o F ( s)
=
=
H ( s) =
Θ r ( s ) 1 + Gol ( s ) s + K d K o F ( s )
N
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 11
Type of the control system
•
The type of a system refers to the number of poles of the open-loop gain Gol(s)
located at the origin.
•
•
The VCO in a PLL introduces one perfect integrator
•
•
Because the phase of the VCO is linearly related to the integral of the control
voltage
To enhance the tracking capability of the PLL the additional integrator is necessary
i.e. Type II PLL is often wanted
•
•
In other words, it tells how many perfect integrators there exists in the loop.
Type II loop is capable of tracking the phase error to zero in case of a frequency
step
The additional integrator is implemented in a loop filter
•
•
© NOKIA
In the past the active loop filters were used
Nowadays phase detector with charge pump (current) output combined with a
simple passive loop filter serves the same purpose
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 12
Closed loop response (Transfer response)
•
•
Closed loop response has a low pass nature
•
The reference noise is multiplied by N2 within the loop BW and shaped by the closed
2
loop response of the PLL
It shows how the noise from the reference or the phase detector is handled by the
loop
K d K o F (s)
N2
H (s) =
=
2
K d K o F ( s)
sN
s+
1+
N
K d K o F (s)
2
PLL closed loop freq response
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© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 13
Blue curve is a closed loop response
Error transfer response
•
•
Error transfer response E(s) is the response from PD reference input to PD output
The response from the VCO control voltage Vc(s) to VCO output frequency sΘo(s)
(remember that frequency is the time derivate of the phase) has the same response
but multiplied by VCO gain
•
•
It is often called modulation response M(s) as it tells about the PLL:s capability
to suppress the modulation inserted to VCO
Error transfer response has a high pass nature
PLL closed loop freq response
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Green curve is an error transfer response
err
E ( s) =
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© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 14
Θe ( s)
1
s
=
=
Θr ( s) 1 + K d K o F ( s) s + K d K o F ( s)
sN
N
f o ( s ) sΘ o ( s )
Ko
Kos
=
=
=
Vc ( s ) Vc ( s) 1 + K d K o F ( s) s + K d K o F ( s )
sN
N
Phase margin
•
The Bode plot is a useful tool for analyzing the stability of the control system. It
consists of a pair of graphs displaying the polar components of the open-loop gain
Gol(s) as a function of the frequency.
•
•
If Gol(s)= 0dB at the same time when ∠Gol(s) = -180° this equals to Gol(s) = -1
•
Phase margin tells how far the design is from the instability, usual goal being 45°
In these conditions the denominator of the loop transfer function H(s) equals zero
making the loop unstable
PLL open loop freq response
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© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 15
Θ o ( s ) G fwd ( s )
H (s) =
=
Θ r ( s ) 1 + Gol ( s)
Peaking and phase margin
The plot shows the second order system transfer response with different damping factors
(damping factor is a measure of stability and corresponds to the phase margin
of the higher order system)
H( ω , ζ )
N . 2 .ζ .ω n .j .ω
2
( j .ω )
ωn
j .ω .2 .ζ .ω n
2
ωn
2
N
10
Loop transfer response
36
dB ( H( ω , 0.1 ) )
dB ( H( ω , 0.3 ) )
dB ( H( ω , 0.5 ) )
30
24
dB ( H( ω , 0.7 ) )
dB ( H( ω , 1 ) )
18
dB ( H( ω , 1.5 ) )
12
6
0.1
1
ω
10
ω n
The peaking of the loop response depends on the phase margin of the loop
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 16
Synthesizer settling time
•
When N divider is changed the step like frequency error is seen between the phase
detector inputs
•
•
The wider the loop BW the faster the settling time
•
With smaller phase margin the ringing of the step response slowers the settling
considerably
The optimum phase margin from settling time point of view is about 45 - 50 degrees
giving overshoot of step response of about 30-35%
PLL loop step response
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© NOKIA
-0.50
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125.00u 250.00u 375.00u 500.00u
t [s]
N*f_in
ph_err
f_out
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 17
PLL loop output phase error
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Settling time of second order system with
different damping factors
Normalized output responce
Type II Second Order Step Responce
θo( t , 0.1 )
θo( t , 0.4 )
θo( t , 0.7 )
θo( t , 1.1 )
θo( t , 2 )
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
© NOKIA
1
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 18
2
3
4
5
6
7
ω n .t
8
9 10 11 12 13 14
Settling time measured with modulation
domain analyzer MDA
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 19
Reference spurioses
•
•
•
The operation of the phase detector is repetitious at the reference frequency
The loop filter can newer filter the reference frequency completely out
The remaining ac modulates the VCO generating so called reference spurioses
which can be seen at the VCO spectrum as discrete spikes
•
Spurious signals are expressed as relative to the carrier power dBc
•
The most problematic about the reference spurioses is that they fall to adjacent
channels of the communications system
•
Any dc current leakage in the loop filter will increase spurioses because the lost
control voltage has to be compensated by the phase detector pulses
•
The highest attenuation of the reference spurioses is obtained when:
•
•
•
© NOKIA
the loop BW is narrow
the phase margin is small => high peaking gives fast roll-off
the loop is of high order (several poles at the same frequency range give faster
roll-off)
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 20
Reference spurioses measured with
spectrum analyzer
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 21
Phase noise
•
The signal is in general case given by
S (t ) = A(t ) cos[ω 0t + θ (t )]
•
where A(t) represents the time dependent amplitude and θ(t) the time dedent
phase
•
In synthesizer A(t) is often taken to be constant which means that no AM
modulation or amplitude noise is present
VCO has an amplitude limiting property
phase detector and dividers are only sensitive to phase
•
•
That’s why the phase modulation (noise) θ(t) is usually the only noise present in
a synthesizer
The most commonly used phase noise notation a so called SSB (single sideband)
phase noise L(f) which is a ratio of power spectral density in one phase modulation
sideband to the total signal power. The unit of L(f) is dBc/Hz.
•
It can be measured using spectrum analyzer which gives two-sided spectrum
(there seems to be contradiction in terms: SSB spectrum is two sided)
•
When the noise is measured using SA the resolution bandwidth has to be taken
into account (the real value referred to 1Hz band is 10*log(RBW) lower than the
measured noise)
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 22
Phase noise in a synthesizer
•
Inside the loop BW the output phase noise is the multiplied reference noise and
phase detector noise (often called noise floor) shaped by the closed loop response
•
•
•
•
The noise power multiplication factor is N2 which results in 20*logN
Outside the loop BW the phase noise is essentially the VCO noise itself
This means that the PLL "cleans" the VCO noise within the loop BW
When the N divider is high the output phase noise within the loop BW becomes high
unless the reference/phase detector noise floor is exceptionally low
Phase noise at VCO output
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100.0
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10.0k 100.0k 1.0M 10.0M
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syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 23
Measured synthesizer & VCO output noise
with reference spurioses
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 24
Synthesizer output noise measured with a
spectrum analyzer (linear frequency scale)
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 25
RMS phase error of the synthesizer
•
Usually defined for phase modulated digital communications systems
•
•
•
•
By integrating the synthesizer output phase noise profile the RMS phase error results
L(f) ≈ ½ Sϕ(| f |) if the phase modulation index of the noise is reasonably small
It is dependent on
•
•
•
•
Affects highly on BER (bit error ratio) performance
In analog frequency modulated systems the corresponding measure is residual FM
•
•
It is a measure of signal to noise ratio (SNR) of the transmittter
Output close-in phase noise
σϕ =
f2
f2
f1
f1
∫ Sϕ ( f )df ≈ 2 ∫ L( f )df =
Pnoise
≈ SNR −1
Ptotal
Loop BW
Loop peaking (phase margin)
In a transmitter the synthesizer is usually responsible for the highest amount of RMS
and peak phase error
•
•
© NOKIA
The other contributors are the modulator, PA and mixers
The dynamic effects like switching transients and unsettled synthesizer increase
the peak (and rms) phase errors in TDMA systems
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 26
Phase detector = PD
•
•
•
•
There exists multiplier type (mixer) PD:s and a variety of different sample&hold PD:s
The most commonly used PD is though a so called PFD Phase Frequency Detector
Its has an infinite lock-in range and ±2π linear range
PFD is normally followed by current source charge pump
•
•
•
•
Current output gives the better linearity than voltage output
Additional integrator required by Type II loop can be realized by a simple passive
loop filter
Phase detector gain is related to the output current
Io
K
=
Phase detector should have extremely low noise floor d
2π
•
The noise floor depends on the sampling frequency (reference frequency) and
detector gain (current)
higher sampling frequency gives higher noise floor
higher charge pump current gives usually lower noise floor
•
© NOKIA
In GSM type of solutions the noise floor should be around -150...-160dBc/Hz
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 27
PFD response
9G
π
π
π
π
π
9G
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 28
π
π
π
Simple Phase Frequency Detector PFD
Ref
SET
D
Q
CK
Q
"1"
VCO
CLR
R
SET
D
R
"1"
CK
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 29
CLR
U
Q
Q
D
PFD with current source charge pump
output
Charge pump is followed by simple filter which has
an integrator response when the input is current
V ( s ) sRC + 1
1
F (s) =
=
= R+
I ( s)
sC
sC
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 30
PFD input/output timings
Fr is reference pulse train
Fp is feedback pulse train
Do is charge pump output pulse train
fr
fp
H
Do
L
fr > f p
fr = f p
fr < fp
fr < f p
fr < f p
Current pulses charge/discharge the integrator capacitor
to generate the correct control voltage for the VCO
The current is constant but the width of the pulse is varying
according to the phase difference of the PFD inputs
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 31
Second order loop filter for charge pump
PFD
I(s)
V(s)
F (s) =
R2
C1
V ( s)
sC 2 R2 + 1
=
I ( s ) s ( sC1C2 R2 + C1 + C2 )
The first pole is at the origin (integrator)
C2
τ 1 = R2
The zero has a time constant
τ2 = R2C2
The filter response can be written in the form
F (s) =
© NOKIA
C1C2
C1 + C2
The second pole has a time constant
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 32
( sτ 2 + 1)τ 1
s ( sτ 1 + 1)C1τ 2
Transfer function of second order loop filter
. 9 C2 3.310
. 9 R2 3.910
. 3
C1 0.6810
F( ω )
( j .ω .R2.C2 1)
( j .ω .( C1 C2 j . ω .C2.R2.C1) )
Transfer function of loop filter
150
120
Phase response of transfer function
0
dB( Mag( F( ω ( x) ) ) ) 90
Ph( F( ω ( x ) ) )
60
90
30
0
135
10
© NOKIA
45
3
4
5
100 1 10 1 10 1 10
ω ( x)
2 .π
6
1 10
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 33
7
1 10
8
1 10
10
100
3
4
5
6
1 10 1 10 1 10 1 10
ω ( x)
2 .π
7
8
1 10 1 10
4th order loop filter for charge pump PFD
I(s)
R3
R4
V(s)
R2
C1
C3
C4
C2
Additional poles have time constants τ3 = R3C3
τ4 = R4C4
Additional poles have to be at high enough frequency not to ruin the phase margin
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 34
Reference source
•
Is typically a VCTCXO Voltage Controlled Temperature Compensated Crystal
Oscillator
•
Has to have a high frequency stability (temperature compensated)
•
•
GSM spec 0.1ppm (parts per million)
Has to have low phase noise, in GSM -120…-145dBc/Hz at 1kHz offset
•
Because the reference noise is increased by 20*logN by the PLL
•
Is normally voltage controlled in order to AFC Automatic Frequency Control to be
able to tune the local oscillator according to temperature changes and Doppler shift
•
Crystal oscillator typically operates at several MHz and has to be divided down to
reference frequency (channel spacing)
•
•
© NOKIA
The reference divider is usually called R divider
The division by R decreases the phase noise by 20*logR, which has to be taken
into account when calculating the noise budget of the synthesizer
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 35
VCO
•
•
•
Linear tuning range has to cover the operating band
•
An important specs in TDMA systems are pushing and pulling figures
•
VCO gain Ko (tuning sensitivity) is expressed in MHz/V
Phase noise spec is typically deduced from rms phase error spec (= noise floor and
loop BW) at low offsets and blocking spec at high offsets
•
Pushing tells the frequency change as a function of the source voltage change
(source glitch or ground bounce)
•
Pulling tells the frequency change as a function of the load change
Low battery voltages in current and future mobile phones causes certain problems:
•
•
•
•
Wide tuning range combined with low source voltage makes the VCO gain high
High gain makes the pushing figure and phase noise worse
This can be solved by using higher voltage source for PLL charge pump in order
to get the VCO gain lower
Low power consumption tends to rise the phase noise because the energy stored in
a resonator circuit is smaller
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 36
Feedback (N) divider
•
•
N divider has to be programmable in order to change the output frequency
•
The fixed prescaler would make the minimum step of the divider equal to prescaling
factor
•
This can be overcome by a so called dual modulus prescaler P/(P+1) where two
prescaling factors are alternated by the following CMOS logic
•
The input is divided by (P+1) for A times and by P for (B-A) times thus giving the total
division ratio of the dual-modulus prescaler of:
At RF/Microwave frequencies the special prescaler P (often BJT) is used before
programmable divider in order to bring the frequency low enough for standard CMOS
logic to handle
•
•
•
Ntot = A(P+1) + (B-A)P = BP + A, where B ≥ A
The smallest possible division ratio of a dual modulus prescaler is P2
In order to accomplish smaller minimum division ratios the three- or even fourmodulus (quad-modulus) prescalers are sometimes used
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 37
Dual modulus prescaler
modulus control
load
B
output
input
B
P/(P+1)
load
Dual-modulus prescaler
A
A
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 38
logic
The limitations of integer N divider
•
In integer-N synthesizers the channel spacing dictates the reference frequency
because the output frequency can only be an integer multiple of reference
•
As the loop filter should be able to attenuate the reference spurs to the specified
level the bandwidth of the loop should be comparable to the reference frequency
•
•
20*logN noise multiplication sets the amount of phase noise at the output caused by
the noise floor of the synthesizer.
•
•
This of course sets the limit for the realizable settling time
This means that if the channel spacing is small and at the same time the output
frequency is high it is practically impossible to design a synthesizer with a small
rms phase error.
The obvious solution to previous problems seems to be an N divider capable of
fractional division !
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 39
Fractional-N divider
•
N divider that is capable of dividing by fractional division ratio instead of only by
integer division ratio.
•
This way the reference frequency can be higher than the channel spacing.
•
•
Reference spurioses move to higher offsets (easier to filter out by the loop filter)
Noise multiplication by 20*logN gets smaller
•
Actually digital divider capable of fractional division does not exist but it has to be
implemented by alternating two (or more) different division ratios
•
Fractional-N synthesizers are based on conventional synthesizer design, but with an
additional control circuitry to rapidly alternate the division ratio between N and (N+1)
•
Let us assume that the feedback divider ratio is N for (q - p) reference periods and
(N+1) for p reference periods. Over the q reference periods, the average output
frequency is
 N (q − p ) + ( N + 1) p 

p
f out = f ref 

•
q
 = f ref  N + q 



The concept is quite similar to the dual-modulus counters. In fractional-N the period
of dual modulus operation extends over more than one reference period whereas in
an integer N the dual-modulus operation is reduced within one reference period only
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 40
Fractional-N beatnote
,R
'&OHYHOGHWHUPLQHGE\1STIUHI
W
,R
'&OHYHOGHWHUPLQHGE\1I
UHI
The changing of the division ratios makes the phase detector to constantly "correct"
the VCO frequency. The correction current pulses form a sawtooth waveform.
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 41
Fractional N compensation
•
The fractional sawtooth (beatnote) modulates the VCO generating the so called
fractional sidebands
•
•
•
They fall to adjacent channel frequencies as in integer N synthesizer
Some compensation method is needed to remove the sawtooth
Fractional N compensation is the heart of the whole fractional N synthesizer
•
•
It defines the performance of the synthesizer !
The compensation can be made at the output (using DAC) or at the input of the
phase detector (using programmable digital delay line DLL)
Fref
DLL calibration
N/N+1 counter
over flow
4-bit F reg
(LSB)
© NOKIA
LPF
D
4-bit Accum
Adder
φ
VCO
Compensation scheme at the input of the phase detector
5-bit A reg
19-bit RF N register
10-bit B reg
(MSB)
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 42
Fractional-N compensation at the output of
the phase detector
Xoscillator
Loop filter
Output
9 UHIW
PhaseDetector
9 SW
I UHI
IF
9 GW
9 FRPSW
1
2IIVHW
JDLQDGM
Dual N Divider
S
WRT
$FFXPXODWRU
>$@
QELW
'HOD\
'$
)XOODGGHU
2YHUIORZ
1
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 43
1STIUHI
The uncomplete fractional compensation
effects
•
•
Unfortunately neither of the compensation methods can do the job properly
Fractional spurious compensation is usually not perfect
•
In some bad designs they can still be as high as in integer N synthesizer
•
•
In all designs fractional compensation tends to rise the phase detector noise floor
•
•
In this case the wider loop BW than in integer N cannot be used
In some bad designs the noise floor rise can mask the noise multiplication benefit
of smaller N divider figure
From this perspective it would be more efficient to prevent the generation of
spurioses rather than compensating them
•
A third compensation method that actually combines the fractionality generator
and the spurious compensation is utilizing noise shaping ∆Σ modulator as a
controller for the multimodulus divider
•
•
Using this method very small frequency resolution can be realized
© NOKIA
Excellent close in phase noise performance can be reached but the phase noise
at high offsets (outside loop BW) can be rather high due to high pass noise
shaping
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 44
Fractional-N generation/compensation
using ∆Σ modulator
fref
PFD
F(s)
VCO
N / ...N+2p-1
frequency control
© NOKIA
∆Σ
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 45
P control bits
fout
Fractional-N applications
•
Despite it’s trade offs fractional-N synthesizers are used in for instance signal
generators and spectrum analysers where
•
•
Frequency resolution of even sub-herz is needed
The common claim that fractional-N could improve settling time of the synthesizer
considerably is missleading
•
Statements of lower output noise and lower reference spurioses are not
necessarily true
•
It is often said that the faster phase detector uppdate rate would improve settling
time
© NOKIA
•
This does not seem to be true
•
The benefit is that the continuos time control theory is more valid with
higher phase detector sampling rate (loop BW << fref)
•
Nyquist criterium (loop BW < ½ fref) is the ultimate limit of the loop BW !
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 46
Commercial synthesizer chips for mobile
comms
•
Usually synthesizer chips consist of:
•
•
•
Programmable reference divider R
PFD phase detector followed by charge pump with programmable output current
Dual, triple or quad modulus prescaler followed by programmable divider
= N divider
•
•
Three wire serial programming interface
Very commonly they include two synthesizers for different frequency bands
•
•
Two locals of superheterodyne transceiver can be generated using one
chip
Still nowadays the external components are typically:
•
•
•
•
© NOKIA
Reference source (VCTCXO)
VCO
Loop filter
Power supply filtering components
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 47
Block diagram of typical dual synthesizer
fin RF
RF
prescalar
18-BIT RF
N COUNTER
PHASE
COMP.
Fout/
Lock
Detect
OSC
IF
prescalar
15-BIT IF
N COUNTER
CLOCK
DATA
22-BIT
DATA REGISTER
LE
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 48
Fo/LD
MUX
15-BIT IF
R COUNTER
fin IF
Do RF
RF
LD
15-BIT RF
R COUNTER
OSC in
CHARGE
PUMP
IF
LD
PHASE
COMP.
CHARGE
PUMP
Do IF
About synthesizer specifications 1
•
Usually selectivity sets most difficult requirement for synthesizer (=VCO) phase noise
at high offsets
•
Example GSM 900 small MS (= handportable):
wanted signal 3dB above sensitivity level => -102 dBm + 3 dB = -99 dBm
blocking signal -43 dBm @ 600 kHz offset from the received signal
typical demodulation S/N = 9 dB to meet the BER spec
noise BW = 10*log(200 kHz) = 53dB is the GSM receiver BW
Synthesizer phase noise spec @600KHz offset = -102 - (-43) - 53 - 9 = -121
dBc/Hz
Now the noise contribution of the blocking signal is the same as with thermal
noise of the receiver alone (with receiver noise figure NF=10dB) i.e.
-174dBm/Hz + 53dB + 10dB = -111dBm
When two uncorrelated noise sources of -111dBm are present at the same
time the total noise level is -108dBm
Because wanted signal level is -99dBm in blocking conditions the required
S/N of 9dB is satisfied
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 49
About synthesizer specifications 2
•
Example of WCDMA receiver
•
blocking signal level -56 dBm @ 10MHz offset from the received signal
typical demodulation S/N= 7 dB for 10-3 BER
noise BW ≈ chip rate = 10*log(3.84MHz) = 66dB in the WCDMA receiver
wanted signal 3dB above the sensitivity level i.e. -117dBm + 3dB = -114dBm
Similarly to GSM example this gives the synthesizer phase noise spec @10MHz
offset = -117 -(- 56) - 66 - 7 = -134dBc/Hz
If the full processing gain of 10log(3.84Mcps/12.2kcps) = 25dB is taken into
account the requirement is relaxed to -134dBc/Hz + 25dB = -109dBc/Hz !
•
One point worth mentioning is that if synthesizer frequency is double that of LO
frequency the divider by 2 reduces the phase noise theoretically by 6dB. The actual
reduction depends on the noise floor of the divider itself compared to the noise level
of the input signal.
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 50
About synthesizer specifications 3
•
In GSM the modulation spectrum spec typically sets the most difficult requirement for
the synthesizer reference spurioses
•
@ 400kHz offset the modulation spectrum is allowed to have contamination level
of -60dBc measured with 30kHz filter BW
Synthesizer spurious should be < -66dBc @ 400kHz offset
•
Usually the selectivity sets synthesizer spurious spec at high offsets
•
Example GSM 900 small MS:
wanted signal 3dB above sensitivity level => -102 dBm + 3 dB = -99 dBm
blocking signal -23dBm @ 3MHz offset from the received signal
typical demodulation S/N = 9 dB to meet the BER spec
At least 3dB margin is needed because the phase noise and the receiver
thermal noise contribution are present at the same time
Synthesizer spurious spec @ 3MHz offset = -102 - (-23) - 9 - 3 = -91dBc
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 51
LO phase noise
•
LO mixes both with wanted
signal and interfering signal
•
LO spectrum shifts to IF
LO
RX
IF
IF
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 52
Interference
About synthesizer specifications 4
•
In GSM the whole transmitter RMS phase error has to be < 5° and peak < 20°
•
•
•
As an example this can be met if the synthesizer meets approximately the
following spec:
•
output phase noise is < -74dBc/Hz @ 1kHz offset
•
loop BW is < 20kHz with 45° phase margin
According to WCDMA standard the Error Vector Magnitude (EVM) of the transmitter
has to be < 17.5%
•
•
•
The rule of thumb is that synthesizer contribution has to be less than half of that
This equals to RMS phase error of approximately 0.175rad≈ 10°
From that the synthesizer contribution should be less than half
The settling time requirement depends on the system and RF architecture
•
•
© NOKIA
Typically in GSM phone it is around 500us within ±20Hz
Some new GSM Phase 2+ features like HSCSD (multislot) and GPRS (packet
radio) set much tighter requirements for the settling time
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 53
Example of RMS phase error calculation
•
Using FM theory of small modulation indices (β<<1) the single sideband to carrier
ratio L(f) can be expressed as follows
2
2
2
 θ rms 2 
f
∆
 peak 
 θ peak 
θ
β 
 = 20 log rms 
 = 10 log
 = 10 log
10 log  = 10 log
 2 
2
 2
 2 
 2 fm 


• Where β is modulation index, ∆fpeak is peak frequency deviation, fm is modulating
frequency, θpeak is peak phase deviation and θrms is RMS phase deviation
•
For instance single modulating tone of -60dBc results in RMS phase phase deviation
(= RMS phase error) of
L( f ) ≈ 10 log (Ptone Pcarrier ) = −60dB => Ptone Pcarrier = 10 −6 => θ rms = 2 ⋅10 −3 rad ≈ 0.08°
•
By integrating the synthesizer phase noise L(f) over the frequency range of interest
the RMS phase error results
•
•
•
•
The starting point of integration is defined by the length of theTDMA burst
The stop of integration is defined by the symbol length
If synthesizer output phase noise is -71dBc/Hz and loop BW = 50kHz, the noise
integral can be approximated by a rectagle which has an area of -71dB +
10log(100k) = -21dB which is roughly the SNR-1 = (Pnoise / Ptotal) of the synthesizer
SNR = −10 log θ 2 rms = −20 log (θ rms ) => SNR=21dB equals RMS phase error of 5 deg
© NOKIA
(
)
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 54
Literature
•
•
•
•
•
Phase Locked Loops: Principle and Practice, P. V. Brennan, 1996
•
Ulrich L. Rohde, Microwave and Wireless Synthesizers - Theory and Design, John
Wiley & Sons, 1997
James A Crawford, Frequency Synthesizer Design Handbook, Artech House 1994
Floyd M. Gardner, Phaselock Techniques, Second edition, John Wiley & Sons, 1979
Bar-Giora Goldberg, Digital Techniques in Frequency Synthesis, McGraw Hill, 1996
Vadim Manassewitsch, Frequency Synthesizers -Theory and Design, Third Edition,
John Wiley & Sons, 1987
© NOKIA
syntsat.PPT / 15.1.1999 / Kalle Asikainen page: 55