25706CP
25 GHz Latched Comparator
Data Sheet
Applications
•
•
•
•
•
•
Broadband test and measurement equipment
Oscilloscope and logic analyzer front ends
Window comparators
High speed line receivers and signal regeneration
Threshold and/or peak detectors
High speed triggers
Features
•
•
•
•
•
•
Supports clock rates up to 25 GHz
100 ps propagation delay input to output (Clk-Q)
Low power consumption: 550 mW typ.
Fast rise and fall times: 15 ps typ.
Deterministic Jitter: 2.0 ps p-p typ.
Random Jitter 0.2 ps RMS typ.
•
•
•
•
•
•
Hysteresis <5 mV
Output amplitude 1.2 Vpp differential
Supports single-ended and differential operation
Single –3.3 V power supply
Available in LGA package or die
Evaluation board available
Description
The 25706CP is an exceptionally fast latched voltage
comparator with very low thermal hysteresis that
operates with clock rates from DC to 25 GHz. The
part is nominally positive-edge triggered; however,
by reversing the positive and negative clock
connections, a negative-edge triggered application
can be accommodated. All differential analog inputs
and differential clock inputs are DC coupled on-chip
and terminated with resistors to ground. The
differential data outputs should be terminated off
chip with 50 Ω resistors to ground.
The 25706CP operates from a single -3.3 V power
supply and is available in a ceramic land grid array
(LGA) package or in die form. The packaged part
is also available on an evaluation board with SMA
connectors. For customers requiring a
comparator that operates from a +3.3 V power
supply Inphi offers the 25707CP.
Block Diagram
GND
IN+
IN-
In
OUTp
Out
25706CP
Latch
OUTn
Clk In
CLKINp
CLKINn
VEE
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Inphi Proprietary
Page 1 of 15
Absolute Maximum Ratings
•
•
•
Stresses beyond those listed here may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions beyond
those indicated in the “Operating Conditions” and “Electrical Specifications” of this datasheet is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameter
Min
Typ
Max
Unit
VEE
–3.6
---
+0.5
V
IN+, IN-,
CLKIN
–2
---
+0.6
V
DOUT
–3.5
---
+1
V
Operating Temperature (Junction) – Die
TJ
---
---
+175
°C
Operating Temperature (Case) – Packaged
TC
---
---
+125
°C
TSTORE
---
---
+125
°C
RH
0
---
100
%
VEE, GND
>1000
---
---
V
Outputs
>200
---
---
V
Clock & analog inputs
>100
---
---
V
Power Supply Voltage
Analog and Clock Input Signals
Output Signals
Shipping/Storage Temperature
Humidity
ESD protection (HBM)1
Symbol
VESD
Conditions
Notes:
1 As
per JESD22-A114-B. ESD testing has not been completed.
Operating Conditions
•
Important Note: Unused I/O should be terminated with 50 Ω to GND for all specifications to be met.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Power Supply Voltage
VEE
± 5% Tolerance
–3.465
–3.300
–3.135
V
Power Supply Current
IEE
---
167
255
mA
On-Chip Power Dissipation
PD
---
550
800
mW
Operating Temperature (Junction) – Die
TJ
+15
---
+125
°C
Operating Temperature (Case) – Packaged
TC
–5
---
+85
°C
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25706CP_DS_1.1
Inphi Proprietary
Page 2 of 15
DC Electrical Specifications
!
WARNING – To prevent damage to the part:
•
DC power must be turned off prior to connecting or disconnecting any cables.
•
Electrical specifications guaranteed when the part is operated within the specified operating conditions
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Analog Input Specification
Input High Level
VIH
GND referenced
-0.5
---
0.5
V
Input Low Level
VIL
GND referenced
-0.8
---
0.0
V
Input Amplitude1
VINpp
Differential peak-to-peak
---
---
1200
Single ended peak-to-peak
---
---
1000
VOS
---
±1.5
±6
mV
∆VOS/∆T
---
3
---
µV/°C
55
62.5
70
Ω
5
6
mV
Input Offset Voltage2
VOS Temperature Coefficient
DC input resistance
RIN
Input to GND
Measured with DC input and
100 MHz clock
Hysteresis (DC)
mVpp
Clock Specification
Input High Level
VIH
GND referenced
–0.5
---
0.5
V
Input Low Level
VIL
GND referenced
–0.8
---
0
V
Input Amplitude1
VCLKpp
Differential peak-to-peak
300
---
1200
Single ended peak-to-peak
300
---
1000
RCLKIN
Input to GND
45
50
55
Ω
Data Output Amplitude
DOUT
Differential peak-to-peak
1000
1200
1400
mVpp
Output High Voltage
VOH
DC coupled, GND referenced
-85
-55
0
mV
Output Common Mode
VOCM
DC coupled, GND referenced
-425
-360
-300
mV
Output Eye Cross
VOEC
Single-ended measurement
40
50
60
%
DC input resistance
Output
mVpp
Specification3
Notes:
1 Analog and clock input amplitudes <300 mVpp may cause part to fail the following AC electrical specifications:
Clock Phase Margin, Deterministic Jitter, Random Jitter, Clock to Data Output Delay.
2 Typical refers to variance or “1-sigma” value. Expectation value is 0 mV.
3 Outputs are CML and must be externally DC terminated with 50 Ω to GND.
1/31/05
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Inphi Proprietary
Page 3 of 15
AC Electrical Specifications
!
WARNING – To prevent damage to the part:
•
DC power must be turned off prior to connecting or disconnecting any cables.
Electrical specifications guaranteed when the part is operated within the specified operating conditions
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
0 to 13 GHz
14
15
---
13 to 25 GHz
11
12
---
Soak time = 0.1 µs
---
2
---
Soak time = 1 µs
---
12
---
Soak time = 100 µs
---
16
---
25
---
---
GHz
Input Specification
Input Return Loss
Thermal Hysteresis1
RLIN
VTHYS
dB
mV
Clock Specification
Maximum Clock Frequency
fMAX
Minimum Clock Slew Rate
SMIN
At CLKIN zero crossing
---
---
1
V/ns
Clock Input Return Loss
RLIN
0 to 25 GHz
11
12
---
dB
Clock Phase Margin
CPM
25 GHz
305
---
---
deg
tr/tf
20–80%
---
15
18
ps
---
---
---
dB
Output Specification
Output Rise/Fall Time
Output Return Loss6
RLOUT
Deterministic Jitter4
JD
Peak-to-peak
---
2.0
3.5
ps
Random Jitter5
JR
RMS
---
0.2
0.3
ps
Clock to Data Output Delay2
tQ
Die
30
40
50
Packaged
80
100
120
Between 20 and 10 mV overdrive
---
TBD
---
Clock to Data Output Delay Variation2, 3
∆tQ
Notes:
1 See Hysteresis Specification section.
2 Valid when clock to data phase is near center of CPM window. t and ∆t specifications are not fully characterized.
Q
Q
3 Increase of t for transition from –0.5-V input voltage to small positive input voltages, V and V , relative to input
Q
1
2
threshold voltage, where V1 = 20 mV, V2 = 10 mV. See note 1 for determining the threshold voltage.
4 Deterministic jitter measured with a 12.5 Gbps, 27-1 PRBS pattern.
5 Random jitter measured with a 12.5 Gbps, 1010… pattern.
6 See Figure 1 for minimum output return loss specification.
1/31/05
25706CP_DS_1.1
Inphi Proprietary
Page 4 of 15
ps
ps
Output Return Loss Specification
Minimum Output Return Loss Specification
Output Return Loss (dB)
16
12
8
4
0
0
5
10
15
20
25
Frequency (GHz)
Figure 1. Minimum output return loss specification.
Timing Diagram
IN -
1
2
3
4
5
IN+
CLKIN =
CLKINp - CLKINn
50%
50%
1/fCLK
tQ
DOUTn
80%
80%
1
2
20%
DOUTp
tf
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25706CP_DS_1.1
Inphi Proprietary
3
20%
tr
Page 5 of 15
Input and Output Equivalent Circuits
GND
62.5 Ω
GND
62.5 Ω
50 Ω
IN+
CLKINp
IN-
CLKINn
50 Ω
GND
65 Ω
65 Ω
DOUTp
DOUTn
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Inphi Proprietary
Page 6 of 15
Typical Operating Characteristics
Typical Output Waveforms
Figure 2. Output DOUTp data eye from on-wafer
measurement (DC coupled). Source is 10 Gbps 27–1
PRBS pattern (scope view is 100 mV/div, 20 ps/div)
Figure 3. Output DOUTp data eye from on-wafer
measurement (AC coupled). Source is 10 Gbps 27–1
PRBS pattern (scope view is 100 mV/div, 20 ps/div)
DC Characteristics
Output Amplitude (OutP, single-ended) vs. Supply with
Temperature as parameter
VOUTp VOH vs. Supply with Temperature as parameter
-52
T = -5 C
T = -5 C
0.67
-54
T = 25 C
VOUTp VOH (mV)
OutP Amplitude (V)
0.69
T = 85 C
0.65
0.63
0.61
0.59
T = 25 C
T = 85 C
-56
-58
-60
-62
0.57
0.55
-64
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
Power supply (V)
25706CP_DS_1.1
3.2
3.3
3.4
3.5
3.6
Power supply (V)
Figure 4. Output DOUTp amplitude swing (volts
pk-pk) vs. VEE and temperature. Source is 25 Gbps
27–1 PRBS pattern.
1/31/05
3.1
Figure 5. Output DOUTp HIGH voltage (volts
DC) vs. VEE and temperature. Source is 25 Gbps
27–1 PRBS pattern.
Inphi Proprietary
Page 7 of 15
Typical Operating Characteristics
Eye Crossing (OutP) vs. Supply with Temperature as
parameter
VOUTp Common Mode Voltage vs. Supply with
Temperature as parameter
60.0
-358
Eye Crossing (OutP) (%)
VOUTp Common Mode Voltage (mV)
-356
-360
-362
-364
-366
T = -5 C
-368
T = 25 C
-370
T = 85 C
-372
55.0
50.0
T = -5 C
45.0
T = 25 C
T = 85 C
-374
40.0
-376
3.0
3.1
3.2
3.3
3.4
3.5
3.0
3.6
3.1
3.2
3.3
3.4
3.5
3.6
Power supply (V)
Power supply (V)
Figure 7. Output DOUTp data eye crossing vs.
VEE and temperature. Source is 25 Gbps 27–1
PRBS pattern.
Figure 6. Output DOUTp common mode voltage
(volts DC) vs. VEE and temperature. Source is 25
Gbps 27–1 PRBS pattern.
Power Dissipation vs. Supply with Temperature as
parameter
0.75
Power Dissipation (W)
0.70
T = -5 C
0.65
T = 25 C
T = 85 C
0.60
0.55
0.50
0.45
0.40
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Power supply (V)
Figure 8. Power dissipation of the 25706CP (W) vs.
VEE and temperature.
1/31/05
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Inphi Proprietary
Page 8 of 15
Typical Operating Characteristics
AC Characteristics
Peak-to-Peak Jitter (OutP, 2^7-1 patt.) vs. Supply with
Temperature as parameter
3.5
Random Jitter (outp) vs. Supply with Temp. as
parameter
220
Random Jitter (RMS in fs)
Peak-to-Peak Jitter (ps)
T = -5 C
3.0
2.5
2.0
T = -5 C
1.5
T = 25 C
T = 85 C
215
T = 25 C
T = 85 C
210
205
200
195
190
185
1.0
3.0
3.1
3.2
3.3
3.4
3.5
3.0
3.6
3.1
Power supply (V)
3.3
3.4
3.5
3.6
Power supply (V)
Figure 9. Output DOUTp deterministic jitter as
measured on the oscilloscope (ps pk-pk) vs. VEE
and temperature. Source is 25 Gbps 27–1 PRBS
pattern. Measurement includes deterministic jitter
of source and test equipment.
Figure 10. Output DOUTp random jitter (ps RMS)
vs. VEE and temperature. Source is 25 Gbps 27–1
PRBS pattern. Measurement includes random jitter
of source and test equipment.
Rise Time (OutP) vs. Supply with Temperature as
parameter
Phase Margin vs. Supply with Temperature as parameter
330
17.0
T = -5 C
16.5
Phase Margin (degrees)
Rise Time (OutP) (ps)
3.2
T = 25 C
T = 85 C
16.0
15.5
15.0
14.5
328
T = -5 C
326
T = 25 C
324
T = 85 C
322
320
318
316
314
312
310
14.0
3.0
3.1
3.2
3.3
3.4
3.5
3.0
3.6
Figure 11. Output DOUTp rise time (ps) vs. VEE
and temperature. Source is 25 Gbps 1010…
pattern.
1/31/05
25706CP_DS_1.1
3.1
3.2
3.3
3.4
3.5
3.6
Power supply (V)
Power supply (V)
Figure 12. Analog input to clock input phase
margin (degrees) vs. VEE and temperature. Source
is 25 Gbps 27–1 PRBS pattern.
Inphi Proprietary
Page 9 of 15
Typical Operating Characteristics
Hysteresis Characteristics
Hysteresis versus Soak Time
Delta VOUT versus Delta VIN
20.00
0.8
16.00
55 C
0.4
Delta Vout (V)
18.00
25 C
85 C
0.2
0.0
-0.2
-10
-5
0
5
10
Data Hysteresis (mV)
0.6
-5 C
-0.4
14.00
12.00
10.00
8.00
6.00
4.00
2.00
-0.6
0.00
(µs) 0.001
(Mbps) 1000
-0.8
Delta Vin (mV)
Figure 13. Typical analog input (IN+) DC
hysteresis on the 25706CP. For this measurement,
the offset voltage was calculated from the swept
data by taking the average of the threshold for the
positive and negative sweep. The difference between
the thresholds is the hysteresis.
0.01
100
0.1
10
Data Soak
1
1
10
0.1
100
0.01
Figure 14. Analog input (IN+) thermal hysteresis
on the 25706CP is shown as a function of input
soak time in µs (and equivalent data rate in Mb/s).
Input used was a 1010… square wave pattern at
varying data rates. Clock frequency set to 1 GHz.
S-Parameter Characteristics
Data Output S22 Amplitude
0
0
-5
-5
-10
-10
S22 amplitude (dB)
S11 amplitude (dB)
Analog Input S11 Amplitude
-15
-20
-25
-30
-35
-15
-20
-25
-30
-35
-40
-40
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
5
Frequency (GHz)
25706CP_DS_1.1
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Frequency (GHz)
Figure 15. Input Return Loss under typical VEE
and temperature conditions.
1/31/05
6
Figure 16. Output Return Loss under typical VEE
and temperature conditions.
Inphi Proprietary
Page 10 of 15
0.980 mm
Die Pad Layout
GND
VEE
VEE
GND
GND
VEE
VEE
GND
1
24
23
22
21
20
19
18
GND
GND
2
17
IN-
DOUTp
3
16
IN+
DOUTn
4
15
65 ± 5 µm
(4 sides)
GND
GND
5
14
GND
GND
6
7
CLKINp
8
CLKINn
GND
VEE
VEE
GND
9
10
11
12
13
1.280 mm
Notes:
1.
2.
3.
Numbers correspond to 100 µm squares on 150 µm pitch.
Pad outer dimensions fit either to squares or to rectangles enclosing two adjacent squares.
Die thickness = 150 ± 10 µm.
Name
Pad Square
Number
IN-
3
Inverting analog input. Internally terminated 65 Ω to GND.
Input
IN+
4
Non-inverting analog input. Internally terminated 65 Ω to GND.
Input
CLKINp
8
Non-inverting clock input. Analog input is latched onto the rising edge
of this input signal. Internally terminated 50 Ω to GND.
Input
CLKINn
9
Inverting clock input. Analog input is latched onto the falling edge of
this input signal. Internally terminated 50 Ω to GND.
Input
DOUTp
16
Non-inverting data output. Back terminated 60 Ω to GND. Always
terminate to 50 Ω to GND.
Output
DOUTn
15
Inverting data output. Back terminated 60 Ω to GND. Always
terminate to 50 Ω to GND.
Output
GND
VEE
1/31/05
Description
1, 2, 5, 6, 7, 10,
13, 14, 17, 18, Ground.
21, 22
11, 12, 19, 20,
Power Supply: Connect to –3.3 V.
23, 24
25706CP_DS_1.1
Inphi Proprietary
Function
Supply
Supply
Page 11 of 15
Die Pad Locations
For dimensioning purposes, reference origin (0, 0) is the lower left corner of the lower left pad.
Pad Lower Left Corner
1/31/05
Pad #
Signal
X
Y
1
GND
0
750
2
GND
0
600
3
IN-
0
450
4
IN+
0
300
5
GND
0
150
6
GND
0
0
7
GND
150
0
8
CLKINp
300
0
9
CLKINn
450
0
10
GND
600
0
11
VEE
750
0
12
VEE
900
0
13
GND
1050
0
14
GND
1050
150
15
DOUTn
1050
300
16
DOUTp
1050
450
17
GND
1050
600
18
GND
1050
750
19
VEE
900
750
20
VEE
750
750
21
GND
600
750
22
GND
450
750
23
VEE
300
750
24
VEE
150
750
25706CP_DS_1.1
Inphi Proprietary
Page 12 of 15
LGA Pinout
Name
Pin
Description
Function
IN-
5
Inverting analog input. Internally terminated 65 Ω to GND.
Input
IN+
3
Non-inverting analog input. Internally terminated 65 Ω to
GND.
Input
CLKINp
26
Non-inverting clock input. Analog input is latched onto the
rising edge of this input signal. Internally terminated 50 Ω to
GND.
Input
CLKINn
24
Inverting clock input. Analog input is latched onto the
falling edge of this input signal. Internally terminated 50 Ω
to GND.
Input
DOUTp
17
Non-inverting data output. Back terminated 60 Ω to GND.
Always terminate to 50 Ω to GND.
Output
DOUTn
19
Inverting data output. Back terminated 60 Ω to GND.
Always terminate to 50 Ω to GND.
Output
GND
1, 2, 4, 6, 7, 9, 12, 13,
16, 18, 20, 21, 23, 25, Ground
27, Paddle
VEE
10, 11, 22
NC
8, 14, 15, 28
1/31/05
25706CP_DS_1.1
Power Supply: Connect to –3.3 V
Not Connected
Inphi Proprietary
Supply
Supply
NC
Page 13 of 15
LGA Package Mechanical Drawing
Top View
Side View
Side View
1/31/05
25706CP_DS_1.1
Bottom View
Inphi Proprietary
Page 14 of 15
Order Information
Part No.
Description
25706CP-S01D
25 GHz Latched Comparator (–3.3 V Supply) – Die
25706CP-S01L
25 GHz Latched Comparator (–3.3 V Supply) in LGA Package
25706CP-S01LEVB
25 GHz Latched Comparator (–3.3 V Supply) in LGA Package on an
Evaluation Board with SMA Connectors
Contact Information
• Phone:
• Fax:
• E-mail:
Inphi Corporation
2393 Townsgate Road, Suite 101
Westlake Village, CA 91361
(805) 446-5100
(805) 446-5189
products@inphi-corp.com
‚Visit us on the Internet at: http://www.inphi-corp.com
For each customer application, customer’s technical experts must validate all parameters. Inphi Corporation reserves the right to change
product specifications contained herein without prior notice. No liability is assumed as a result of the use or application of this product.
No circuit patent licenses are implied. Contact Inphi Corporation’s marketing department for the latest information regarding this product.
Limited Qualification Notification
NOTE: The 25706CP has been tested to meet the DC and AC electrical specifications outlined in this data
sheet and a characterization report is available. While the 25706CP has not undergone full qualification
testing (i.e. it has not been subjected to high temperature operation life test), a number of other products
fabricated in the same semiconductor process and packaged in the same ceramic LGA package have
completed full qualification testing and have been demonstrated to be reliable. Contact Inphi Corporation
for more details.
Updates To Version 1.0
1. Corrected block diagram on page 1.
2. Changed DC electrical specification tables on page 3 based upon recommendations in the
characterization report. Specs changed are: Input VIH, Input VIL, Input VOS, Input ∆VOS/∆T, Clock
Input VIL, Output DOUT, Output VOH, Output VOCM.
3. Changed AC electrical specification tables on page 4 based upon recommendations in the
characterization report. Specs changed are: Clock CPM, Output RLOUT.
4. Added figure 1 – minimum output return loss specification – on page 5.
5. Added data on DC hysteresis (spec on page 3 and new diagram on figure 12).
6. Clarified previous “hysteresis” spec entries as “thermal hysteresis” (page 4 and figure 13).
7. Removed “Hysteresis Specification” section – moved to the application note instead.
1/31/05
25706CP_DS_1.1
Inphi Proprietary
Page 15 of 15