Advanced Technology Group
Radiation Hardened Microelectronics Program:
A Status Report
Presented at the Annual
Microelectronics Reliability and Qualification
Workshop
11-12 December 2012
RHM Branch Mission, Objectives & Applications
Mission: Develop both evolutionary and revolutionary
microelectronics technologies to enhance satellite electronic
systems capabilities
•
• Objectives:
• Onboard Processing (OBP) Enhancements:
• Provide heterogeneous OBP capability to support TFLOP
performance & TB storage at reduced SWaP
• Provide high performance analog/mixed-signal technologies to
support communications and intelligence applications
• Electronically Steerable Array (ESA) Enablement:
•Very high SFDR low power CNT FET technology for LNA, mixer
and ADC designs
• UDSM technology for elemental digital beam-forming
• Applications:
•System survivability
•Pre-planned program upgrades by providing improvements in
performance, reliability & SWaP
• New mission capabilities
Near Term Technology Program
Objective:
• Productization & Qualification of RH Electronics Technologies (250nm
to 150nm)
• 10X improvement in OB processing performance
Tasks:
•
•
•
•
•
•
•
•
•
•
•
RH15F Process Class V Qualification
L2 Cache MCM/Synchronous SRAM Qualification
4Mb CRAM Qualification
RH18/RAD750 200MHz/400MIPS Processor Qualification
100 MHz Bridge ASSP Development
RAD750/250MHz 500 MIPS processor
RH SERDES Development
Structured Array Development
Optimized SERDES Development
Advanced Packaging Development
HX-5000 SEE Characterization
Near Term Program Status
Balanced design to support > 400 MIPS Throughput
Spacecraft Front-end & Processing

L2 CACHE Memory
Class Q Qualification
Completed

RAD750
200MHz/400MIPS
Class Q Qual
4QCY12


100MHz Bridge Chip
Class Q Qual
4QCY12
RH 16Mb (X32) SRAM
Class Q Qual
4QCY12
SERDES Test Chip
X
BAE SYSTEMS
RH SERDES
Pass 2 Completed
Class Q Qual
4QCY12

RH15F Class V
Qual Completed
RH 4Mb NVRAM
Class Q & V Quall
Completed

RH15 Class V
Qual Complete

Structured Array
Complete
FPGA Replacement

5Gbps SERDES
Design Complete
Demo 2QCY13
Mid/Far Term Technology Program
Objective:
•
Demonstration of technology to provide a heterogeneous, flexible >
TFLOP OBP architecture to support full range of processing needs
(MIPS to TIPS)
Adaptation of Commercial Processes & IP for Space Applications
>1000X in OB processing performance; > TFLOP OBP performance
•
Demonstration of high performance AMS technology
GSPS wide-band ADC/DAC
Tasks:
•
•
RHBD 90nm & 45nm 70/250GFLOP DSP
•
RHBD 45nm Next Generation multi-core GPP Family
•
RHBD 45nm ASIC Design, Demonstration and Qualifcation
•
RHBD 45nm/32nm Next Generation Analog/Mixed-Signal Technology
Development
•
RHBD 90nm Reliability Investigation & QML Qualification Support
•
RHBD Next Generation FPGA Investigation
RHBD Vector Processor Host Bridge
RHBD 45nm ASIC Development Technical Approach
In production
since 2009
Freescale 45nm
Physical IP
• Combinational and
sequential standard cells
• LVCMOS I/O
• 5 Gbps multi-protocol, multirate SerDes
• Single Port SRAM compiler
• Dual Port SRAM compiler
• PLL
• SSTL I/O
• DDR3 I/O
• CML I/O
• USB phy
• Register File
• ROM
• CAM
Freescale and
BAE Systems High Level IP
BAE Systems
45nm Physical IP
+
• SEU/SET hardened
sequential cells
• SEU hardened PLL / SerDes
• LVDS I/O
• Upgrades to EM for 15 year
missions at 125°C
• Upgrades to Vth for low
leakage
+
• Multiple memory controllers:
SRAM, SDRAM, DDR2/3, DDR3/3L, Flash
• 32-bit Embedded microcontroller (EMC)
• Pattern matching engine
• Multiple I/O protocols:
Serial RapidIO (sRIO), SpaceWire,
PCI 32/64, UART, JTAG, I2C
• On-Chip Bus
Proven on
multiple ASICs
Ready for space…
…and long missions.
• Optimal system size, weight and power through 45nm SOI technology
• Lower program risk through reuse of proven library elements
• High reliability for 15 year missions through enhancements
• Excellent radiation tolerance through direct proton ionization immunity and selective SEU/SET hardening
The combination of a SOC proven 45nm ASIC library and improvements for radiation and
reliability provide an extensive capability for demanding space missions
Mid/Far Term Program Status
RHBD < 90nm technology to support ESA, Signal Conversion, Data Storage &
OBP Applications
RH OBP Board
4- 70/250GFLOP DSPs + Host Bridge Spacecraft Front-end & Processing
~ 1TLOP Performance/BD
(> TFLOP/Box )
RHBD 90/45nm GFLOP DSP
70/250 GFLOP
RHBD 90nm devices in test
RHBD 45nm DSP Host
Demo 4QFY14
Next Gen RH
Reprogrammable
FPGA
FY12 Architecture
Investigation
RHBD 45nm GPP
RAD55XX Family
RHBD 45nm Mixed-Signal
technology for SIGINT,ESA & COMM
Applications
RHBD 45nm
ASIC Design &
Demonstration and
Qualification Effort
4QFY14
RHBD 90nm/45nm Onboard Processing & Control
Technology Development & Demonstration Program
• Program Objectives
• Design, development, demonstration and verification of a
RH, flexible and heterogeneous architecture onboard
processing capability to meet the full range of satellite
payload processing and control function needs (MIPS to
TIPS)
• Technical Approach
• Combines advanced commercial DSP & GPP IP with RHBD
45nm technology to achieve program objectives
• Develop and demonstrate:
• GFLOP DSP (90nm mid term& 45nm far term)
• Host Bridge to support TFLOP SBC capability
• MIPS to GIPS GPP family
• GPP SBC
• RH DDRX Controller
RHBD 90nm RADSPEED™ SIMD DSP
The RADSPEED DSP is a radiation hardened variant
of the CSX700 digital signal processor (DSP) from
ClearSpeed Technology
RADSPEED DSP features @ 90nm
• 160 (152 + 8 spare) processing elements (PE) in
two multi-threaded array processors (MTAP)
• Throughput: 70 GFLOPS @ 15 W power
dissipation
• Each PE incorporates double precision floating
point hardware as well as integer processing
• Single instruction, multiple data (SIMD)
architecture
• Dual ClearConnect™ bridges (CCBR)
Each with ~ 30 Gb/s throughput
Supports direct connection between
DSPs or to a backplane using a bridge
•
Dual DDR2 DRAM interfaces
A DDR2 interface is dedicated to each MTAP, avoiding
bottlenecks
Throughput: ~30 Gb/s each
Supported by mature commercial software
development kit
Software prototyping hardware available now
RADSPEED DSP
block diagram with
detailed PE
The RADSPEED DSP chip includes two independent cores, each with 76 parallel
processing engines, and dual high performance memory and I/O ports
RADSPEED-HB™ host / bridge ASIC architecture
Dual CCBR interfaces to RADSPEED DSP
chips (30 Gb/s each)
• Full duplex double data rate wide parallel
point to point connection
Four “x4” serial 3.125/5 GHz RapidIO 2.1
interfaces plus a spare x4 (40-64 Gb/s total)
Control Plane provided through SpaceWire
interface
DDR2/3 SDRAM memory controller with
SECDED ECC (up to 50 Gb/s)
Startup ROM and Flash controllers for
interfacing with boot and non-volatile memory
Multiple 64-bit RAD5500™ Power Architecture
processor cores:
•
•
•
Setup RADSPEED DSP operations
Control data transfers to/from Serial RapidIO
backplane
Supplement data processing where more efficient
Host debug port to RADSPEED DSP and JTAG
interface for debug and test
Real time trace provides access to internal nodes
Preliminary block diagram
RADSPEED-HB status:
In design now
Prototypes: 2014
• The RADSPEED-HB is built upon
Freescale QorIQ™ architecture
The RADSPEED-HB ASIC sets up the RADSPEED DSP, provides a high speed path to and
from a RapidIO backplane, and provides high performance general purpose processing
Processor Family Development –
RAD 5545 – 32/64bit multi-core Processor
Processor Family Development RAD 5510 – 32/64bit Processor
DSP Flight Board Block diagram & Model
RAM
Dual DSP RAM
RADSPEED
DSP
RADSPEED
DSP
RAM RADSPEED-HB
NVRAM
ASIC
ASSP
RAM
ASIC
sRIO
backplane
RHM Program Satellite Processing & Control Systems
(MIPS to TIPS)
RAM
FPGA
Solid State Recorder
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
Communications I/F
Golden
Gate
Bridge
RAD5545
processor
RAM NVRAM
RapidIO
ASIC
Single Board Computer
RAD750
CPU +
RAM L2 cache
NVRAM
Golden
Gate
Bridge
RAM RADSPEED-HB
NVRAM
ASIC
SpaceWire
Router
ASIC
Payload I/O
Sensor
RAM RAD5545
NVRAM processor
Sensor
Sensor
Serial RapidIO
ClearConnect bridge
Analog
Sensor
D/A
converter
Analog
Actuator
SpaceWire
endpoint
ASIC
w/PCI
I/F
Golden
Gate
Bridge
NVRAM
NVRAM
NVRAM
NVRAM
NVRAM
NVRAM
Instrument Control
45nm Front End
Processor ASIC
Payload Processor
Golden
Gate
Bridge
A/D
converter
Non-volatile Memory
Single Board Computer
RAD750
NVRAM
CPU +
RAM L2 cache
RadRunner
FPGA
Programmable I/O
SpaceWire
Analog
IMU
Analog
Sensor
GNC I/F
Bus Electronics
Sensor
45nm
Comm
ASIC
Antenna
Switch
Fabric
RAD5510
processor
RAM NVRAM
Digital
Sensor
Star
Tracker
A/D
converter
Analog
Sensor
D/A
converter
Analog
Actuator
1553
PCI
The Rad Hard By Design 45nm Library Development program provides the
technology required for low power, high performance, high density ASIC solutions.
RHBD 45nm ASIC Development, Demonstration
& Qualification Program
Program Objectives
• Development, demonstration, and Class Q/V qualification of a
RHBD 45nm ASIC technology.
Program Tasks
• Radiation & Reliability Technology Assessment & Characterization
Reliability assessment and remediation
RHBD library development & demonstration
Radiation effects modeling and simulation
• RHBD ASIC Design and Demonstration
Design, fabrication and test of two ASICs
Package development and demonstration
• ASIC & Technology Qualification
QML Class V qualification
QML Class Q ASIC qualification
Design flow qualification
RH45 ASIC Library Description
Reliability Enhancements to RH45 ASIC library and custom circuitry
– Selective metal width updates and modifications for electro-migration (EM)
– Lower VDD (0.95V nominal) to limit NBTI/GOI effects
– Enhanced design methodology (e.g. power aware placement) for reduction of hot spots
– Power grid segmenting to control power and thermal profile
– Avoiding (and identifying / updating) circuit topologies that may impact reliability (e.g. voltage stacks)
– Limiting I/O ranges
– Package / image co-design (board / package / image when applicable)
Combinational Cells
• I/O
• Full family : INV, AND, NAND, OR, NOR, BUF, AO, AOI,
– LVCMOS with programmable voltage
OA, OAI, XOR, XNOR, FA, HA, MUX2, MUX4, TIE
and drive
• Data-path enhancement family: ADDRs, MAJs, MUXs,
– Low power LVCMOS
others
– SSTL (DDR2 and DDR3 support)
Clock Cells
– LVDS
– Schmitt Trigger
• INV, NAND, NOR designed for radiation hardness
– PCI
• Proper EM consideration for 20 year lifetime
• Glitch-less hardened clock gates for power reduction
• Support Cells
Sequential Cells
− Voltage island isolation
• D Flip-flops (DFFs) and Latches
− Delay cells
− Antenna cells
• Scan or non-scan, set, reset, set-reset
− Filler cells
• With or without Single Event Transient (SET) filters
− ESD structures
• Soft latches and DFFs available for non-hardened paths
− E-fuse
RHBD AMS Design, Development & Demonstration Program
Program Objective
• Investigate the use of < 45nm technology to support AMS requirements to
include:
• Very high sample rate (> 25 Gsps) moderate ENOB
• High sample rate (> 1.5 Gsps) high ENOB
• Very high sample rate & very low power elemental digital beam
forming (eDBF) applications
Technical Approach
• Test and analysis through
• Critical circuit (e.g., PLL, S/H, etc) design, fabrication, test and
characterization
• Analog to Digital Converter architecture (ADC) Analysis
• 1-3 bit/ > 20 Gsps W-ADC Arch. Design
• 10/14 bit/1.5 Gsps W-ADC Evaluation
• Commercial ADC Benchmark/Qualification
• High sample rate ADC and digital filter architecture investigation
Mid/Far Term RHM Program Roadmap
2011
2012
2013
2014
2015
2016
2017
2018
2019
3 2 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2
Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
90nm
GLOP DSP
Prototype
Complete
90nm DSP
GLOP T&E
Complete
45nm
Reliability
Assessment
45nm IP
Library
Transfer
Initiate
GPP
Design
Complete
Start
90nm
45nm
GFLOP DSP
GLOP DSP
Qualification
Complete
45nm RHBD
ASIC Demo
Complete GPP
Design & Initiate
Fabrication
Complete
ESA moon-bit
ADC study
Complete
Initial COMM
ADC study
Complete
45nm
RHBD ASIC
Qualification
45nm
GLOP DSP
Prototype
Complete
45nm
GLOP DSP
GLOP T&E
RHBD 45nm ASIC
Demonstration &
Qualification
Complete
45nm
GFLOP DSP
Qualification
RHBD GLOP DSP
Demonstration &
Qualification
RHBD 45nm Host Bridge &
GPP Demonstration &
Qualification
Complete
GPP (5545)
Qualification
Complete
Complete
SBC
HB
Qualification Qualification
Complete
SIGINT ADC
Qualification
Complete
COMM
Demo
RHBD < 45nm AMS
Demonstration &
Qualification
Complete
Complete
COMM AMS ESA moon-bit
Qualification ADC Demo
Complete
SIGINT AMS
Qualification
Disruptive Technologies Program
Objective:
• Develop and demonstrate Disruptive Technologies for Space
Applications
• High SFDR @ low power CNT FET LNA, Mixer & ADC
• RH non-volatile & low power memory
Tasks:
• CNT Non-volatile Memory
4Mb/64Mb NRAM
1G DDRX SDRAM
• CNT FET Technology
Low power mixer
High SFDR ADC
Disruptive Technologies Program Status
Spacecraft Front-end & Processing
CNT FET LNA +Mixer + ADC
2
Spectrum
1
1000X reduction in power @ > 40dbm SFDR
When compared to traditional semiconductor technologies
CNT 4M NRAM
Demo 2QFY12
64M NRAM FY14
1G SDRAM FY16
Improvement in the Frequency Performance of
CNT FETs
4.2 GHz
3.8 GHz
Hero
Device
F max (GHz)
4
3
Average
Device
8 µm Channel
3 µm Channel
2
1.3 GHz
2 GHz
0.95 GHz
1
1 GHz
0.5 GHz
0.4 GHz
2009
2010
2011
2012
Time (Year)
21
CNT Microelectronics Technology Roadmap
2007
NRAM™ Fully
Integrated Circuit
2008
2009
2010
2012
2014
2016
4Mb RT NRAM™ Design & Production
4Mb RH NRAM™
Design
Why CNT Technology?
•Rad hard
• Non-volatile storage
• High switch speed
• Highly scalable
• Easily integrated into
silicon technology
• ~ zero leakage current
• Low interconnect
resistance
• Highly linear operation @
low power for mixers & LNA
applications
4M NRAM
Fully functional
NRAM
Demonstrated
4QFY12
4Mb RH NRAM™
Fabrication
Space Qual
64Mb RH NRAM™
e-NRAM™
RH FPGA
256Mb NRAM/
1Gb RH SDRAM/
Embedded CNT NRAM technology Development
CNT FET Technology to support memory demonstrations (w/ ~ 30% increase in density) and
analog mixed-signal circuit development
4Mb NRAM® Description
Fabricated on 8” wafer
67 usable die per wafer for wafer-scale testing and/or packaging 4Mb
test chips
8-1Mb NRAM® arrays with up to 4-1Mb arrays used for error
detection and correction
32 databit I/O architecture
Test register implementation to accommodate standard and multiple
special test and debug modes
Significant enhancements to improve operability and function from
1Mb test chip predecessor
LBL
LSL
LWL
CNT
NRAM CNT Memory Cell Schematic
First packaged parts in testing
UNCLASSIFIED
NRAM functional verification
64 NRAM® bits tested per data
point
Multiple die and array tested to
verify NRAM® operability
Consistent 100% w0 yield (OFF) performance
D31
…
…
…
D0
1Mb array
w1 yield (ON) performance; > 95% yield across die
D31
…
LOCKHEED MARTIN PROPRIETARY INFORMATION
…
…
D0
Memory Development Tasks
DDR2 SDRAM
Design In-progress
CNT NRAM
64Mb NRAM
Design Complete
Summary
The RHM Program is addressing DoD and IC RH microelectronics
needs through a variety of technical thrusts:
• Near term P&Q, Yield enhancement and optimization tasks are
underway to exploit 250nm, 180nm and 150nm technologies at
BAE Systems and Honeywell
• Mid-term efforts to adopt advanced commercial technologies,
e.g., DSP, FPGA, microprocessors, for space system
applications, i.e., redesign to address radiation effects, power
restrictions and reliability.
• Mid to Far term investigate and demonstrate the use of highly
scaled & disruptive technologies, e.g., CNT, to support various
spacecraft applications, e.g., OBP, ESA enablement, DSU.
CLASSIFY AS APPROPRIATE ON MASTER SLIDE