Pulsar 2b AMchip05-based
Pattern Recognition Mezzanine
Daniel Magalotti
OUTLINE
• Introduction and motivation
• Description of the architecture and design of
Pattern Recognition Mezzanine
•
Activity: Design of the board (Perugia)
• Preliminary test
•
Activities: Power consumption, Serial link test, AM chip JTAG, AM
links, Realistic test - Test stand (Pisa & Perugia)
• Firmware implementation
•
Activities: Top Level Definition, Data flow management (Finite State
Machine), Aurora protocol definition (Pulsar Protocol), Data
Organizer and Track Fitter implementation (Perugia & Pisa)
• Future plan
2/10
Introduction
GOAL: design of a system integrating all the operations and functionalities of the
track reconstruction in a single mezzanine by minimizing the processing latency
• The track reconstruction is divided in two sequential steps

pattern reconstruction by using Associative Memories
 track fitting by using FPGA devices
PULSAR IIB
3/10
Design of the board
14 layers
6 links @ 8 Gbps
FMC connectors
32 links @2 Gbps
AMChip group
FPGA
XC7K335TFG901
Power group
Schematic definition: Daniel Magalotti & Alberto Annovi
Check schematic: FNAL
Layout design: Daniel Magalotti
Little interaction with Andrea Papi…
4/16
Input data distribution
• Half part of the PRM mezzanine
• Dedicate transceiver for each
input of AM chip bus
− 8 links@2 Gbps to serve all
the 8 input buses
• Latency connections
reduction:
(*)
− “fanout buffer” to transmit
input signal to the AM chip
(propagation delay of a
“fanout buffer” = 380ps)
• Total bandwidth(after the
splitting ) = 128Gbps (with
reference to half mezzanine)
− 8 buses x 8 AM chip
@2Gbps
5/16
Output data distribution
6/16
Preliminary test
• Test setup with the loopback card. The loopback provides the
power, the 3.3 V and 12 V, to the PRM mezzanine.
Preliminary test
• Check the FPGA configuration by using JTAG
programming header
• Check the system clock distribution and the GTX
clock distribution
• Measure the power consumption
• Check the outputs of the power regulators
• High speed interface test by using Xilinx IBERT
environment
7/13
Power consumption: what we measure
• FPGA programmed with the correct pin assignment
•
The GTX implemented at 2Gbps to/from AM and at 8 Gbps to/from
Pulsar
Input voltage
Voltage
Watt
0.36 A @
12 V
6.25 A @
3.3 V
Voltage
s
# 16
AM05
Fanout
FPGA
TOTAL
4.3 W
1V
-
-
4.3 W
4.3 W
20.6 W
1,2 V
-
-
9.4W
9.4 W
2,5 V
-
-
3,3 V
-
11.2 W
11.2 W
• We expect that the power consumption of 1V for the FPGA
increases when the logic block of the firmware will be
implemented but not the I/O.
8/10
Serial link test
• The input/output links are tested in loopback considering different
speeds and for both connectors.
• For each connectors we have 3 input links and 3 output link
Loopback test @ 8 Gbps
FMC (U76)
Link0
Link1
Link2
FMC (U73)
9/16
Mezzanine test stand
The Virtex6 firmware was changed to cope with the
mezzanine test
• JTAG mainly software managed, no changes in the
firmware
• JTAG links pass trough the Kintex7 and reach the AM
chips
• Currently only the reset of Kintex7 GTX is done via
Virtex6 software
TEST: Daniel Magalotti & Giacomo Fedi
10/13
AM chip JTAG
• JTAG commands are wrapped into IPbus packets and sent to the
Virtex6 (evaluation board) where the JTAG commands are
unwrapped and interpreted by a FSM. The JTAG connections pass
through the FMC connector and the Kintex7 (mezzanine) and reach
the 4 AM chips in daisy-chain.
• Actions:
•
•
•
•
•
The single-test-chip Python scripts have been modified to work with a chain
of 4 chips
Retrieving of IDCODEs
Configuration of AM chip SerDes:
PRBS test (in/out)
Normal operation (IDLE)
Report on 2nd year Ph.D. research activity
11/13
AM chips -> FPGA links
• Each AM chip:
8 SerDes input -> 8 links FPGA -> AM chips (fanouts)
• 1 SerDes output -> 4 links AM chips -> FPGA
•
• SerDes are configured to run @ 2Gbps
Can be configured in normal operation (IDLE) and in PRBS test
• Using a LeCroy 8 GHz Serial data analyzer we tested an output link near the
FGPA
•
• No errors measured in 8 hours BER<10-14
12/13
Realistic test - Test stand
• Goal: emulate the pulsar using the Virtex6 evaluation board
Schematic definition: Daniel Magalotti
Layout design: Daniel Magalotti
Little interaction with Andrea Papi…
13/13
Firmware implementation
14/13
Firmware implementation
FSM design: Daniel Magalotti DO+TF: Chrisots Gentos OTHERS: Guido Magazzù
Future plan
• 1 year of post-doc
50% Associative Memory project
• 50% RD53 project
•
• 50% Associative Memory project
Test stand in Perugia, evaluation card + PRM card
• Design of the FW for implementing Finite State
Machine
• Definition of the specification for the AM06 PRM
design in collaboration with the Karlsruhe group
•
• 50% RD53 project
•
Supervision of P. Placidi
16/10