A 33-mW 12-Bit 100-MHz Sample-and-Hold Amplifier
Cheng-Chung Hsu and Jieh-Tsorng Wu
Department of Electronics Engineering
National Chiao-Tung University, Hsin-Chu 300, Taiwan
Abstract — A high-speed high-resolution sample-and-hold
amplifier (SHA) is designed for time-interleaved analog-todigital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the requirements for the opamp, resulting in low power dissipation.
Implemented in a standard 0.25 µm CMOS technology, the
SHA achieves 73 dB SFDR for 2 Vpp input at 100 MHz sampling rate. The performance is not degraded for input’s frequency up to the Nyquist frequency. Power consumption is
33 mW from a single 2.5 V supply.
Vi1
2
1
B1
S1
S9
C
1a S3
VCMI
Vo2
S4
C
Vi2
B2
S2
L1
Vo1
1a
1
C
s1
s2
2
C
L2
S10
Introduction
As shown in Fig. 1, the time-interleaved analog-to-digital
converter (ADC) uses M identical N-bit ADCs operating in
parallel at fs /M clock rate to achieve an equivalent f s sampling rate and N-bit resolution. The input sample-and-hold amplifier (SHA) is used to eliminate the effect of sampling phase
inaccuracy among the M individual ADC channels [1]. The
design of the input SHA is crucial since it operates at f s clock
rate and needs to have N-bit resolution. In cases of broadband
communication systems, the input signal may have bandwidth
more than fs /2.
High-speed SHAs usually operate in open-loop architecture.
The resolution of the SHAs is limited to 8–10 bits due to the
non-ideal effects of switches such as charge injection and clock
feedthrough [2][3]. On the other hand, high-resolution SHAs
usually operate in closed-loop architecture. The speed of the
SHAs is determined by the performance of the opamps used
[4][5]. The opamps are designed based on the requirements
of dc gain, bandwidth, slew rate, output voltage swing, noises,
and under the constraint of supply voltage.
This paper describes the design of a SHA suitable for
the time-interleaved ADC applications. The SHA employs
the closed-loop configuration to achieve high resolution. By
precharging the capacitive loads, the settling time in the hold
SHA
N-Bit A/D (2)
fs
N-Bit A/D (M)
fs / M
Fig. 1. Time-interleaved ADC.
MUX
Vin
MUX
N-Bit A/D (1)
Do
Fig. 2. The conventional flip-around SHA.
time can be reduced. In addition, the purposed architecture
also mitigates the requirements for the opamp used.
Conventional Flip-Around SHA
The conventional flip-around SHA shown in Fig. 2 has
been extensively employed for high-speed and high-resolution
CMOS SHAs [4][6]. When φ 1 = 1, the SHA is in the sample
mode, and the input is sampled on the C s1 and Cs2 capacitors.
When φ2 = 1, the SHA is in the hold mode, the sampling capacitors are connected to the outputs of the opamp. The opamp
and the two sampling capacitors form a feedback loop to drive
the CL1 and CL2 capacitive loads.
In the sample mode, the input sampling network consists of
two input buffers B1 and B2, two sampling capacitors C s1 and
Cs2 , and MOSFET analog switches S1–S4. The speed requirement for sampling network can be expressed as [7]:
1
1
≥
2
exp
−
(1)
2fs τs
2N
where N is the resolution, f s is the clock frequency, and τ s
is RC time constant of the sampling network. Aperture jitter and switching errors due to the charge injection and clock
feedthrough are reduced by using the fully differential bottomplate sampling technique, in which switches S3 and S4 are
turned off before S1 and S2.
In the hold mode, unity-gain feedback of C s1 and Cs2 make
the opamp exhibit a settling time constant of
CL + Csi + Cp,o
Cs + Cp,i
τa =
(2)
·
Gm
Cs
where Cs = Cs1,s2 , CL = CL1,L2 , Gm is the transconductance
of the opamp, C p,i and Cp,o are the parasitic capacitances at the
opamp’s input and output nodes, respectively, and C si is
Csi =
Cs Cp,i
Cs + Cp,i
(3)
Vi1
1
B1
S1
C
C
s1
C
1a S3
VCMI
3
S9 4
3
4
1a
S4
C
C
Vi2
o1
L1
1
B2
o2
S10
s2
C
L2
C
L3
S11
Vo1
Vo2
S12
C
L4
S2
bination of output capacitor coupling and precharging also reduce the opamp’s the dc gain and output voltage swing requirements, so that higher speed can be achieved.
In Fig. 3, switches S3 and S4 are turned off before switches
S1 and S2 in the bottom-plate sampling configuration. Due to
the changing input, the voltage sampled in C s will be different
from those in C L and Co when φ1a = 0. Then during the
subsequent φ 1 = 0 cycle, the output can be expressed as:
1 CL Vcl
1 Vco
Vo ≈ Vi 1 +
−1 +
−1
(5)
A Vi
A Co Vi
where Vco is the voltage stored on C o , Vcl is the voltage stored
on CL . Let CL = 3Co , and Vco = Vcl = 0.98Vi , then the dc gain
A need to be larger than 56 dB to achieve 12-bit resolution.
The output voltage swing of the opamp can be expressed as:
φ1
φ1a
∆Vo = (Vi − Vco ) +
φ3
φ4
Fig. 3. The pre-charge SHA for time-interleaved ADC.
With a finite dc gain of A, the output of the SHA can be
expressed as
Cp,i
1
Vo ≈ Vi 1 −
(4)
1+
A
Cs
The dc gain A should be designed so that the V o deviation from
Vi should be less than 1/2 N+1 . The parasitic capacitance C p,i
demands an increase in A. For example, with C s = 4 pF and
Cp,i = 0.25 pF, A should be at least 79 dB for 12-bit resolution.
During the sample mode, the opamp’s outputs are usually forced to return to the designated common-mode voltage,
VCMO . Thus, during the hold mode, the opamp needs to have
large output voltage swing, wide bandwidth, and high slew rate
to settle the outputs to voltages the sampled inputs. In addition,
the opamp’s input common-mode range has to be large enough
to accommodate the common-mode voltage variation of the inputs.
The Proposed Pre-Charge SHA
Fig. 3 shows the proposed SHA circuit configuration. Analog switches S9–S12 and additional clock phases φ 3 and φ4
represent the input multiplexer of a time-interleaved ADC system. During the channel-1 sample mode, φ 1 = 1 and φ3 = 1,
the input buffers B1 and B2 not only drive the C s1 and Cs2 sampling capacitors but also precharge the opamp’s output nodes
including C L1 and CL2 . When switching to the hold mode
(φ1 = 0), the opamp’s outputs can settle to their final values
in a much shorter time period and without slewing due to the
precharging. During the channel-2 sample mode, φ 1 = 1 and
φ4 = 1, the channel-2 capacitive loading of C L3 and CL4 are
precharged alternately.
The two output coupling capacitors, C o1 and Co2 , are added
to reduce the switching errors of S1 and S2 [8]. The com-
CL
(Vi − Vcl )
Co
(6)
The voltage swing can be reduced by minimizing the voltage
differences of V i − Vco and Vi − Vcl . Increasing C o can reduce
∆Vo , but also increases the capacitive loadings of the B1 and
B2 input buffers during the sample mode.
During the hold mode, the settling time constant of the feedback amplifier is given by
CL + Csi + Cp,o (CL + Csi )Cp,o
Cs + Cp,i
+
(7)
τa =
·
Gm
Gm C o
Cs
where Cs = Cs1,s2 , Co = Co1,o2 , CL = CL1,L2,L3,L4 , Gm is the
opamp’s transconductance, C p,i and Cp,o are the parasitic capacitances at the opamp’s input and output nodes, respectively,
and Csi is
Cs Cp,i
.
(8)
Csi =
Cs + Cp,i
Comparing (2) and (7), it reveals that the second term on the
right side of (7) is the additional speed penalty using output
capacitor coupling with C o1 and Co2 .
Operational Amplifier
The schematic of the opamp is shown in Fig. 4. The telescopic circuit configuration has the best speed/power performance. The circuit’s limited output swing is not a major drawback in this SHA application. The continuous-time output
common-mode feedback (CMFB) using two source-coupled
pairs is suitable here due to the reduced output voltage swing.
The input and output common-mode voltage of the opamp,
VCMI and VCMO , can be different, and both can be different
from the common-mode voltage of the SHA’s inputs. Since
the required dc gain is less than 60 dB, active cascode for gain
boosting is not used. The analog switch M10 is added to equalize the outputs during the sample mode.
The thermal noise in the input sampling network in the sample mode can be expressed as:
Vn2 ≈
kT
Cs + Co + CL
(9)
A total capacitance of more than 4 pF is used to achieve 12-bit
resolution with 2 Vpp differential signal. In this design, we
90
VDD
MC6
M7
Vo
φ1
M6
M10
Vo
VB3
VB2
M3
M4
VB2
Vi
M1
M2
Vi
VB1
SFDR (dB)
M5
VB3
85
MC5
M8
MC1
MC2
VCMO
MC3
MC4
80
75
70
65
60
0
M9
MC8
MC7
10
20
30
40
50
Input Frequency (MHz)
VSS
Fig. 6. SHA SFDR vs. input signal frequency.
Settling Time Constant (ns)
Fig. 4. Telescope opamp schematic.
0.6
0.5
However, the settling time in the hold mode is 9τ a for the
flip-around SHA, and is 5.1τ a for the pre-charge SHA while
12-bit resolution is achieved. Thus, the settling time of the
flip-around SHA is 38% more than the settling time of the precharge SHA, when the opamp of the flip-around SHA operates
without the slew-rate limit.
Pre-Charge SHA
Flip-Around SHA1
Flip-Around SHA2
0.4
Implementation Details
0.3
0.2
0.1
0
0
1
2
3
4
5
6
CL (pF)
Fig. 5. Settling time constant in the hold mode.
have CL = 4 pF while Cs = 1 pF and Co = 1.5 pF. The B1 and
B2 input buffers are required to drive a total capacitive loads of
6.5 pF. For comparison, in the flip-around SHA case, we have
Cs = 4 pF and CL = 4 pF, since the input sampling network
also has Cs in the sample mode. The input buffers are only
required to drive 4 pF capacitive loads.
Fig. 5 shows the settling time constant of (2) and (7) versus different values of C L . The flip-around SHA1 has G m =
15 mA/V, Cs = 4 pF, Cp,i = 0.25 pF, and C p,o = 0.4 pF
while the pre-charge SHA has G m = 15 mA/V, Cs = 1 pF,
Co = 1.5 pF, Cp,i = 0.25 pF, and C p,o = 0.4 pF. With
CL = 4 pF, the τa of the flip-around SHA1 is 31% less than
the τa of the pre-charge SHA.
If dynamic output CMFB is used in the flip-around SHA
to accommodate wide output voltage swing, additional capacitance of 1 pF is added to the C p,o . The resulting circuit is
SHA2. It is noted that the flip-around SHA usually uses the dynamic common-mode feedback to achieve wide output swing,
and its τa becomes 22% less than the τ a of the pre-charge SHA.
The purposed SHA is designed based on a standard 0.25µm
CMOS process. The input buffers B1 and B2 are pMOST
source followers with floating wells tied to the outputs. Each
buffer consumes 10.2 mW of power and has a −3 dB bandwidth of 340 MHz, while driving a 6.5 pF capacitive load. The
analog switches, S1 and S2, are nMOSTs with boosted gate
control voltage to reduce the distortion and allow the use of
smaller device size [9]. The telescope opamp has a gain bandwidth product (GBW) of 1.2 GHz when driving 1.5 pF capacitive loads and dissipating only 12.5 mW of power. The opamp
has a dc gain of 63 dB, and a phase margin of 74 ◦ in closedloop feedback configuration.
Fig. 6 shows the simulated SFDR of the SHA versus the
input frequency. The clock frequency is 100 MHz and the input
has a 2 Vpp differential voltage. The SHA achieves a minimum
SFDR of 73 dB over the entire Nyquist frequency band. The
simulation also reveals that the major distortion contribution
comes from the input buffers driving the sampling network.
Fig. 7 shows the layout of the SHA. The active area occupies approximately 0.44 mm 2 . The SHA simulation results are
summarized in Table I.
Conclusions
A pre-charge SHA is designed for high-speed and highresolution time-interleaved ADC. The combination of precharging and output capacitor coupling can mitigate the opamp
requirements such as dc gain, output voltage swing, input
common-mode range, and slew rate, resulting in low power
dissipation. The settling time in the hold mode is comparable to the conventional flip-around SHAs. Implemented in a
61dB THD S/H Circuit,”in Proc. Custom Integrated Circuits Conference, 1998, pp.381-383.
[4] Wenhua Yang, Dan Kelly, Iuri Mehr, Mark T. Sayuk, and
Larry Singer, “A 3-V 340-mW 14-b 75-Msample/s CMOS
ADC With 85-dB SFDR at Nyquist Input,” IEEE Journal
of Solid-State Circuits, vol. 36, pp. 1931–1936, December
2001.
[5] Gil-Cho Ahn, Hee-Cheol Choi, Shin-Il Lim, Seung-Hoon
Lee, and Chul-Dong Lee, “A 12-b, 10-MHz, 250-mW
CMOS A/D Converter,” IEEE Journal of Solid-State Circuits, vol. 31, pp. 2030–2035, December 1996.
[6] Hendrik Van der Ploeg, Gian Hoogzaad, Henk A. H. Termeer, Maarten Vertregt, and RafL. J. Roovers , “A 2.5-V
12-B 54-Msample/s 0.25-µm CMOS ADC in 1-mm 2 With
Mixed-Signal Chopping and Calibration,” IEEE Journal
of Solid-State Circuits, vol. 36, pp. 1859–1867, December
2001.
Fig. 7. SHA layout.
TABLE I
Summary of SHA simulation results.
Sample Rate
Differential Input
SFDR (2 Vpp)
Output Loads C L
Power Dissipaton
Supply Voltage
Die Area
Technology
100 MHz
2 Vpp
≥ 73 dB
4pF
33 mW
2.5 V
0.44 mm2
0.25 µm CMOS
standard 0.25 µm CMOS technology, the SHA achieves 73 dB
SFDR for 2 Vpp input at 100 MHz sampling rate. The performance is not degraded for input’s frequency up to the Nyquist
frequency. Power consumption is 33 mW from a single 2.5 V
supply.
Acknowledgment
This project is supported by the National Science Council
under the contract NSC-91-2215-E-009-009, and by the Lee
and MTI Center for Networking Research, National ChiaoTung University, Taiwan.
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