J. of Active and Passive Electronic Devices, Vol. 3, pp. 125–133
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©2008 Old City Publishing, Inc.
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CMOS Compatible Single Input Five/Six
Outputs First Order Filter Circuits
Sudhanshu Maheshwari∗
Department of Electronics Engineering, Z.H. College of Engineering and Technology
A.M.U., Aligarh 202 002, India
This paper introduces two new DVCC based first order filter circuits, each
capable of providing five distinct responses simultaneously, three as voltage outputs and two as current outputs. Each of the circuit with a single
grounded capacitor uses one/two resistors for providing three/five filter
functions. Each of the circuit can also generate six distinct first order
functions by incorporating one more resistor. The proposed circuits are
compatible to IC implementation in CMOS technology. The proposed
circuits are verified through PSPICE simulation results.
Keywords: All-pass filters, Analog signal processing.
1 INTRODUCTION
First order all-pass filters are one of the simplest of all analog building blocks
with numerous applications in communication and instrumentation systems
for instance in phase equalizers, design of sinusoidal oscillators etc. This is
evident from the rich repertoire of technical literature published on the subject,
especially the circuits based on different generations and variations of current
conveyors [1–13]. These include mainly the circuits based on CCII[1–7,12],
CCIII [8,9], CCCII [10,11], and DVCC [13]. Among the cited references,
several works are on voltage-mode circuits [1,2,4,6–8,12] and many other on
current-mode works [3,5,9–11,13]. There are a few circuits with operability
in either voltage or current-mode [11]. A number of available circuits benefit
from being derivable from a general configuration [4,6,9,13]. There are circuits
with the advantage of using minimum component count [5,9,10], or providing
∗ Corresponding author. E-mail: sudhanshu_maheshwari@rediffmail.com
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S. Maheshwari
tunable all-pass functions [10,11]. One recent DVCC based current-mode
work enjoys high output impedance, hence cascadable outputs [13].
The intent of this paper is to introduce new first order single voltage input
filter circuits based on DVCC that provide five independent outputs simultaneously; three of which are voltage outputs and two as current outputs.
This feature is unique when the proposed circuits are compared to the already
available circuits. Each of the new proposed circuits employ two DVCCs, one
grounded capacitor and two resistors. Each of the proposed circuits can also
be used to obtain six distinct functions with the addition of one more resistor to
the circuit. PSPICE simulations using CMOS implementation of DVCC [14]
with MIETEC 0.5µm process are included in support of the proposed circuits.
2 PROPOSED CIRCUITS
A differential voltage current conveyor (DVCC) is a five terminal active
element as shown in Figure 1, with the following defining equation.
VX = (VY 1 − VY 2 ), IY 1 = IY 2 = 0, IZ + = IX , IZ− = −IX
(1)
A DVCC was first introduced long back as a modified current conveyor by
Pal [15], and developed by Elwan and Soliman [14]. Some filtering applications of DVCC have also been reported [13–16]. The basic aim of introducing
DVCC was to add the differential input voltage capability to the already
versatile second generation current conveyor, which has been in use for
long [17,18].
The first of the new proposed single input five outputs first order filter
circuit is shown in Figure 2. Routine analysis of the circuit using equation (1)
yields the following transfer functions.
VHP
s − 1/RC VLP
1/RC
s
VAP
;
;
=−
=
=
Vin
s + 1/RC Vin
s + 1/RC Vin
s + 1/RC
IAP1
1 s − 1/RC
1 s − 1/RC
IAP2
=
=−
;
Vin
RL s + 1/RC
Vin
RL s + 1/RC
(2)
(3)
From eqns. (2,3), it is evident that three voltage outputs in form of first order
all-pass, low-pass and high-pass functions and two all-pass current outputs
(with different phase responses) are obtained from the circuit of Figure 2.
Thus a total of five outputs are generated simultaneously. It is also to be noted
that the current outputs are at high impedance Z terminals of the DVCC, thus
enabling easy cascading to successive current inputs in signal processing.
Another interesting feature of the circuit is that a minimum of passive components (two) realize the three first order responses (eqn. 2), a third component
(RL ) is required, if two all-pass current outputs are also to be generated (eqn. 3).
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CMOS Compatible Single Input Five/Six Outputs
IY1
IZ+
Vy1
Y1
VZ+
Z+
DVCC
Y2
Vy2
ZX
IY2
VZ-
IZIX
VX
(a)
VDD
M6
M5
M7
M1
VBB
M13
M14
M15
M4
M2
Y2
M8
Y1
M3
X
M10
M9
M11
M12
Z-
Z+
M16
M17
M18
VSS
(b)
FIGURE 1
(a) Symbol of a DVCC (b) CMOS implementation of DVCC.
Another single input five outputs first order filter circuit is shown in Figure 3.
The same is obtained from the circuit of Figure 2 by interchanging the two Y
terminals of DVCC2. Circuit analysis yields the following transfer functions.
VAP
s − 1/RC VLP
1/RC
s
VHP
=−
=
=
;
;
Vin
s + 1/RC Vin
s + 1/RC Vin
s + 1/RC
IAP1
1 s − 1/RC
1 s − 1/RC
IAP2
=
=−
;
Vin
RL s + 1/RC
Vin
RL s + 1/RC
(4)
(5)
Five responses are obtained from the circuit of Figure 3 like the circuit of
Figure 2, but with different phase responses for the all-pass functions.
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S. Maheshwari
Vin
Y1
Z+
DVCC1
Y2
ZX
R
VHP
Y2
IAP2
Z+
DVCC2
Y1
IAP1
ZX
C
VLP
VAP
RL
FIGURE 2
Proposed single input five outputs first order filter.
Vin
Y1
Z+
DVCC1
Y2
ZX
R
VHP
Y1
IAP2
Z+
DVCC2
Y2
IAP1
ZX
C
VLP
VAP
RL
FIGURE 3
Another single input five outputs first order filter.
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CMOS Compatible Single Input Five/Six Outputs
Another important aspect of the proposed circuits is the non-utility of Z
terminal of DVCC1. Thus when implementing the circuit in IC form, these
Z stages can be suppressed, simplifying the circuit implementation and complexity. Alternatively, if high-pass and low-pass current outputs are desired
then these stages need to be incorporated. By connecting a load (RL ) at the X
terminal of DVCC1 (say in Fig. 2), the two types of high pass current outputs
(with different phase) are generated at the Z− and Z+ terminal of DVCC1
respectively. Low-pass current output can be obtained (from the circuit of
Fig. 2) either by shorting Z− of DVCC1 with IAP1 or by shorting Z+ (of
DVCC1) with IAP2 . Such a circuit with single voltage input then provides
six distinct output functions (three voltages and three currents). The resulting
circuit with single input and six outputs is shown in Figure 4. The transfer
functions for the same are:
VAP
s − 1/RC VLP
1/RC
s
VHP
=−
=
=
;
;
(6)
Vin
s + 1/RC Vin
s + 1/RC Vin
s + 1/RC
IAP
IHP
s
1 s − 1/RC ILP
1 1/RC
1
;
;
(7)
=
=
=−
Vin
RL s + 1/RC Vin
RL s + 1/RC Vin
RL s + 1/RC
It is to be noted that six first order responses are simultaneously obtained from
the circuit with a total active and passive component count of ‘five’. Similar
circuits can also be derived from the circuit of Figure 3. It is to be further
Vin
Y1
Z-
IHP
DVCC1
Y2
Z+
X
RL
R
ILP
VHP
Y2
Z+
DVCC2
Y1
IAP
ZX
C
VLP
VAP
RL
FIGURE 4
First order filter with single inputs and six outputs.
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S. Maheshwari
noted that a first order filter circuit with such features is not yet attempted in
the already available vast literature on the subject [1–13].
3 NON-IDEAL STUDY
A non-ideal/practical DVCC when implemented in a contemporary IC
technology shall be characterized by the following expression.
VX = (β1 VY 1− β2 VY 2 ), IY 1 = IY 2 = 0, IZ+ = α1 IX , IZ− = −α2 IX
(8)
Here, αi and βi (i = 1, 2) are the current and voltage transfer gains respectively, for the DVCC, which differ from unity by the transfer errors. Using the
above equation, the circuit analysis of Figure 2 yields the modified transfer
functions as:
VAP
(β1 s − 1/RC) + (β1 − β2 )/RC
=−
;
Vin
s + 1/RC
VLP
VHP
1/RC
β1 s + (β1 − β2 )/RC
;
=
=
Vin
s + 1/RC Vin
s + 1/RC
IAP1
1
IAP2
1
=−
VAP ;
=
VAP
Vin
α2 R L
Vin
α 1 RL
(9)
(10)
From the above equations, it is evident that the pole-frequency is unaltered
by DVCC non-idealities for all the transfer functions, but the filter gains
are slightly modified due the DVCC non-idealities. Thus the pole-frequency
sensitivity to the DVCC non-idealities is zero, and the filter gain sensitivity to
these non-idealities is found within unity in magnitude. This suggests a good
sensitivity performance for the proposed filter circuit. Moreover, the filter pole
always lies in the left half of s-plane, ensuring unconditional stability of the
proposed circuit. Similar observations are also valid for the circuits of Figure 3
and Figure 4.
4 DESIGN AND VERIFICATIONS
The proposed first order circuit (Figure 2) was simulated using the DVCC
implementation with MIETEC 0.5µm CMOS process parameters [13,14].
The circuit was designed for the pole-frequency 159KHz with R = 1K and
C = 1nF. The value of RL used was 1 K. The magnitude (in dB) and phase
(in deg.) plots for VAP are shown in Figure 5, which is in consistent with the
theory. Figure 6 next shows the phase responses at the two current outputs (IAP1
and IAP2 ), which are inverse of one another. Next the circuit was subjected
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CMOS Compatible Single Input Five/Six Outputs
0
-1.0
-2.0
0d
-50d
-100d
vdb(23)
SEL>>
-200d
100Hz
1.0KHz
vp(23)
10KHz
100KHz
1.0MHz
10MHz
Frequency
FIGURE 5
Magnitude and Phase plots for voltage-mode all-pass response of Fig. 2.
200d
150d
100d
50d
0d
0d
-50d
-100d
IP(VO1)
SEL>>
-200d
100Hz
1.0KHz
IP(VO2)
10KHz
100KHz
1.0MHz
10MHz
Frequency
FIGURE 6
Phase response for two all-pass current outputs of Fig. 2.
to a sinusoidal input (Vin ) of 159KHz. The voltage output (VAP ) and the two
current outputs are shown in Figure 7. As expected, the voltage output is phase
shifted with respect to the input by −90 degrees and the two current outputs
are phase inverted, which is also consistent with the presented theory. Similar
results are also obtained for the other proposed circuits of Figure 3 and 4.
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10mV
S. Maheshwari
Vin
VAP
0V
SEL>>
-10mV
V(23) V(20)
20uA
IAP1
IAP2
0A
-20uA
5us
10us
15us
20us
25us
I(vo1) I(vo2)
Time
FIGURE 7
Input/Output voltage waveforms and output current waveforms at 159 KHz for all-pass functions
of Fig. 2.
5 INTEGRATION ASPECT
The proposed single input five/six outputs filter circuit uses two differential
voltage current conveyors, which can be conveniently implemented in CMOS
technology [14]. Each of the circuit uses a single grounded capacitor in its
realization, which is ideal for integration. The resistors used in the circuits are
replaceable by active MOS resistors, available in literature [19,20], with the
advantage of tunability through external voltage. Such a replacement offers
two advantages. Firstly it allows the circuits to be tuned electronically and
secondly it is desirable from the IC implementation viewpoint. Thus it is to
be realized that each of the proposed circuits can be integrated in CMOS
technology.
6 CONCLUSION
Two new single input five outputs first order filter circuits each employing two
DVCC and a minimum of passive elements (keeping in view the number of
functions generated) are proposed. Another circuit with an additional resistor is also proposed which is capable of providing six first order responses
simultaneously. A circuit with single input providing five/six first order filter
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CMOS Compatible Single Input Five/Six Outputs
133
responses simultaneously is not yet available in the literature. The proposed
circuits with grounded capacitor in each case are suited for IC implementation in CMOS technology and are verified through PSPICE simulations using
MIETEC 0.5µm process parameters.
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