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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 60, NO. 9, SEPTEMBER 2013
Frequency Limitations of First-Order
gm − RC All-Pass Delay Circuits
Seyed Kasra Garakoui, Eric A. M. Klumperink, Bram Nauta, and Frank E. vanVliet
Abstract—All-pass filter circuits can implement a time delay
but, in practice, show delay and gain variations versus frequency,
limiting their useful frequency range. This brief derives analytical equations to estimate this frequency range, given a certain
maximum allowable budget for variation in delay and gain. We
analyze and compare two well-known gm − RC first-order all–
pass circuits, which can be compactly realized in CMOS technology and relate their delay variation to the main pole frequency.
Modeling parasitic poles and putting a constraint on gain variation, equations for the maximum achievable pole frequency and
delay variation versus frequency are derived. These equations are
compared with simulation and used to design and compare delay
cells satisfying given design goals.
Index Terms—All-pass filter, bandwidth, delay, filter optimization, frequency range, phase shift, phase shifter, true time delay.
I. I NTRODUCTION
Fig. 1.
Phase and gain of an ideal versus first-order delay cell.
amount of delay much more compactly than inductor-based
delay cells. Although many tradeoffs exist, for instance, in
achievable frequency, noise, linearity, and power consumption,
gm − RC all-pass circuits are clearly area and, hence, cost
effective and will be the focus of this brief.
An ideal first-order all-pass filter has a pole and zero and can
be written as
A
NALOG time delay circuits have several applications,
for instance, compensating delay differences between
signal paths, broadband beamforming [1], and equalizing the
communication channel for wireline communication [2]. Ideally, such delay circuits should have both a constant unity
gain and a well-defined constant delay, which does not vary
with frequency. However, practical delay circuits do show
frequency-dependent gain and delay variations. This frequency
dependence affects the functionality of systems, which exploit delay circuits, limiting their accuracy. For example, in
time-delay-based phased-array antenna systems, a frequencydependent time delay causes frequency dependence in the beam
direction (“beam squint”) [3], [4].
CMOS is often the desired technology for the implementation of mixed-signal systems. At radio frequencies, operational
amplifiers are impractical, and time delays are typically implemented either in transmission lines [5], LC delay lines [1], or
all-pass gm − RC delay circuits [2], [6], [7]. In this brief, we
focus on circuits that can be implemented in standard CMOS
integrated circuit technology at low area cost and low supply
voltage. Transmission lines in CMOS require very long (lossy)
metal lines to produce a significant amount of delay, whereas
LC delay lines need on-chip inductors. The gm − RC all-pass
delay circuits proposed in [2], [6], and [7] can produce a given
Manuscript received March 11, 2013; revised April 30, 2013; accepted
May 31, 2013. Date of publication August 2, 2013; date of current version September 11, 2013. This brief was recommended by Associate Editor
R. Martins.
The authors are with the Integrated Circuit Design group, University of
Twente, 7500 Enschede, The Netherlands (e-mail: sgarakooee@yahoo.com;
E.A.M.Klumperink@utwente.nl;
B.Nauta@utwente.nl;
F.E.vanVliet@
utwente.nl).
Digital Object Identifier 10.1109/TCSII.2013.2268418
H(s) =
1−
1+
s
2πfP
s
2πfP
(1)
where fP refers to the pole frequency. Note that the pole and
zeros are positioned at +/ − fP , resulting in twice the phase
and delay of a single-pole system. In addition, the gain is 1 and
is frequency independent. Fig. 1 shows the phase and gain of
(1), in comparison to an ideal time-delay cell. The time delay at
an operating frequency of f0 is equal to τ = −ϕ(f0 )/(2πf0 ).
As Fig. 1 shows, the delay of a first-order all-pass cell is
frequency dependent and varies with f0 .
In general, delay [8] and gain variations limit the useful
frequency range. What is acceptable depends on system requirements (see, for instance, [3] and [4]), and we will assume
a maximum allowed gain and delay variation budget. This brief
provides a method to analyze the achievable frequency range of
delay circuits, given such a budget.
In the literature, we found several delay circuits but no
comparison of their relative merits nor a design method to
maximize the useful frequency range. This brief aims at filling
this gap.
As low-level circuit details critically affect delay cell performance, we will analyze and compare two well-known voltagemode all-pass circuits. One is the “classical” all-pass delay
circuit described in [6], but with much older roots at least dating
back to [9]. We will compare this with the “Buckwalter” cell
structure proposed in [2]. The circuit in [7] is not considered
further, as it is a current-mode circuit complicating comparison
and uses three stacked transistors that are less suitable for low
supply voltages.
We will propose an analysis method that also holds for the
practical case where a delay cell operates in a cascade of similar
1549-7747 © 2013 IEEE
GARAKOUI et al.: FREQUENCY LIMITATIONS OF gm − RC ALL-PASS DELAY CIRCUITS
573
Fig. 2. fϕ=0 for a delay cell with operating frequency f0 .
Fig. 4. “Classical” first-order all-pass delay cell.
Fig. 3. fϕ=0 /f0 and fP τ versus normalized frequency f0 /fP .
delay cells. The input impedance of the next cell will then
load the previous one, while an extra capacitive load (CL )
may also be present. The analysis partly builds on [8], where
criterion fϕ=0 is introduced to quantify variations of delay
versus frequency. This figure of merit has some properties [8]
that we will exploit, which are briefly summarized below.
As shown in Fig. 2, fϕ=0 is the frequency where the tangent
to the phase transfer function at f0 crosses the frequency axis
(ϕ = 0). For an ideal time delay cell, fϕ=0 /f0 = 0, and for an
ideal phase shifter, fϕ=0 /f0 = −∞ [8]. For a practical delay
cell with a nonlinear phase transfer function, a low value of
fϕ=0 /f0 is desirable. In general, fϕ=0 /f0 values can be found
from the phase transfer function as [8]
fϕ=0,cell
=1−
f0
ϕcell (f0 )
f0
.
∂ϕcell (f ) ∂f
f
(2)
0
Now, relative delay variation ΔtD /tD (f0 ) for frequency
variation Δf around f0 is given by [8]
fϕ=0,cell
f0
fϕ=0,cell
f0
ΔtD (f0 )
≈
tD (f0 )
1−
Δf
.
f0
(3)
Clearly, if (fϕ=0 /f0 ) 1, then ΔtD /tD (f0 ) ≈ 0, which
means that the circuit approximates an ideal delay over frequency band Δf .
If we apply (2) to the phase transfer function of the ideal
first-order all-pass cell (1), we find
fϕ=0,cell
a tan(f0 /fp ) 1 + (f0 /fp )2 .
=1−
f0
f0 /fp
(4)
Fig. 3 plots numerical values for (4) versus operating frequency f0 , normalized to pole frequency fp . In addition, fP τ
is shown, which slightly varies around 0.25 for f0 = fp (phase
shift −π/2). For low relative delay variation at given Δf and
f0 , (3) asks for low fϕ=0 /f0 , i.e., large fP . However, as fP τ
is around 0.25, less delay per cell results (roughly ∝ 1/fP ).
Fortunately, cascading cells allows for more delay at constant
relative delay variation. If cells are identical, fϕ=0 of the
cascade is equal to that of a cell [8]. Hence, analyzing fp of
a single (loaded) cell is sufficient to characterize a cascade of
delay cells with respect to delay variation.
In this brief, we will show how the maximum value of fP
is limited by the circuit topology and technology parameters,
where also gain variations induced by parasitic poles will be
considered. Note that previous work [8] only modeled ideal
low-pass RC and LC delay cell behavior, no all-pass cells.
Moreover, no gain variation effects nor parasitic loading effects
were modeled, which is way too optimistic.
The maximum achievable fp will now be analyzed for the
“classical” delay circuit in Section II and the “Buchwalter”
delay circuit in Section III. Section IV will verify analysis
by simulation and compare the relative merits of the circuits.
Section V will present the conclusions.
II. A NALYSIS : T HE C LASSICAL D ELAY C IRCUIT
Fig. 4 shows the classical all-pass delay cell [6], [9]. Instead
of resistors, diode-connected MOSFETs or triode MOSFETs
may also be used; however, resistors are preferred for linearity
reasons, for having less parasitic capacitance than MOSFETs,
and for requiring low voltage headroom.
Equation (5) shows an approximate transfer function, i.e.,
gm
1−RH CH s
Vout
. (5)
≈
·
Vin
gm +GA 1+ R + 2
(C
+C
+C
)s
H
H
in
L
gm+GA
Cin is the input capacitance of the next stage. If each delay
cell is cascaded with identical delay cells, then Cin ≈ 2Cgd
(due to the Miller effect on Cgd ). Equation (5) differs from
transfer function (1) because its dc gain is less than one and
the absolute value of the pole and zero differ from each other,
causing attenuation at high frequencies (see Fig. 5). Still, (5)
can approximately imitate transfer function (1); hence, we can
reuse (4) provided that two conditions are satisfied as follows:
1) (gm /gm + GA ) ≈ 1;
2) (RH + 2/(gm + GA ))(CH + Cin + CL ) ≈ RH CH .
The second condition ensures proximity of the absolute value
of the pole and the zero frequency, which keeps the amount of
frequency-dependent gain attenuation small.
We will now assume that the design requirements are
1) dc gain Av0 , (0 < Av0 < 1);
2) high-frequency attenuation ≤ ΔHp .
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 60, NO. 9, SEPTEMBER 2013
Fig. 5. Voltage gain of the “Classical” delay cell.
Fig. 7.
Fig. 6. Buckwalter circuit.
By substituting these values in (5), we get
1
AV 0
1 − AV 0 gm
2AV 0
≥
1
gm 4 √
RA ≥
RH
(6)
(7)
2(1−ΔHp )2 −1−1
CH ≥ CL + 2Cgd
√
4
1
2(1−ΔHp )2 −1
.
−1
(8)
Note that (9a) gives the maximum possible pole frequency,
i.e., the lowest delay variation [see (4) and Fig. 3].
III. A NALYSIS : T HE B UCKWALTER D ELAY C IRCUIT
Fig. 6 shows the all-pass circuit proposed by Buckwalter [2]
implemented using MOSFETs and resistors.
As aforementioned, the circuit is cascaded with identical
circuits; therefore, the circuit is loaded with impedance that
is equal to its input impedance and an extra load capacitance
CL . The input impedance can be simply approximated by evaluating the Miller effects on capacitance values CB and Cgs1 :
Cin ≈ 2CB +Cgs1 /(1+gm RS ) ≈ 2CB . During the rest of the
calculations, the value of Cgd1 is absorbed inside CB . Cprs =
Cdb1 +Cgd2 . The approximate transfer function of the circuit is
Vout
RD
≈− 1
Vi
gm1 + Rs
+
1+
CL
1
CB RD gm2
2
RD gm2
1+gm1 Rs
CB s
gm1
2
RD gm2
1+ Cprs + CL
1
CB
CB RD gm2
2
1+ R g
D m2
.
s
(10)
1 and
2
1.
1 + RD gm2
These conditions cause the absolute values of pole and zero
to be close to each other. Suppose there are two design requirements: 1) dc gain = 1 and 2) at f0 = fP , the high-frequency
attenuation ≤ ΔHp . Via these assumptions, we can find gm2 ,
CB , and fp . Thus
2 4 2(1 − ΔHP )2 − 1
gm2 ≥ (11)
1
4
2−1
1
−
+
R
)
2(1
−
ΔH
s
p
gm1
CB ≥
CL
RD gm2
2
RD gm2
Cprs +
1+
4
2(1 − ΔHP )2 − 1
. (12)
1 − 4 2(1 − ΔHP )2 − 1
Substituting RD = (1/gm1 ) + Rs (the unity gain condition),
gm2 , and CB in (10) results the following pole and zero
conditions:
1
2
2(1 − ΔHp )2 − 1
(13a)
|fp,B | ≤
2πRD CB
|fz,B | ≤
1−
1 + RD CB 1 +
The right side of (10) contains two parts. The first part is
the dc gain, and the second part is approximately the all-pass
transfer function. The initial phase shift at dc is π, which
we do not consider in our calculations because in processing
differential signals, the π phase shift can be compensated with
interchanging the output signals [2]. To design the delay circuit,
we again aim at approximating transfer function (1). For the
unity dc gain, the following condition must be satisfied: RD =
RS + 1/gm1 . Fig. 7 shows the gain transfer function of the
Buckwalter delay circuit with unity dc gain.
Equation (10) can approximate the transfer function of an allpass delay cell, provided that two conditions are satisfied, i.e.,
Cprs
CB
Based on (7) and (8), the condition on the pole and zero
frequencies for the “Classical” delay circuit becomes
1
|fp,C | ≤
· 2 2(1 − ΔHp )2 − 1
(9a)
2πRH CH
1
|fz,C | ≤
.
(9b)
2πRH CH
·
Voltage gain of the Buckwalter delay cell.
1
.
2πRD CB
(13b)
Again, (13a) provides an estimate of the maximum possible
pole frequency of the Buckwalter delay circuit, and (3) and (4)
and Fig. 3 relate this to delay variation.
GARAKOUI et al.: FREQUENCY LIMITATIONS OF gm − RC ALL-PASS DELAY CIRCUITS
TABLE I
T RANSISTOR D ESIGN PARAMETERS U SED
575
TABLE II
C OMPARISON OF THE D ELAY C ELL P ROPERTIES
IV. V ERIFICATION AND D ESIGN E XAMPLES
To verify analysis and exemplify how the analytical equations can be used during design, we will address two design
questions as follows: 1) Which of the delay cells achieves the
highest fp for a given power budget? and 2) What is the power
consumption for each delay circuit provided that they fulfill the
same delay and noise figure requirements?
We will use a CMOS process UMC 180-nm supply voltage
that is equal to 1.8 V.
A. Maximum fp for a Given Power Budget
Suppose the design requirements for a delay cell in a cascaded chain are dc gain > −1 dB and ΔHp < 1 dB, and we allow a maximum dc current of 3.5 mA. Assume also two loading
cases: CL is 0 or 2 pF. We aim at finding the best circuit w.r.t.
delay variations and, hence, compare the maximum achievable
fP . To reduce the channel length modulation in transistors, their
lengths are chosen to be 240 nm. The overdrive voltage of all
transistors is chosen equal for both circuits (VGS,OV = 75 mV),
so that fT of the transistors is equal. For Buckwalter’s cell, the
size of M2 is chosen to be ≈15 times of M1 to satisfy (11), even
for Rs = 0 (see Table I).
For these transistor sizes, Cgd for “Classical” is 173 fF, and
Cprs for “Buckwalter” is around 152 fF. Based on (8) and
(12) and CL = 0, we find CH ≥ 2434 fF and CB ≥ 943 fF,
whereas for CL = 2 pF, we find CH ≥ 16.508 pF and CB ≥
1.771 pF. (In the Buckwalter circuit, the effect of CL is reduced
by the buffer stage.) The values for resistors calculated based
on (7) are RA = RS = 170 Ω and RH = 252 Ω, whereas for
the Buckwalter circuit, we find RS = 0, RD = 249 Ω (to have
unity gain condition at dc: RD = RS + 1/gm1 . Table II shows
calculated and simulated values for each delay cell for the
two loading conditions, which match good enough for first-cut
circuit design. As noise and linearity are often also important,
we also added simulation results for noise and IIP3 (with
50 Ω as reference) for operating frequency ≈ fp , where ΔHp
has been estimated and verified. Overall, the Buckwalter cell
achieves better higher fp and is less sensitive to CL .
Fig. 8 shows the simulated phase and gain plots of the delay
cells. The values of AV 0 (the dc gain) and ΔHp (gain drop at
the pole frequency) are shown in the figures, where the pole frequency is defined as the frequency where the phase has dropped
90◦ with respect to dc. Note that, although circuit parasitics
affect the transfer function, the phase characteristic roughly
resembles that of a first-order all-pass filter. As predicted, the
“Classical” circuit has attenuation at low frequency, but the
Buckwalter circuit can have quite near to unity dc gain. Clearly,
the Buckwalter circuits achieve the best frequency range, with
also less overall attenuation.
Fig. 8. Simulated phase and gain for CL = 0 and CL = 2 pF.
If we compare these results with that of a single-pole lowpass circuit, we achieve double the delay using an all-pass
cell and about a 1-dB gain drop instead of 3 dB at the pole
frequency.
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 60, NO. 9, SEPTEMBER 2013
TABLE III
PARAMETERS FOR E QUAL D ELAY AND 10-dB N OISE F IGURE
B. Power Comparison for Equal Delay Cell Requirements
Suppose now the following properties are desired: an operating frequency f0 = 100 MHz, a relative delay variation of
5% for Δf = ±10 MHz around f0 , a dc gain of > −1 dB,
ΔHp < 1 dB, and NF = 10 dB referred to 50 Ω, while we want
to calculate the achievable delay per cell.
To obtain the maximum delay per cell, we choose the minimum fp that just satisfies (3) [8] for the aforementioned requirements. For design, suppose the initial sizes of the transistors are
as in Table II, then from fp , we find the value of capacitors. Using admittance scaling [10] to satisfy the noise figure requirements, we multiply all W and capacitor values by α and divide
all resistor values by α. With this method, the circuit delays do
not change; however, the noise figure will change proportional
to the power consumption (constant signal-to-noise ratio/Power
[10]). The power consumption also strongly depends on the
overdrive voltage of the transistors. Substituting the delay variation of 5% and relative bandwidth of ±10 MHz into (3) results
in fϕ=0 /f0 = −1. In the graph in Fig. 3, this corresponds
to f0 /fp = 1.4. Therefore, the minimum value of fp of the
delay cells must be 100/1.4 = 71.4 MHz. This requires equal
fP for both circuits, i.e., RH CH ≈ 1/2πfp = 2.23e − 9 and
RD CB ≈ 1/2πfp = 2.23e − 9. To bring the noise figure to
10 dB for both, the values of resistors and capacitors will be
RA = RS = 173.4 Ω, RH = 257 Ω, CH = 8.67 pF and Rs =
0, RD = 321.2 Ω, CB = 6.94 pF. Table III shows the resulting
aspect ratio and dc consumption of both circuits. The achievable
delay with both circuits now is 3.025 ns at f0 = 100 MHz. For
the same noise figure, the Buckwalter cell consumes 20% less
dc than the Classical circuit. In addition, the majority of its
current is mainly consumed by the buffer transistor. For some
applications, the loading capacitance may be small, and it might
be possible to remove the buffer part of the Buckwalter circuit
to reduce its power consumption.
V. S UMMARY AND C ONCLUSION
A method for analyzing the maximum useful frequency
range of first-order all-pass delay cells has been introduced. It
has been used to analyze and compare two well-known gm −
RC delay cells, i.e., the “Classical” and the “Buckwalter” allpass cell. The analysis holds for single and cascaded identical
cells. To this end, the cells have been analyzed as a self-loaded
content with an arbitrary extra loading capacitance. The resulting transfer function deviates from ideal delay-cell behavior in
two key aspects, i.e., both the gain and delay are frequency
dependent. Design boundary conditions were derived for each
all-pass circuit to keep the gain variation below a specified
maximum and ensure that the shape of the transfer function still
resembles the simple first-order all-pass function (1), which is
characterized by one pole frequency fP . The design boundary
conditions were then expressed as constraints on the maximum
achievable pole frequency fP . Substituting fP in (4), (3) can
now be used to estimate the amount of delay variation as a
function of frequency variation Δf around nominal operating
frequency f0 .
For any single first-order all-pass delay cell, or approximation thereof, a larger value of fp renders smaller delay variations
over a given frequency range Δf around f0 , but also smaller
delay (see Fig. 3). When cascading multiple cells, each cell
needs to realize less delay and, hence, can have higher fP ,
resulting in less relative delay variations (3). This thus results in
a larger useful frequency range (but more chip area and power
consumption). The equations in this brief model the tradeoffs
between delay-cell pole frequency fP , center frequency f0 ,
frequency range Δf , and delay variation, while keeping amplitude variations within a budget and allowing for improving
performance by cascading cells.
To exemplify the usefulness of the analysis, it was applied
to two delay cells to compare their relative performance and
estimate their delay variation versus frequency. With the help
of the derived design equations, an optimization of fp was illustrated, keeping delay and power constraints fixed, comparing
results with and without extra capacitance. Then, the analysis
results were exploited to achieve equal delay with different
circuits, under the condition of fixed noise performance, while
comparing power dissipations. Similar analysis can be done for
other kinds of first-order gm − RC all-pass delay cells.
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