Forum for Electromagnetic Research Methods and Application Technologies (FERMAT)
Electromagnetic Analysis and Circuit Modeling
of Ultra-Wideband SPST Switch in 65-nm
CMOS Technology
Anak Agung Alit Apriyana(1), Jin He(2), and Yue Ping Zhang(3)
Virtus IC Design Centre, Nanyang Technological University
(1)
(Email: E090055@ e.ntu.edu.sg)
(2)
School of Physics and Technology, Wuhan University
(Email: jin.he@whu.edu.cn)
(3)
School of Electrical and Electronic Engineering, Nanyang Technological University,
Singapore
(Email: EYPZhang@ntu.edu.sg)
the distributive and coupling effects within the structure.
Section III describes how to extract extrinsic parasitic
inductances, capacitances and resistances of the switch structure
for circuit modeling. Section IV compares the simulated and
modeled with the measured results of the SPST switch,
validating the electromagnetic analysis and circuit modeling.
Finally, Section V concludes the paper.
Abstract—This paper focuses on electromagnetic analysis and
circuit modeling of an ultra-wideband single-pole single-throw
(SPST) switch in a 65-nm CMOS technology up to
millimeter-wave frequencies. We begin by carrying out the
electromagnetic analysis using the HFSS, which is a
three-dimensional full-wave field solver. A novel technique to
simulate an on-state switching transistor is proposed and
highlighted. Then, the circuit modeling is performed by including
all extracted extrinsic parasitic inductances, capacitances, and
resistances, especially the drain-to-source parasitic capacitances
introduced by the overlapped multi-finger metalization of the
transistors. Next, the electromagnetic analysis and circuit
modeling are validated with the measurements of the SPST switch
over the frequency ranges from 1 to 110 GHz and 140 to 170 GHz,
respectively. Finally, we point out that although the
electromagnetic analysis can provide a deep physical insight into
the switch behavior, it has an inherent limitation, namely it cannot
handle the devices for the electron transfer phenomena such as the
hot carrier effect, well proximity effect, negative bias temperature
instability, and etc.
II. ELECTROMAGNETIC ANALYSIS
A single-pole-double-throw (SPDT) switch that consists of 2
transistors, 2 resistors, and 4 transmission-line sections was
simulated in [13] by using the Sonnet, a two-dimensional (2D)
full-wave electromagnetic field solver. Unfortunately, no
electromagnetic analysis was carried out to gain physical insight
into the switch behavior [13]. In this Section, the SPST switch
that consists of 2 transistors, 2 resistors, 1 inductor, 8
transmission-line sections, and 7 testing pads is simulated using
the HFSS, a three-dimensional (3D) full-wave electromagnetic
field solver. More importantly, the distributive and coupling
effects within the SPST structure are discussed for in-depth
understanding of the switch characteristics.
Index Terms—65-nm CMOS, 60 GHz, millimeter wave, switch.
A. The SPST Switch
Fig. 1 shows the schematic and layout of the SPST switch in a
65-nm CMOS technology. The transistors M1 and M2 are used
to turn-on or turn-off the switch, depending on the state of the
control voltage (VCTRL). When VCTRL is low, both transistors M1
and M2 are off. Hence, the signal at Port 1 can be passed to Port
2 through the inductor L1. On the other hand, when the VCTRL is
high, both transistors M1 and M2 are on and thereby shorting
both ports to the ground and thus ideally there is no signal
passed through from Port 1 to Port 2. The poly resistors (RG1 and
RG2) are used to bootstrap the gate at RF. By bootstrapping the
gate, it will be floating at RF and hence its gate-to-source and
gate-to-drain potential will be relatively constant. The inductor
L1 is used to improve the input and output matching by
compensating the shunt capacitance effects that are introduced
by the transistors M1 and M2 during their off-state.
I. INTRODUCTION
M
ILLIMETER-WAVE technologies are very promising for
multi-gigabit wireless communications at 60 GHz,
sensing and detection at 77 GHz, high resolution imaging at 94
GHz, and wireless chip area networks above 100 GHz. The
interest in these applications has led to extensive research in
millimeter-wave CMOS circuits and systems [1-6]. This paper
reports a SPST switch, a basic circuit to build
single-pole-multiple-throw
(SPMT)
switches
for
time-domain-duplexing transceivers, switched-beam arrays,
and multiple-input and multiple-output systems [7-15]. The
SPST switch designed in a 65-nm CMOS exhibits
ultra-wideband characteristics up to millimeter-wave
frequencies.
Section II of the paper addresses how to build and simulate
the SPST switch in the HFSS and more importantly discusses
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Forum for Electromagnetic Research Methods and Application Technologies (FERMAT)
rectangles/boxes. Lump-port excitation is used at the input and
output. Radiation boundaries surround the SPST switch with
horizontal separations of λ0/8 (λ0 is the wavelength at 60GHz)
from each edges and vertical separations of λ0/8 from the top
and bottom surface. Since the ground probing planes of the
input or output are connected, we can apply two-port excitation
as shown by the arrow directing from the ground to Port 1 and
Port 2.
L1
Port 1
Port 2
96 pH
M1
RG1
RG2
M2
10 k
10 k
VCTRL
0 / 1.2V
(a)
GND
GND
(G)
GND
GND
(G)
L1
Port 1
L1
Port 2
(S)
+
Port 1
(S)
+
Port 2
M1
GND
M2
RG2
RG1
GND
VCTRL
GND
(G)
VCTRL
GND
(G)
(b)
Fig. 1. The SPST switch: (a) schematic and (b) layout.
B. HFSS Simulation
The 65-nm CMOS process is a fully developed technology.
There are 29 different dielectric layers in the process. The
bottom dielectric layer is the silicon substrate and the active
region. The thickness of the silicon substrate can be chosen as
250 or 350 or 450 µm. The dielectric constant and resistivity of
the silicon substrate are around 11.9 and 10 Ω·cm, respectively.
On the silicon substrate is the dielectric contact layer of
thickness 400 nm and dielectric constant 4.2. On the contact
layer are the 24 silicon-oxide layers whose thicknesses are
20~790 nm and dielectric constants are 2.9~8.1. On top of the
silicon-oxide layers are the 3 passivation layers whose
thicknesses are 40~600 nm and dielectric constant 4.2~8.1 to
protect the circuits. There are also 7 copper and one aluminum
metal layers in the process. They are sandwiched in between the
silicon-oxide layers and can be connected with inter metal vias.
The sheet resistance of these metal layers are 19~225 mΩ/sq,
depending on the layer thickness. Dummy fills need to be
inserted to respect metal density rules and guarantee component
integrity.
(a)
(b)
Fig. 2. The HFSS model of the SPST switch: (a) Top view and (b) 3D view
showing the radiation boundaries enclosing the chip.
Fig. 2 shows the HFSS model of the SPST switch. It is known
that the electromagnetic simulation of such a multi-scale
structure is quite challenging and almost impossible with our
computer resource of 8G RAM. To speed up computation and
to reduce required memory, the number of dummies has been
greatly reduced and series/arrays of vias are simplified as
The HFSS or other field solvers have an inherent limitation,
that is, they cannot handle the devices in their active states.
Hence, the electromagnetic simulation of the isolation
performance of this SPST switch seems to be infeasible because
the transistors M1 and M2 are in the on- state. The limitation is
overcome by using a T-junction to control the amount of
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Forum for Electromagnetic Research Methods and Application Technologies (FERMAT)
(a)
currents that are flowing from the input port to the inductor and
the drain of the control transistor, and by using a thin conductive
layer that has a resistivity of 4~6 Ω placed underneath the
source and drain metallization to represent the conducting
channel during the on-state of the control transistors. Fig. 3(a)
shows the current distribution when the control voltage is high
(1.2V) and both M1 and M2 are turned-on. For this particular
case, the current x (µA) flows to the drain of the transistor and y
(µA) flows to the inductor. To mimic this transistor action in the
HFSS simulation, the T-junction as illustrated in Fig. 3(b)
should have the same current distribution as that in the circuit
simulation. Hence, the equivalent resistance of metal
interconnection toward the inductor (RB) is set (x/y) times higher
than the equivalent resistance of metal interconnection toward
drain of M1 or M2 (RA).
y (uA)
L1
M2
M1
(b)
L1
Port 1
Port 2
96 pH
M2
x (uA)
RG2
RG1
M1
80/0.06
M2
80/0.06
(c)
(a)
x
RB = y RA
Fig. 4 shows the current density distribution across the chip at
60 GHz when the switch is on (VCTRL = 0 V). The current
distribution is shown with high density within inductor (L1).
When the switch is on, most of the current should flow from Port
1 to Port 2 through the inductor to achieve low insertion loss.
However, as shown in the magnified area around the transistor,
some current is leaked to the ground through the off-state
control transistor. As shown in Fig. 4(d), the current densities at
the multi-finger drain and source metalization are very high,
which indicate that a strong electromagnetic coupling exists
between the source and drain metallization. This strong
electromagnetic coupling introduces very large parasitic
capacitances that affect the insertion loss and return loss of the
switch. The coupling strength is found to increase with
frequency as illustrated in Fig. 5. As shown in Fig. 5(a), at 5
GHz the leakage current due to electromagnetic coupling across
the drain-source metalization is smaller. As shown in Fig. 5(b),
5(c) and 5(d) respectively for 20 GHz, 40 GHz and 50 GHz, the
leakage currents increase with frequency. Based on this finding,
the insertion loss is expected to increase as the frequency
increases due to higher leakage.
RA
(b)
Fig. 3. Illustration of T-junctions used in isolation simulation with the HFSS:
(a) current distribution when both control transistors are turned-on and (b) the
equivalent resistance of T-junction to mimic the current distribution as in (a).
GND
GND
L1
Port 1
Port 2
+
+
GND
(d)
Fig. 4. Current density distribution when the switch is on (VCTRL = 0 V) at 60
GHz: (a) Top view of the current density distribution, (b) Zoom-in 3D view, (c)
Zoom-in at the rectangle area as in (b) showing the current leakages to the
ground via M2, and (d) Zoom-in at the dashed rectangle area as in (c) showing
the coupling strength across the transistor metallization.
VCTRL = 1.2 V
Port 1
M2
GND
VCTRL
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Port 2
L1
Port 1
(a)
(b)
(a)
Port 2
L1
Id2
(c)
(d)
Fig.5. Current density distribution when the switch is on (VCTRL = 0 V) at
difference frequencies: (a) at 5 GHz, (b) at 20 GHz, (c) at 40 GHz, (d) at 50
GHz.
Ip1
Ip2
Figure 6 shows the current density distribution, when the
switch is off (VCTRL = 1.2 V) at 135 GHz. When the control
transistors are on, most of the current will be sinked to the
ground and less current will flow from Port 1 to Port 2 through
inductor. This is shown clearly that the current density within
the inductor is now low. To achieve good isolation performance,
the current that flows from Port 1 to Port 2 should be minimized
when VCTRL is high. However, the current at Port 1 may reach
Port 2 due to electromagnetic coupling within the control
transistor. As illustrated in Fig. 6(b), the drain current of the of
M1 (Id) can be coupled to the source through the drain-to-source
electromagnetic coupling (Ip1), and can be coupled to the gate
through the drain-to-gate electromagnetic coupling (Ip2). The
currents Ip1 and Ip2 are then coupled to the drain and eventually
reach Port 2 via a similar mechanism.
Id1
Port 1
(b)
M2
RG2
(c)
Fig. 6. Current density distribution when the switch is off (VCTRL = 1.2 V) at
135 GHz: (a) Full 3D view, (b) Zoom inside the rectangle as in (a), and (c)
Zoom inside the dashed rectangle as in (b) around the transistor area.
III. CIRCUIT MODELING
HFSS simulation is known for its accuracy in predicting the
electromagnetic behavior of a passive circuit. However,
designing a circuit with active devices based on HFSS
simulation alone will be infeasible and very time consuming.
Usually, the parasitic parameters are extracted from the HFSS
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Forum for Electromagnetic Research Methods and Application Technologies (FERMAT)
simulations and are used to enhance the circuit model to
improve the accuracy of circuit simulation.
R & L GND
Metalizations
PORT 1
A. Parasitic Extraction
CPORT
Fig. 7 illustrates the source-to-ground parasitic resistance
(RP1) and inductance (LP1) that are contributed by:
(1) Metals and vias of the source-to-ground metallization as
illustrated by Fig. 7(b).
(2) Metal-1 ground plane (M1 GND plane)
(3) The ground metals and vias of the GSG testing pads (R &
L GND metallization) as illustrated by Fig. 7(c).
The main contributors of RP1 and LP1 are the control transistor’s
source-to-ground metallization as illustrated by Fig. 7(b). In this
case, the equivalent resistance and inductance of the ground of
the GSG testing pads shown in Fig. 7(c) are much smaller since
there are many vias within the GSG testing pads multilayer
metallization.
M2
RG1
RG1
CP1
(c)
Fig. 7. (a) and (b) Illustrations of the equivalent extrinsic parasitic resistance
and inductance (Rp1 & Lp1) of the source-to-actual ground (ground of testing
pad), and (c) AA’ cross-section to illustrate the parasitic capacitances between
the signal ports to the ground (CPORT) and also source-to-ground parasitic
capacitances (CP1).
The GSG testing pads of Port 1 and Port 2 are used as the
direct access to the circuit; hence the modeling and
characterization of them are also critical to ensure that they are
operable beyond the operating frequency [17]. The signal pads
are aluminum on top of copper metal 7. The top of ground pads
are also aluminum followed by a series of copper metallization
from metal 7 down to metal 1. Metal 1 provides the ground
shield to minimize the substrate losses due to fringing fields.
Fig. 8 shows the equivalent circuit of the signal pad of the GSG
testing pads. For this case, Rs-pad models the resistive losses due
to metal and the resistivity of the vias. The inductivity of the
signal pad, which is mostly introduced by the vias, is modeled
by Lpad. The fringing capacitance effect between the port
metallization to the metal 1 (ground plane) is modeled by CPORT.
Since the actual ground resides on top of the aluminum layer of
the GSG testing pads, we have series resistance and inductance
that are introduced by the multilayer ground pad, as illustrated
in Fig. 7(c).
RP1
M1
CP1
Bulk/Substrate
PORT 2
RP1
CP1
M1
VCTRL
L1
PORT 1
CP1
CP1
LP1
LP1
CPORT
CPORT
A
LP1
M1 GND Plane
LP1
RG2
A'
VCTRL
Lpad
(a)
VCTRL
RG1
Rs-pad
CPORT
M1
CPORT
R & L GND
metalization
RP1 & LP1
S-to-GND
Parasitics
S to GND
Multilayer
Metalizations
(b)
M1 GND Plane
(a)
Fig. 8. The equivalent circuit for a port: (a) complex model and (b) simplified
model.
(b)
Fig. 9 shows the insertion loss simulation of the GSG testing
pads. The GSG testing pads are capacitive from low frequency
up to 200 GHz and after that they become more inductive. The
parasitic capacitance of the GSG testing pads (CPORT) is
connected in parallel with the signal pad; it acts as an additional
loading capacitance to the input/output port of the switch which
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Forum for Electromagnetic Research Methods and Application Technologies (FERMAT)
TABLE I
COMPONENT VALUES IN THE ENAHNCED CIRCUIT MODEL
L1
M1
M2
RG1
RG2
96pH
80/0.06
80/0.06
10kΩ
10kΩ
RP1
RP2
CP1
CPORT
CDS
CGD
CGS
LP1
0.1Ω 0.1Ω
5fp
50fp
6fp
2fp
2fp
20pH
affects the overall matching performance. The GSG testing pads
introduce about 0.5-dB insertion loss at 60 GHz and about 2-dB
insertion loss at 100 GHz.
The parasitic capacitances associated with the multilayer
metalization of the sources, drains and gates and also the
parasitic capacitances for the sources, drains, gates to
bulk/substrate are extracted. As expected, (CDS, CGD, CGS) are
much larger than (CSB, CDB, CGB) [19].
IV. EXPERIMENTAL VALIDATION
Fig. 11 shows the die micrograph of the SPST switch that has
been fabricated in the 65-nm CMOS technology. The active
area is only 96 µm × 140 µm and the whole chip area including
all testing pads is 340 µm × 340 µm. The measurements from 1
to 100 GHz were performed using Cascade 100-µm
ground-signal-ground (GSG) probes and an Anritsu 110-GHz
on-wafer S-parameter measurement system with a SussTec 12
probe station. The measurements from 110 to 170 GHz were
recently carried out using Cascade Microtech I170–GSG probes
with 100-µm pitch and R&S vector network analyzer, which
was calibrated using line-reflect-reflect-match calibration
technique with WinCal XE software and impedance standard
substrate provided by Cascade Microtech.
Fig. 9. HFSS simulated insertion loss of the testing pads up to 300 GHz.
B. Enhanced Circuit Model
The foundry-provided circuit model is added with the
extracted parasitic components to improve its accuracy at
frequencies higher than 50 GHz. Fig. 10 shows the enhanced
circuit model of the switch. Table I lists the component values in
the enhanced circuit model.
L1
Port 1
CDS1
CPORT
M1
CGD1
RG1
RG2
Port 2
CGD2
M2 C
DS2
Fig.11. The SPST switch die micrograph.
CPORT
CGS2
CGS1
Fig. 12 shows the simulated, modeled, and measured results.
They are in good agreement, which validates the
electromagnetic analysis and circuit modeling. The isolation
behavior of the SPST switch deserves a scrutiny because the
transistors are in their on-state and simulated with the novel
technique illustrated in Fig. 3. It is evident from Fig. 12(c) that
the isolation deteriorates from the frequency of 35 GHz on up to
170 GHz. This can be understood from the pole at 35 GHz
introduced by the parallel resonance due to interaction of
between inductor L1 and the parasitic drain-to-source
capacitances (CDS) of the transistor, the parasitic capacitances of
the ports (CPORT) and the ground capacitances (CP1). From the
isolation circuit simulation, we understand that the inductor L1 is
not completely short-circuited to the ground from 1 to 30 GHz,
even when both transistors are turned on. That is the reason why
VCTRL
RP2
RP1
RP1
RP2
CP1
LP1
LP1
CP1
Fig.10. The enhanced circuit model of the switch.
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Forum for Electromagnetic Research Methods and Application Technologies (FERMAT)
we obtain a finite isolation performance (about 20 dB) at low
frequencies. The isolation continuously improves as the
frequency is increased from 1 to 30 GHz since the impedance of
the inductor continues to increase and, hence, less leakage
current can flow through the inductor during the off-state.
However, as the frequency further increases, the strength of the
coupling within the transistor metalization becomes stronger.
The electromagnetic coupling provides an alternative path for
the current to flow from Port 1 to Port 2 as shown in Fig. 6.
Consequently, the isolation becomes worse as the frequency is
increased.
(c)
Fig. 12. The simulated, modeled, and measured results: (a) Return loss, (b)
Insertion loss, and (c) Isolation.
Clearly, the electromagnetic analysis has provided a deep
physical insight into the switch behavior. However, it has an
inherent limitation, that is, it cannot handle the devices in their
active states for the electron transfer phenomena such as the hot
carrier effect, well-proximity effect, negative-bias temperature
instability, etc. Those active phenomena may lead to mobility
degradation and a shift in the threshold voltage [20].
Furthermore, the analysis cannot handle the shallow trench
isolation induced stress that impacts on the millimeter-wave
performance of the active devices due to change in carrier
mobility, saturation velocity, threshold voltage and other
second-order behaviors [21].
(a)
V. CONCLUSION
The electromagnetic analysis and circuit modeling of the
ultra-wideband SPST switch in the 65-nm CMOS technology up
to millimeter-wave frequencies have been conducted and
validated experimentally. A novel technique that makes it
possible to conduct electromagnetic simulation of an on-state
switching transistor has been proposed for the first time. It has
been shown that the electromagnetic analysis provides a much
deeper physical insight into the switch behavior and predicts the
otherwise unforeseeable parasitic series resonance at high
frequency. Also, the electromagnetic analysis improves circuit
modeling and enhances circuit simulation. However, the
electromagnetic analysis has an inherent limitation, that is, it
cannot handle the devices for the electron transfer phenomena
such as the hot carrier effect, well-proximity effect,
negative-bias temperature instability, etc. Furthermore, the
electromagnetic analysis cannot handle the shallow trench
isolation induced stress that impacts on the millimeter-wave
performance of the active devices due to change in carrier
mobility, saturation velocity, threshold voltage and other
second-order behaviors.
(b)
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Forum for Electromagnetic Research Methods and Application Technologies (FERMAT)
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Alit Apriyana received the B.E. degree in Electrical and
Electronic Engineering from Nanyang Technological
University, Singapore, in 2003, and the M. Phil. degree
in RF and telecommunication engineering from Nanyang
Technological University, Singapore, in 2004. He has
been with Nanyang Technological University, Singapore
since 2010, working towards the Ph.D. degree. From
2004 to 2009, he worked at EPCOS Pte Ltd, Singapore as
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Jin He (SM’13) received the Ph.D. degree from the
Nanyang Technological University, Singapore, in 2011.
He has been working on analog/RF/mm-Wave in both
academia and industry during 2003-2013 in China and
Singapore, respectively, holding positions of Engineer,
Research Associate, Senior Research Engineer,
Scientist, and Project Leader. He joined in Wuhan
University, China in 2013 and is now an Associate
Professor of the School of Physics and Technology,
Wuhan University, China. His current research interests
include
analog/RF/mm-Wave/THz
integrated
circuit
design
in
CMOS/BiCMOS/SiGe for optical and wireless applications.
Dr. He has authored and co-authored over 10 international journal and
conference papers in the area of RF/mm-Wave IC design for wireless
applications. He was promoted to be IEEE Senior Member and has served as a
technical reviewer for the IEEE Transaction on Microwave and Theory
Techniques, the IEEE Transaction on Electron Devices, the IEEE Microwave
and Wireless Components Letters, the Electronics and Telecommunications
Research Institute (ETRL) Journal, and the Journal of Electronic Science and
Technology.
Yueping Zhang (M’03-SM’07-F’10) received the B.E.
and M.E. degrees from Taiyuan Polytechnic Institute and
Shanxi Mining Institute of Taiyuan University of
Technology, Shanxi, China, in 1982 and 1987, respectively
and the Ph.D. degree from the Chinese University of Hong
Kong, Hong Kong, in 1995, all in electronic engineering.
From 1982 to 1984, he worked at Shanxi Electronic
Industry Bureau, from 1990 to 1992, the University of
Liverpool, U. K., and from 1996 to 1997, City University of Hong Kong. From
1987 to 1990, he taught at Shanxi Mining Institute and from 1997 to 1998, the
University of Hong Kong. He was promoted to Professor at Taiyuan University
of Technology in 1996. He is now Professor of Electronic Engineering with the
School of Electrical and Electronic Engineering at Nanyang Technological
University, Singapore. He has researched extensively in the field of radio
science and technology. He has published numerous papers and taken various
US patents.
Dr. Zhang was a Guest Editor of the International Journal of RF and
Microwave Computer-Aided Engineering, an Associate Editor of the
International Journal of Microwave Science and Technology, and an
Associate Editor of the International Journal of Electromagnetic Waves and
Applications. He serves as an Editor of ETRI Journal and an Associate Editor
of the IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION. He also serves
on the Editorial Boards of a large number of Journals including the IEEE
TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES and IEEE
MICROWAVE AND WIRELESS COMPONENTS LETTERS.
He was the recipient of the Sino-British Technical Collaboration Award
(1990) for his contribution to the advancement of subsurface radio science and
technology, the Best Paper Award of the 2nd IEEE/IET International
Symposium on Communication Systems, Networks and Digital Signal
Processing, Bournemouth, U.K. (July 18–20, 2000), and the Best Paper Prize of
the 3rd IEEE International Workshop on Antenna Technology, Cambridge,
U.K. (March 21–23, 2007). He was also the recipient of a William Mong
Visiting Fellowship of the University of Hong Kong (2005) and the S. A.
Schelkunoff Transactions Prize Paper Award of the IEEE Antennas and
Propagation Society (2012). He was the Chair, leading the Singapore Chapter
to win the Best Chapter Award of the IEEE Antennas and Propagation Society
(2013).
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Forum for Electromagnetic Research Methods and Application Technologies (FERMAT)
Manuscript received October 12, 2012.
9