James Watt Nanofabrication Centre @ Glasgow
@ Glasgow
Contact: douglas.Paul@glasgow.ac.uk
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@g g
James Watt Nanofabrication Centre @ Glasgow
In School of Engineering University of Glasgow
In School of Engineering, University of Glasgow
World Bests:
Smallest electron‐beam lithography pattern – 3 nm
Best layer‐to‐layer alignment accuracy 0.46 nm rms
Smallest diamond transistor (50 nm gate length)
Lowest loss silicon optical waveguide (< 0 9 dB/cm)
Lowest loss silicon optical waveguide (< 0.9 dB/cm)
Fastest mode locked laser (2.1 THz)
Highest Q silicon nanowire cavity
>30 Years Nanofabrication at Glasgow
1978 – EBL on converted
SEM i b
SEM in basement
t
2005 – New James Watt
Nanofabrication Centre built
a o ab cat o Ce t e bu t
1989 – our first dedicated
SEM f
SEM for metrology
t l
2006 – New EBL tool
State‐of‐the‐art
State
o t eat
1990 – Leica EBPG5
Fi t UK U i l b t
First UK Uni lab to run
professional installation
2007 – Nanoforum formed
Cross‐disciplinary group
of researchers
of researchers
James Watt Nanofabrication Centre @Glasgow
750m2 cleanroom ‐ pseudo‐industrial operation
Vistec VB6 & EBPG5
18 technicians + 5 research technologists
(PhD level process engineers)
Large number of process modules
Large number of process modules
E‐beam lithography
Processes include: GaAs/AlGaAs, InGaAs/InP,
III V CMOS MMIC
III‐V CMOS, MMICs, optoelectronics, metamaterials
t l t i
t
t i l
http://www.jwnc.gla.ac.uk
9 RIE / PECVD
/
Süss MA6 optical &
nanoimprint
lithography
g p y
4 Metal dep tools
ld
l
4 SEMs: Hitachi S4700
h
Electron Beam Lithography @ Glasgow
Vistec VB6 electron beam lithography:
maximum 200 mm wafer <10 nm minimum feature size (≥4 nm spot)
0.46 nm proprietary layer‐to‐layer alignment
50 keV
0 k and 100 keV
d 100 k operation
i
extra wide field of 1.3 mm
l
laser interferometer stage to 0.62 nm
i t f
t t
t 0 62
50 MHz pattern generator
automated alignment
automated alignment
multi‐substrate load locked
Vistec EBPG5 electron beam lithography:
g p y
maximum 150 mm wafer <10 nm minimum feature size
0 46 nm proprietary layer to layer alignment
0.46 nm proprietary layer to layer alignment
E‐beam Lithography with HSQ Resist
Stephen Thoms
e‐beam
Coat HSQ with tungsten HSQ
tungsten
substrate
SEM backscatter detector
Measured linewidth vs dose
9
8
7
6
5
4
3
16000
50 nm
20000
24000
Dose ( µC cm -2 )
28000
Eb
E‐beam Layer‐to‐Layer Correlation Alignment
L
t L
C
l ti Ali
t
Penrose tile
Normal alignment
marks ‐ 4 squares
Problems: Low statistics
& errors from defects
For correlated alignment For
correlated alignment –>>
sharply peaked autocorrelation
(i.e. ideal is 2D δ‐function) Wiener–Khintchine theorem –>
ideal alignment from perfectly aperiodic pattern
0.46 nm rms layer‐to‐layer alignment
K.E. Docherty et al., Microelect. Eng. 85, 761 (2008)
K.E. Docherty et al., Microelect. Eng. 85, 761 (2008)
nm
nm
Optical and Nanoimprint Lithography
Süss MA6 optical i‐line lithography &
UV nanoimprint lithography – up to 150 mm substrates
Obducat nanoimprint lithography up to 75 mm substrates
Reactive Ion Etch
6 tools for different etch chemistries / applications
Load‐locked Cl chemistry for GaN
& GaAs/AlGaAs etching
CH4/H2 : for selective InGaAs/InP etching
Low damage processes (no reduction
in µ or ns in InGaAs HEMTs)
Dry etches for Al, Ti, W, Au, Pt, Pd metals
Dry etches for Si3N4 and SiO2
ICP Deep Si Bosch process for III‐V on Si/SOI
Dielectric Deposition
3 tools:
PECVD SiO2
PECVD Si3N4
Room temperature ICP PECVD low stress Si3N4 4.6x106 V/cm breakdown for 5 nm films
Complementary selective dry etches for (In)GaAs
National Centre for III-V Technologies
Universities of Sheffield, Cambridge, Glasgow, Nottingham
Wet Chemical Processing
Metallisation
Plassys I: Load‐locked electron beam evaporator, ion‐beam surface prep with 6 sources for Au, Ge, Ni, Pd, NiCr, Ti
Plassys II: Electron beam evaporator Plassys
II: Electron beam evaporator
with 6 sources for Au, Ge, Ni, NiCr, Al, Pt
Plassys III: dc and rf sputter tool with Pl
III d
d f
tt t l ith
6 sources for V, Cr, Cu, W, Al, W/Ti
Thermal evaporator: for non standard materials
Thermal evaporator: for non‐standard materials
Metrology
4 SEMs: Hitachi S900, S3000, S4700 with EDX and Nova NanoSEM S600
2 Digital Instruments AFM, Veeco Dektak
For dry etch / deposition: ellipsometer
QuickTime™ and a
decompressor
are needed to see this picture.
Miscellaneous Tools Jipelec JetFirst Rapid Thermal Annealler (RTA)
p
p
(
)
Up to 1000 ˚C anneal in N2
Veeco Dektak 6M
Electroplating kit
Ellipsometer
Wire bonder – deep access ultrasonic wedge bonder
Wafer scribe
Wafer saw
Process Integration
Process integration is key to obtain functioning devices
Not all individual processes can be integrated for complete devices Heterolayer design must be integrated with full process to maximise device yield
device yield
Heterolayers optimised for etch stop, Schottky barriers and Ohmic y
p
p,
y
contact are available for many III‐V materials
MMICs Technology
50 nm InGaAsT‐gate HEMT process on 100mm wafers
Maximum ID = 0.9 A/mm
Maximum gm = 1.6 S/mm
fT = 550 GHz
fmax = 440 GHz
10 nm T‐gate process in development
Process includes: airbridge technology
P
i l d
i b id
h l
spiral inductors, capacitors
waveguides, antenna
D i (d i & i i ) MBE
Design (device & circuit), MBE growth, foundry, test
h f
d
Circuit demonstrators: 94 & 140 GHz LNAs, 94 GHz mixers
140 GHz LNA
22 nm
II. Thayne et al.,
al
Thin Solid Films
515, 4373 (2007)
Scaling T gate Process to 22 nm
Scaling T‐gate Process to 22 nm
Ti/Pt/Au
50
50 nm SiN
SiN
S. Bentley et al., Microelect. Eng. 85, 1375 (2008)
22 nm T‐gates
ZEB resist
profile
SiN RIE SF6/N2
@ 20W Mobility and carrier density measurements
bl
d
d
used to confirm low damage SiN etching
S. Bentley et al., Microelect. Eng. 85, 1375 (2008)
S. Bentley et al., Microelect. Eng. 85, 1375 (2008)
Metal 1
lift‐off
III‐V CMOS
Statistical variation
of 90 nm devices
of 90 nm devices
Channel mobility
optimisation
Atomic scale
Atomic
scale
interface
characterisation
Oxide
Semiconductor
Predicted
p
performance
calibrated using experimental
p
data
30 nm RIE Tungsten Gates for III‐V CMOS
Low damage W RIE
NEB31 resist
NEB31 resist
ICP SF
ICP
SF6:C4F8
25:15 sccm
200 W, 5 mTorr
X Li et al Microelec Eng 85 996 (2008)
X. Li et al., Microelec. Eng. 85, 996 (2008)
300 K ICP‐CVD Si3N4
spacer deposition
Low damage spacer RIE
RIE SF
RIE
SF6:N2
5:55 sccm
20 W, 15 mTorr
X Li et al Microelec Eng 85 996 (2008)
X. Li et al., Microelec. Eng. 85, 996 (2008)
Electrical Test
In cleanroom:
On‐wafer probing
Probe station with Agilent dc test
Outside cleanroom:
On‐wafer probing up to 150 mm substrates
p
g p
DC to 325 GHz (Agilent B1500 and VNAs)
In situ CV and variable duty cycle pulsed to 50 ns
In‐situ CV and variable duty‐cycle pulsed to 50 ns
Microwave/Millimetre Wave Test & Measurement
VNA suite from MHz to 325 GHz
20 GHz nearfield test range ‐ anechoic chamber
Quantum Cascade Lasers
MIR and THz QCLs fabricated
GaAs/AlGaAs and InP/InGaAs(Sb) supported
Ridge, plasmon and racetrack waveguides demonstrated
Semiconductor Lasers
Semiconductor lasers: ridge, ring, microdisc
GaAs/AlGaAs, InGaAs(P)/InP, GaN
/
,
( )/ ,
G. Mezosi et al., IEEE Phot. Technol. Lett. 21, 88 (2009)
2.0
Fastest mode locked laser at 2.1 THz
1 CRT
1 CRT
1.8
2.1 THz
1.6
Siggnal, A.U.
1.4
1.2
D.A. Yanson et al., IEEE J. Quant. Electron. 38, 244 (2002)
1.0
0
5
10
Delay,
y ps
p
15
Optoelectronics
Pulse shaping using Bragg gratings
L.M. Rivas et al., Opt. Lett. 33, 2425 (2008)
Integrated technologies
(GaAs/AlGaAs;InGaAs/InP;
GaN)
Optoelectronic Modulators
Mach‐Zender
modulators
Photonic crystals
and nanophotonic
modulator
RIE dry etching of gallium nitride (GaN)
SiCl4/SF6/Ar RIE (physical to chemical etching 1:1), 120W, 40mTorr: 650nm HSQ resist
2-D FDTD simulation results
Proc SPIE,
Proc.
SPIE Vol.
Vol 7713,
7713 77131N (2010)
RIE dry etching of gallium nitride (GaN)
SiCl4/SF6/Ar RIE (physical to chemical etching 1:1), 120W, 40mTorr: 650nm HSQ resist
QuickTime™ and a
GIF decompressor
are needed to see this picture.
2 D FDTD simulation results
2-D
Proc. SPIE, Vol. 7713, 77131N, 2010.
ICP dry etching of indium phosphide (InP)
InP/InGaAsP ICP‐RIE: Cl2/Ar/N2 gas mixture
Highly anisotropic process
Highly
anisotropic process resulted in near
resulted in near‐vertical
vertical sidewalls sidewalls
on deeply etched structures, for a single HSQ hard‐mask used.
Nano-sized
features
in InP/InGaAsP-based
micrograph
of high
aspect ratio (~30) material:
etching. SEM
Deeply etched
µm)
andsimultaneously
highly recessedwith
first-order
sidewall
grating(3.2
fabricated
a ridge
waveguide.
ICP dry etching of indium phosphide (InP)
Deep ICP dry etching of InP/AlGaInAs: Cl2/Ar/N2 ICP‐RIE
Smooth transition between InGaAs capping layer and InP, InGaAsP AlGaInAs layers (equal rate etching process)
InGaAsP, AlGaInAs layers (equal‐rate etching process).