Albert-Ludwigs-Universität Freiburg
Analysis of the Potential of Gallium Nitride
Based Monolithic Power Amplifiers in the
Microwave Domain with more than an
Octave Bandwidth
Dissertation
zur Erlangung des Doktorgrades
vorgelegt von
M. Sc. Philippe Dennler
Dekan:
Prof. Dr.-Ing. Yiannos Manoli
Gutachter:
Prof. Dr. rer. nat. Oliver Ambacher
Zweitgutachter:
Prof. Dr.-Ing. Hermann Schumacher
c Universität Freiburg, Juli, 2014
Albert-Ludwigs-Universität Freiburg
Technische Fakultät
Georges-Köhler-Allee 101
D-79110 Freiburg i. Brsg.
www.tf.uni-freiburg.de/
To my wonderful wife Mirjam
and enchanting daughter Loı̈s
iv
Abstract
Broadband power amplifiers are regarded as key components employed in numerous
applications such as test equipment, radar, and communication systems. Recently, there
has been significant investment in the development of high performance microwave
transistors and integrated circuits based on gallium nitride (GaN). Because of their
high electron velocity combined with a high electron sheet charge as well as break
down voltage, GaN based high electron mobility transistors (HEMTs) are promising
candidates to push the boundaries set by other semiconductor materials by orders of
magnitude. The scope of this work is to theoretically and experimentally analyze the
potential of GaN based monolithic broadband high power amplifiers with more than an
octave bandwidth in the microwave domain up to 40 GHz with unprecedented power
levels. The most fundamental theoretical limitation for reactively matched amplifiers
is imposed by the Bode-Fano limit. This technology related figure of merit quantifies
the attainable reflection coefficient for a matching network compensating the reactance
of a single transistor in a given frequency band. A detailed analysis of the Bode-Fano
criterion is performed for the input and output of GaN based HEMTs.
The challenge in designing broadband amplifiers is to present the optimum complex
load to the input and output of each transistor in an arbitrary interconnection in such
a way that they deliver maximum output power or efficiency at all frequencies within a designated band. Because of the high output resistance of GaN transistors, the
Bode-Fano limit at the output is aggravated dramatically as compared to lower voltage technologies such as gallium arsenide (GaAs). However, as calculations show, this
theoretical limitation does not pose the dominating difficulty. The main limiting factor
is the large impedance transformation ratio to be dealt with in the output matching
network, attributable to large gate width devices. Since this limitation is not addressed
by the Bode-Fano criterion, it needs special consideration and is addressed by reference
to filter theory which allows to quantify the filter order of a matching network in terms
of bandwidth and transformation ratio. The interplay between realizable quality factors
and impedances on monolithic integrated circuits is exemplarily shown on designed and
fabricated monolithic broadband power amplifiers with various reactively-matched and
distributed topologies. The analyses imply that for the given technology and targeted
upper frequency and power level, the critical realizable bandwidth ratio of the output matching network for reactively matched amplifier is around B = 3, e.g. 6 GHz to
18 GHz. Higher bandwidth ratios up to B = 6 are demonstrated by distributed ampli-
v
Abstract
fiers, which are by nature not prone to the theoretical limitations affecting reactively
matched amplifiers.
In contrast to the output, the Bode-Fano criterion for the input is dependent on center
frequency and device size. Calculations show that for reasonable device sizes, it poses
a severe theoretical limitation in obtaining an octave bandwidth. Since in a multistage
design two complex impedances face at the interstage, the problem becomes even more severe. In order to overcome this limitation, a novel power amplifier architecture is
proposed, which evades the aggravated matching aspects introduced by designing multistage reactively-matched amplifiers. A dual-stage semi-reactively-matched amplifier
(SRMA) which comprises a distributed active power splitter acting as the driver stage
is introduced. In doing so, a purely real interstage impedance is obtained and therefore
the proposed architecture allows wider bandwidth operation as compared to the conventional reactively-matched multistage topology. A 4.5 W 6 GHz–20 GHz high power
SRMA is designed and realized. The bandwidth ratio is the largest ever reported for a
reactively matched multistage monolithic GaN power amplifier at the given frequency
and output power.
This thesis targets upper frequency limits, which exceed one third of the transit
frequency of the active device. As a consequence, gain is a limited resource for the
broadband amplifiers within the scope of this work. A very attractive way to enhance
the gain of an amplifier is to reduce the Miller effect by using dual-gate active devices.
In order to be able to use dual-gate structures for amplifier design, an accurate model
is needed. A method to accurately describe dual-gate structures is demonstrated up to
18 GHz using a distributed modeling approach. A scalable nonlinear model with varying
total gate width and number of fingers was obtained. The proposed modeling approach
is the first of its kind to accurately describe dual-gate transistors. The knowledge gained from studying the model is put into practice by proposing advanced dual-gate
structures to improve the stability, gain, maximum output power, and efficiency of the
devices. Designed and manufactured structures show improvements in all the aforesaid
disciplines as compared to a conventional dual-gate design.
However, dual-gate devices suffer from strong gain compression at high driving power
levels and therefore are not suitable to be operated in saturation in power amplifier
stages. Therefore, dual-gate transistors are preferably used in driver stages to boost
the gain of the amplifier. A dual-stage 6 GHz to 37 GHz distributed amplifier with
a measured S21 of (17 ± 1) dB, demonstrates the usability of this concept. Besides the
enhanced gain, the said amplifier was optimized for maximum output power by applying
a nonuniform distributed approach. With more than 1 W output power over the entire
frequency band, the design shows the highest ever reported power for a monolithic solid
state amplifier at this frequency range.
vi
Zusammenfassung
Der Einsatzbereich von Breitband-Leistungsverstärkern reicht von Kommunikationssystemen über Radaranwendungen bis hin zur Messtechnik. In den letzten Jahren wurde
erheblich in die Entwicklung leistungsstarker Galliumnitrid-basierter (GaN-basierter)
Mikrowellentransistoren und integrierten Schaltungen investiert. Bedingt durch die hohe
Elektronengeschwindigkeit in Kombination mit einer hohen Elektronen-Flächenladung
und Durchbruchspannung versprechen GaN-basierte High-Electron-Mobility Transistoren (HEMTs) die durch andere Materialsysteme definierten Grenzen um Größenordnungen zu verschieben. Im Rahmen dieser Arbeit soll das Potential von GaN-basierten
monolithischen Breitband-Hochleistungsverstärkern mit mehr als einer Oktave Bandbreite im Mikrowellenbereich bis zu 40 GHz mit bisher unerreichten Ausgangsleistungen
theoretisch und experimentell analysiert werden. Die grundlegendste theoretische Einschränkung für reaktiv angepasste Verstärker ist durch die Bode-Fano Grenze auferlegt.
Diese technologiebezogene Kenngröße ist ein Maß für den erzielbaren Reflexionsfaktor
für ein Anpassnetzwerk zur Kompensation der Reaktanz eines einzelnen Transistors in
einem gegebenen Frequenzband. Eine detaillierte Analyse des Bode-Fano Kriteriums
für den Ein- und Ausgang eines GaN-basierten HEMTs ist aufgezeigt.
Die Herausforderung bei der Entwicklung von Breitband-Verstärkern liegt darin, jedem einzelnen Transistor in einer beliebigen Zusammenschaltung die optimale komplexe
Last am Ein- und Ausgang anzubieten, sodass deren Ausgangsleistung oder Effizienz
über ein festgelegtes Frequenzband maximiert wird. Bedingt durch den hohen Ausgangswiderstand von GaN-Transistoren wird die Bode-Fano Grenze am Ausgang im
Vergleich zu Technologien mit niedrigerer Betriebsspannung, wie etwa Galliumarsenid
(GaAs), drastisch verschärft. Berechnungen zeigen allerdings, dass diese theoretische
Einschränkung nicht die dominierende Schwierigkeit darstellt. Die Haupteinschränkung
rührt vom großen im Ausgangsnetzwerk aufzubringenden Transformationsverhältnis
her, bedingt durch Bauelemente mit großer Gateweite. Da diese Limitierung vom BodeFano Kriterium nicht behandelt wird, erfordert sie eine separate Betrachtung. Dies geschieht mit Hilfe der Filtertheorie, welche die Filterordnung eines Anpassnetzwerks mit
der Bandbreite und dem Transformationsverhältnis in Zusammenhang stellt. Das Zusammenspiel zwischen realisierbaren Güten und Impedanzen in monolithisch integrierten Schaltkreisen wird beispielhaft anhand von entwickelten und fabrizierten monolithischen Breitband-Leistungsverstärkern mit unterschiedlichen reaktiv-angepassten und
verteilten Topologien aufgezeigt. Die Analysen besagen, dass für die gegebene Technolo-
vii
Zusammenfassung
gie, angestrebte obere Frequenz und Ausgangsleistung, das kritische realisierbare Bandbreitenverhältnis des Ausgangsanpassungsnetzwerks für reaktiv-angepasste Verstärker
bei rund B = 3 liegt, z.B. 6 GHz bis 18 GHz. Höhere Bandbreitenverhältnisse bis zu
B = 6 werden anhand von verteilten Verstärkern demonstriert. Diese unterliegen von
Natur aus nicht den theoretischen Limitierungen, welche reaktiv-angepasste Verstärker
einschränken.
Im Gegensatz zum Ausgang ist das Bode-Fano Kriterium für den Eingang abhängig
von der Mittenfrequenz und der Bauelementgröße. Berechnungen zeigen, dass das Kriterium für sinnvolle Bauelementgrößen für Bandbreiten von mehr als einer Oktave
durchaus eine ernstzunehmende theoretische Beschränkung darstellt. Für mehrstufige Verstärkerentwürfe wird das Problem noch einschneidender, da in der Zwischenstufe
zwei komplexe Impedanzen aufeinandertreffen. Um diese Einschränkung zu überwinden
wird eine neuartige Leistungsverstärker Architektur vorgeschlagen. Diese umgeht die
verschärften Anforderungen an das Anpassnetzwerk in der Zwischenstufe von mehrstufigen reaktiv-angepassten Verstärkern. Ein zweistufiger semi-reaktiv-angepasster Verstärker (SRMA) mit einem verteilten aktiven Leistungsteiler, welcher als Treiberstufe
fungiert, wird vorgestellt. Auf diese Weise wird eine rein reelle Zwischenstufen-Impedanz
geschaffen. Dadurch erreicht die vorgeschlagene Architektur größere Bandbreiten als
konventionell reaktiv-angepasste mehrstufige Topologien. Ein 4.5 W 6 GHz bis 20 GHz
Hochleistungs SRMA wurde entwickelt und realisiert. Das dabei erreichte Bandbreitenverhältnis ist das größte jemals publizierte für einen reaktiv-angepassten mehrstufigen
monolithischen GaN-Leistungsverstärker bei der gegebenen Frequenz und Ausgangsleistung.
Die in dieser Arbeit angestrebten oberen Frequenzgrenzen überschreiten einen Drittel
der Transitfrequenz des aktiven Bauelements. Als Konsequenz daraus ist die Verstärkung eine streng limitierte Ressource für die Breitbandverstärker dieser Studie. Eine
attraktive Möglichkeit, den Gewinn eines Verstärkers zu erhöhen, ist die Reduktion des
Millereffekts durch den Einsatz von Dual-Gate Transistoren. Um Dual-Gate Strukturen für die Entwicklung von Verstärkern einsetzen zu können, ist ein exaktes Modell
erforderlich. Eine auf einen verteilten Modellierungsansatz gestützte Methode, die es
erlaubt, Dual-Gate Strukturen bis 18 GHz präzise zu beschreiben, wird aufgezeigt. Ein
skalierbares nichtlineares Modell für eine variable Gateweite und Fingeranzahl wurde
erlangt. Der vorgeschlagene Modellierungsansatz ist der erste seiner Art, um Dual-Gate
Transistoren akkurat zu beschreiben. Die durch das Studium des Modells erlangten Erkenntnisse werden anhand von Vorschlägen für die Weiterentwicklung von Dual-Gate
Strukturen in die Praxis umgesetzt. Sie verbessern die Stabilität, Verstärkung, maximale Ausgangsleistung und Effizienz der Bauelemente. Fabrizierte weiterentwickelte
Strukturen zeigen im Vergleich zu konventionellen Dual-Gate Transistoren Verbesserungen in all den obengenannten Disziplinen.
Dual-Gate Bauelemente haben allerdings den Nachteil erhöhter Kompression unter
hoher Aussteuerung und sind deshalb ungeeignet, um in Leistungsverstärker Endstufen
in Sättigung betrieben zu werden. Aus diesem Grund werden Dual-Gate Transistoren
viii
Zusammenfassung
vorzugsweise in Treiberstufen eingesetzt und deutlich unterhalb der Sättigung betrieben, um die Verstärkung des Sytems zu erhöhen. Ein zweistufiger verteilter 6 GHz bis
37 GHz Verstärker mit einem gemessenen S21 von (17 ± 1) dB demonstriert die Nutzbarkeit dieses Konzepts. Neben der erhöhten Verstärkung wurde der besagte Verstärker
durch den Einsatz eines nicht uniform verteilten Ansatzes auf maximale Ausgangsleistung optimiert. Mit mehr als einem Watt Ausgangsleistung über den gesamten Frequenzbereich zeigt die Schaltung die höchste je publizierte Leistung für einen monolithischen Halbleiterverstärker in diesem Frequenzbereich.
ix
Zusammenfassung
x
Contents
Acronyms
1 Introduction
1.1 Solid State Broadband Power Amplifiers . . . . . . . . . . .
1.1.1 The Potential of Gallium Nitride . . . . . . . . . . .
1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 State of the Art Solid State Broadband Power Amplifiers .
1.3.1 GaN Based Solid State Broadband Power Amplifiers
xxiii
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2 Gallium Nitride Based Monolithic IC Technology
2.1 Semiconductor Technology for AlGaN/GaN Transistors . . .
2.1.1 The Conventional GaN HEMT . . . . . . . . . . . . .
2.2 Degradation Mechanisms in GaN Heterostructures . . . . . .
2.3 250 nm MMIC Technology . . . . . . . . . . . . . . . . . . . .
2.3.1 250 nm GaN Technology Performance . . . . . . . . .
2.4 100 nm MMIC Technology . . . . . . . . . . . . . . . . . . . .
2.4.1 Scaling Properties of HEMTs Regarding Gate Length
2.4.2 100 nm GaN Technology Performance . . . . . . . . .
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3 Power HEMT Structures for Broadband Applications
3.1 Figures of Merit of Broadband Active Devices . . . . . . . . . . .
3.1.1 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 Two-Port Power Gain Definitions . . . . . . . . . . . . . .
3.1.3 Transit Frequency and Maximum Frequency of Oscillation
3.1.4 Drain Efficiency and Power Added Efficiency . . . . . . .
3.2 DC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Power Density . . . . . . . . . . . . . . . . . . . . . . . .
3.3 RF Performance . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 Load Pull Device Characterization . . . . . . . . . . . . .
3.4 The Common-Source HEMT as a Reference . . . . . . . . . . . .
3.4.1 Small Signal Model . . . . . . . . . . . . . . . . . . . . . .
3.5 The Bode-Fano Criterion Applied on GaN HEMTs . . . . . . . .
3.5.1 Bode-Fano Criterion for the Output of a GaN HEMT . .
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xi
Contents
3.6
3.7
3.5.2 Bode-Fano Criterion for the Input of a GaN HEMT
3.5.3 Conclusions on the Bode-Fano Criterion . . . . . . .
Dual-Gate and Cascode GaN HEMTs . . . . . . . . . . . .
3.6.1 Definition of Cascode and Dual-Gate Devices . . . .
3.6.2 Stability Considerations of Dual-Gate HEMTs . . .
Advanced Dual-Gate Structures . . . . . . . . . . . . . . . .
3.7.1 Fabricated Advanced Dual-Gate Structures . . . . .
3.7.2 Advanced Dual-Gate Results . . . . . . . . . . . . .
3.7.3 Conclusions on Dual-Gate HEMTs . . . . . . . . . .
4 GaN Dual-Gate HEMT Characterization and Modeling
4.1 Layout and Realization of Dual-Gate HEMTs . . . .
4.2 Distributed Dual-Gate HEMT Model . . . . . . . . .
4.2.1 Stability Considerations . . . . . . . . . . . .
4.3 Large Signal Model . . . . . . . . . . . . . . . . . . .
4.4 Dual-Gate HEMT Power Amplifier . . . . . . . . . .
4.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . .
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5 Verification of Broadband Amplifier Concepts on MMIC Level
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5.1 Bandwidth Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.2 Review of Various Broadband Architectures . . . . . . . . . . . . . . . . 70
5.2.1 Reactively Matched Amplifiers . . . . . . . . . . . . . . . . . . . 71
5.2.2 Traveling Wave Amplifiers . . . . . . . . . . . . . . . . . . . . . . 71
5.3 The Broadband Amplifier Design Problem . . . . . . . . . . . . . . . . . 73
5.3.1 Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.4 Theoretical Limitations for the Design of Equalizers . . . . . . . . . . . 76
5.4.1 The Kramers-Kronig Relations . . . . . . . . . . . . . . . . . . . 76
5.4.2 The Bode Gain-Phase Relation . . . . . . . . . . . . . . . . . . . 77
5.5 Impedance Level Transformation for GaN Devices . . . . . . . . . . . . 79
5.5.1 Constant Q Matching . . . . . . . . . . . . . . . . . . . . . . . . 79
5.5.2 Chebyshev Impedance Transforming Networks of Low-Pass Filter
Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.6 Reactively Matched GaN Power Amplifier MMICs . . . . . . . . . . . . 84
5.6.1 Dual-Gate HEMT Reactively Matched Amplifiers . . . . . . . . . 86
5.6.2 Bandwidth Limiting Effects in Multistage Power Amplifiers . . . 88
5.7 Distributed GaN Power Amplifier MMICs . . . . . . . . . . . . . . . . . 90
5.7.1 The NDPA Approach for GaN Based Distributed Amplifiers . . 91
5.7.2 Design Limitations for GaN Distributed Amplifiers . . . . . . . . 92
5.7.3 Ku Band Distributed Dual-Gate HEMT Power Amplifier . . . . 97
5.8 Millimeter-Wave Distributed Power Amplifiers . . . . . . . . . . . . . . 99
5.8.1 Single-Stage NDPA MMIC . . . . . . . . . . . . . . . . . . . . . 100
5.8.2 Dual-Stage NDPA MMIC . . . . . . . . . . . . . . . . . . . . . . 100
5.8.3 Measured Large Signal Results . . . . . . . . . . . . . . . . . . . 102
xii
Contents
5.8.4 Dual-Stage NDPA with Dual-Gate Driver Stage . . . . . . . . . .
Semi-Reactively-Matched Amplifier . . . . . . . . . . . . . . . . . . . . .
5.9.1 Introduction of a Novel Amplifier Architecture . . . . . . . . . .
5.9.2 Distributed Active Power Splitter Driver Stage . . . . . . . . . .
5.9.3 Reactively-Matched Power Amplifier Stage . . . . . . . . . . . .
5.9.4 Broadband High Power Semi-Reactively-Matched Amplifier MMIC
5.10 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9
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6 Conclusion and Outlook
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A
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A.1 Relevant Equations . . . . . . . . . . . . . . . . . . . . .
A.1.1 Effective Dielectric Constant of a Microstrip Line
A.1.2 Characteristic Impedance of Microstrip Lines . .
A.2 Detailed Overview of the Designed MMICs . . . . . . .
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References
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List of Publications
137
xiii
Contents
xiv
List of Figures
1.1
1.2
1.3
2.1
2.2
2.3
2.4
3.1
3.2
3.3
3.4
Illustration of the benefits of a broadband power amplifier design over a
narrowband solution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE frequency bands for electromagnetic frequencies for radio and radar.
State of the art GaAs pHEMT based broadband PA monolithic microwave integrated circuits (MMICs). Center of ellipses = center frequency and output power on the x-axis and left y-axis, respectively.
Horizontal axis of ellipses = bandwidth, vertical axis = gain. . . . . . . .
Schematic cross section of a conventional 250 nm AlGaN/GaN heterostructure and simulated conduction band diagram and electron concentration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output and transfer characteristics of an n-channel depletion-mode field
effect transistor (FET). . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematic cross section of the full IAF AlGaN/GaN HEMT MMIC process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Photograph of a fully processed 4 × 100 µm GaN HEMT and cross section
scanning electron micrographs of the gate area. . . . . . . . . . . . . . .
Simplified layout of an eight-finger HEMT. . . . . . . . . . . . . . . . .
Common-source HEMTs in various via configurations. . . . . . . . . . .
Definition of the K-point on the example of an 8 × 75 µm GaN25 device.
Simulation of the dependence of the K-point on total gate width (TGW)
by means of scalable 8-term small signal HEMT models. . . . . . . . . .
3.5 Simplified shorted equivalent circuit of an intrinsic HEMT for the determination of the transit frequency fT . . . . . . . . . . . . . . . . . . . . .
3.6 Simulated fT and fmax of an 8 × 75 µm HEMT using a small signal model.
3.7 DC equivalent circuit of a HEMT. . . . . . . . . . . . . . . . . . . . . .
3.8 Measured normalized DC I-V characteristics for a 2 × 50 µm HEMT. Vgs
is varied from =2 V to 2 V, the saturation current is 1130 mA mm=1 . . .
3.9 Measured normalized DC transconductance gm and drain current Id for
a 2 × 50 µm HEMT at Vds = 7 V and Vds = 30 V. . . . . . . . . . . . . . .
3.10 DC output characteristics with loadline and quiescent point Q for class-A
operation of a HEMT. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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xv
List of Figures
3.11 Simplified RF equivalent output circuit of a HEMT. . . . . . . . . . . .
3.12 Frequency trajectory of the generator reflection coefficient Γgen of a 1 mm
HEMT from DC to 20 GHz. . . . . . . . . . . . . . . . . . . . . . . . . .
3.13 Iso-contours of output power obtained by load pull (LP) simulation of a
1 mm device with dependence of ΓL,opt on frequency from DC to 20 GHz.
3.14 Measured output power of an 8 × 125 µm HEMT with 0.8 µm shield at
10 GHz (Vds = 30 V, Id,DC = 100 mA mm=1 ). . . . . . . . . . . . . . . . .
3.15 Load pull frequency sweep of a 6 × 75 µm HEMT from 6 GHz to 18 GHz
(3rd -order polynomial data fit). Output power, gain, and efficiencies are
measured at a load tuned for maximum power added efficiency (PAE)
(Vds = 30 V, Id,DC = 100 mA mm=1 ). . . . . . . . . . . . . . . . . . . . .
3.16 Small signal equivalent circuit of a HEMT. . . . . . . . . . . . . . . . .
3.17 Two-port network representation using Y parameters. . . . . . . . . . .
3.18 Comparison of the approximated maximum stable gain (MSG) after
(3.33) and the exact MSG after (3.32) versus frequency for an intrinsic 8 × 125 µm HEMT. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19 Reference planes at the gate and drain of a HEMT for model extraction.
3.20 Illustration of the meaning of the Bode-Fano criterion; note that the
Smith chart is normalized to 15 Ω. . . . . . . . . . . . . . . . . . . . . .
3.21 Definition of τ and Γ for Bode-Fano networks. . . . . . . . . . . . . . . .
3.22 Illustration of the Bode-Fano criterion. . . . . . . . . . . . . . . . . . . .
3.23 Equivalent circuit of the input of a GaN HEMT in common-source configuration and simplified configurations with complex input impedance
Zg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.24 Simplified schematic of the cascode topology. . . . . . . . . . . . . . . .
3.25 Photograph of a 6 × 75 µm discrete cascode structure. . . . . . . . . . .
3.26 Layout of an 8 × 75 µm dual-gate HEMT. Yellow = METG, red = MET1,
brown = OHM, orange = GATE (see Fig. 3.26 for layer definitions).
Gray = MET1 + METG metal stack, blue = airbridge. . . . . . . . . . . .
3.27 Equivalent circuit configuration and schematic cross section of a dualgate HEMT in GaN25 technology. . . . . . . . . . . . . . . . . . . . . .
3.28 S22 versus frequency of an 8 × 100 µm dual-gate HEMT. . . . . . . . . .
3.29 HEMT in common-source and common-gate configuration with feedback
elements critical for device stability. . . . . . . . . . . . . . . . . . . . .
3.30 FET with open source. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.31 Equivalent circuit of a FET with open source. . . . . . . . . . . . . . . .
3.32 Two-port network representation of the FET with open source. . . . . .
3.33 < {Yeff } as a function of frequency for the simplified intrinsic equivalent
circuit (neglecting Rgd and τgs ) of an 8 × 125 µm HEMT. . . . . . . . .
3.34 < {Yeff } as a function of frequency for the complete 8-term intrinsic
equivalent circuit of an 8 × 125 µm HEMT. . . . . . . . . . . . . . . . .
xvi
25
26
27
27
28
29
30
31
32
33
34
35
38
43
43
44
45
45
46
46
46
47
49
49
List of Figures
3.35 Layout of an 8 × 75 µm advanced dual-gate (ADG) HEMT.
Green = MET1 + GATE metal-insulator-metal (MIM) capacitor,
red = MET1, brown = OHM, orange = GATE, gray = MET1 + METG
metal stack, blue = airbridge. . . . . . . . . . . . . . . . . . . . . . . . .
3.36 Detail extracts of ADG 2 to ADG 5. ADG 2 to ADG 4 = gate bus G2 as
electrode of the MIM capacitor CRF . ADG 5 = identical to ADG 1, but
without the ohmic metal strip between the gates. . . . . . . . . . . . . .
3.37 Photographs of two variants of 8 × 75 µm ADG HEMTs with
GATE + MET1 MIM capacitor CRF . . . . . . . . . . . . . . . . . . . . .
3.38 Small and large signal comparison of two ADG structures with and
without ohmic metal strip between the gates (Vds = 30 V, Vg2 = 6 V, and
Id,DC = 100 mA mm=1 ). . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.39 |S22 | of ADG 2 and ADG 3 without and with source connected capacitor
(S cons), respectively (Vds = 30 V, Vg2 = 6 V, and Id = 100 mA mm=1 ). .
3.40 Small and large signal comparison of two ADG devices without and
with source connected field plate (SH) (Vds = 30 V, Vg2 = 6 V, and
Id,DC = 100 mA mm=1 ). . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.41 Constant output gain circles and optimum output power loads at 18 GHz
of an ADG HEMT without and with shield, ADG 3 and ADG 4, respectively. Red = w/o SH, blue = w/ SH, step size = 1 dB, green = optimum
power loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.42 Maximum stable gain and maximum available gain of the different investigated 6 × 75 µm cascode structures versus frequency from 1 GHz to
50 GHz (Vds = 30 V, Vg2 = 6 V, and Id = 100 mA mm=1 ). . . . . . . . . .
3.43 Magnitude of S22 of the investigated cascode structures versus frequency
from 0.1 GHz to 50 GHz (Vds = 30 V, Vg2 = 6 V, and Id = 100 mA mm=1 ).
3.44 Power sweep at f = 18 GHz for the investigated cascode structures
(Vds = 30 V, Vg2 = 6 V, and Id,DC = 100 mA mm=1 ). . . . . . . . . . . . .
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Equivalent small signal circuit of a dual-gate HEMT. . . . . . . . . . . .
Chip photograph of an 8 × 100 µm dual-gate HEMT with stabilization
resistor and radio frequency (RF)-capacitor with enlarged dual-gate region. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplified block diagram of the dual-gate slice model for a total number
of nF gate fingers and nS slices. . . . . . . . . . . . . . . . . . . . . . . .
Simplified equivalent circuit of a GaN dual-gate FET. . . . . . . . . . .
Measured and modeled critical small signal parameters of an 8 × 100 µm
device in the 0.1 GHz to 25 GHz range (Vds = 30 V, Vg1 = =2.2 V,
Vg2 = 6 V, and Id = 100 mA mm=1 ). . . . . . . . . . . . . . . . . . . . . .
Simulation of the effect of Rstab on |S22 | for an 8 × 100 µm device. . . .
Measured and modeled gain and K-factor of two 6-finger devices in
the 0.1 GHz to 25 GHz range (Vds = 30 V, Vg1 = =2.2 V, Vg2 = 6 V, and
Id = 100 mA mm=1 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
51
52
53
53
54
55
56
57
57
60
60
61
62
62
63
64
xvii
List of Figures
Measured and modeled power sweeps of V1 and V2 of an 8 × 100 µm
device. (Vds = 35 V, Vg1 = =2.3 V, Vg2 = 6 V, and Id,DC = 100 mA mm=1 ,
f = 16 GHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Photograph of the microstrip line (MSL) single-stage Ku band high power
cascode amplifier MMIC (2.75 × 2.25 mm2 ). . . . . . . . . . . . . . . . .
4.10 Simulated and measured small signal parameters of the single-stage dualgate power amplifier (PA) in the frequency range 14 GHz to 18 GHz
(Vds = 30 V, Vg1 = =2.4 V, Vg2 = 6 V, Id = 100 mA mm=1 ). . . . . . . . .
4.11 Simulated and measured power sweeps of the single-stage dual-gate PA at
f = 16 GHz (Vds = 35 V, Vg1 = =2.4 V, Vg2 = 6 V, Id,DC = 100 mA mm=1 ).
4.8
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
xviii
Schematic diagram of a reactively matched amplifier. . . . . . . . . . . .
Simplified schematic of a traveling wave amplifier (TWA). . . . . . . . .
Illustration of the broadband power amplifier design problem. . . . . . .
General design procedure for a power amplifier. . . . . . . . . . . . . . .
Input and output signal for a system with impulse-response function g(t).
Illustration of the broadband power amplifier design problem. . . . . . .
Resistive and reactive matching networks after [67]. . . . . . . . . . . . .
Frequency compensated matching network after [67]. . . . . . . . . . . .
Illustration of the concept of constant Q matching. . . . . . . . . . . . .
General form of low-pass impedance transforming structures with definition for normalized prototype element values. . . . . . . . . . . . . . .
Normalized frequency response of an 8th order low-pass Chebyshev
impedance transforming network (r = 12, B = 3, αmax = 0.4 dB). . . . . .
Contour plot to determine the filter order required for a certain
bandwidth-impedance ratio pairing for αmax = 0.4 dB. 2m = filter order,
r = transformation ratio of the matching network, B = ratio bandwidth,
αmax = maximum ripple. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip photographs of two versions of the broadband 18 GHz dynamic
evaluation circuit (DEC) (2 × 1.5 mm2 ). . . . . . . . . . . . . . . . . . .
Measured small signal parameters wafer mapping in the frequency range
from 0.1 GHz to 26 GHz (Vds = 30 V, Id = 100 mA mm=1 ) of 22 out of 24
cells of the 18 GHz DEC V2. . . . . . . . . . . . . . . . . . . . . . . . .
Measured frequency and power sweep of the 20 GHz DEC V2 (Vds = 30 V
and Id,DC = 100 mA mm=1 ). . . . . . . . . . . . . . . . . . . . . . . . . .
Chip photographs of the two versions of the dual-stage dual-gate power
amplifiers (4 × 2.5 mm2 and 3.5 × 2.5 mm2 ). . . . . . . . . . . . . . . . .
Measured small signal parameters of the dual-stage dual-gate PAs
in the frequency range from 5 GHz to 25 GHz (Vds = 30 V, Vg2 = 6 V,
Id = 100 mA mm=1 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measured power sweeps of the dual-stage dual-gate PAs at f = 16 GHz
(Vds = 30 V, Vg1 = =2.4 V, Vg2 = 6 V, Id,DC = 100 mA mm=1 ). . . . . . . .
Illustration of output reflection coefficient traveling over frequency. . . .
65
65
66
67
71
72
73
75
77
78
79
80
80
81
82
84
85
86
86
87
87
88
89
List of Figures
5.20 Schematic of a conventional reactively-matched dual-stage power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.21 Illustration of reflection coefficients between two consecutive stages traveling in opposite directions. . . . . . . . . . . . . . . . . . . . . . . . . .
5.22 Simplified schematic of the basic NDPA topology. . . . . . . . . . . . . .
5.23 Layout of the tapered drain line of an NDPA. . . . . . . . . . . . . . . .
5.24 Microstrip line with substrate parameters for the GaN25 and GaN10
processes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.25 Microstrip line width as a function of impedance for the GaN25 and
GaN10 MSL processes. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.26 Flattening of the loadline by increasing Vmax . . . . . . . . . . . . . . . .
5.27 Quadratic increase of the maximum output power with increasing Vds in a
distributed power amplifier (DPA) for multiple minimum characteristic
impedances Z0 ,min with corresponding line widths Wl for the GaN25
process (Vknee = 6 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.28 Photograph of the advanced dual-gate HEMT nonuniform distributed
power amplifier MMIC (4.5 × 2.75 mm2 ). . . . . . . . . . . . . . . . . . .
5.29 Measured small signal parameters of the dual-gate non-uniform distributed power amplifier (NDPA) in the 0.1 to 25 GHz range (Vds = 15 V,
Vg1 = =1.4 V, Vg2 = 6 V, Id = 100 mA mm=1 ). . . . . . . . . . . . . . . .
5.30 Measured frequency and power sweeps of the dual-gate NDPA
(3rd -order polynomial data fit, Vds = 20 V, Vg1 = =1.6 V, Vg2 = 8 V,
Id,DC = 100 mA mm=1 ). . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.31 Photograph of the single-stage NDPA (2.5 × 1.5 mm2 ). . . . . . . . . . .
5.32 Simulated and measured small signal parameters of the single-stage
NDPA in the 0.1 to 60 GHz range (Vds = 15 V, Id = 300 mA mm=1 ). . . .
5.33 Photograph of the dual-stage NDPA (5 × 1.5 mm2 ). . . . . . . . . . . . .
5.34 Simulated and measured small signal parameters of the dual-stage NDPA
in the 0.1 to 60 GHz range (Vds = 15 V, Id = 300 mA mm=1 ). . . . . . . .
5.35 Simulated and measured frequency and power sweeps of the single-stage
NDPA (Vds = 15 V and Id,DC = 200 mA mm=1 ). . . . . . . . . . . . . . .
5.36 Simulated and measured frequency and power sweep of the dual-stage
NDPA (Vds = 15 V and Id,DC = 200 mA mm=1 ). . . . . . . . . . . . . . .
5.37 Schematic and photograph of a 4 × 45 µm dual-gate HEMT structure. .
5.38 Photograph of the dual-stage dual-gate NDPA (5 × 1.5 mm2 ). . . . . . .
5.39 Simulated and measured small signal parameters of the dualstage dual-gate NDPA in the 0.1 GHz to 50 GHz range (Vds = 15 V,
Id = 300 mA mm=1 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.40 Simulated and measured frequency sweep of the dual-stage NDPA at
Pin = 20 dBm (Vds = 15 V and Id,DC = 300 mA mm=1 ). . . . . . . . . . .
5.41 Measured power sweeps of the dual-stage NDPA with DG driver-stage
(Vds = 15 V and Id,DC = 300 mA mm=1 ). . . . . . . . . . . . . . . . . . .
89
90
91
92
93
94
96
97
98
98
99
100
101
101
102
102
103
104
105
106
106
107
xix
List of Figures
5.42 Simplified schematic of the basic semi-reactively-matched power amplifier
topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.43 Conventional parallel circuit of two HEMTs and arrangement with short
drain connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.44 Schematic of the layout of the semi-reactively-matched amplifier. . . . .
5.45 Schematic cross section of a double-deck MIM capacitor with indicated
odd-mode suppression resistor Rodd . . . . . . . . . . . . . . . . . . . . .
5.46 Photograph of the semi-reactively-matched dual-stage high power amplifier MMIC, RFin is at the bottom, RFout at the top (4.5 × 4.25 mm2 ). .
5.47 Photograph of an 8 × 90 µm individual source via (ISV) HEMT with RF
pads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.48 Small signal parameters of the semi-reactively-matched PA in the
0.1 GHz to 30 GHz range (Vds = 30 V, Id = 100 mA mm=1 ). . . . . . . . .
5.49 Simulated and measured frequency sweep at Pin = 24 dBm (Vds = 30 V
and Id,DC = 100 mA mm=1 ). . . . . . . . . . . . . . . . . . . . . . . . . .
5.50 Measured power sweep at the upper band edge (f = 20 GHz, Vds = 30 V
and Id,DC = 100 mA mm=1 ). . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
6.2
6.3
6.4
xx
State of the art GaN based broadband PA MMICs in contrast to the designed and manufactured MMICs in this work. Center of ellipses = center
frequency and output power on the x-axis and left y-axis, respectively.
Horizontal axis of ellipses = bandwidth, vertical axis = gain. Red = this
work, blue = other work, green = other work on IAF GaN25 process. . .
Ultra-wideband transmit module demonstrator for multi-function defense AESA applications. Photograph courtesy of Airbus Defence and
Space, Ulm, Germany [88]. . . . . . . . . . . . . . . . . . . . . . . . . .
Simplified schematic of the three-stage semi-reactively-matched power
amplifier topology with distributed interstage. . . . . . . . . . . . . . . .
Simulated small and large signal performance of the designed 10 W
SRMA MMIC (Vds = 35 V and Id,DC = 100 mA mm=1 ). . . . . . . . . . .
108
109
110
110
111
112
112
113
113
118
119
120
121
List of Tables
3.1
3.2
3.3
3.4
3.5
5.1
5.2
Typical small signal equivalent circuit element values, extracted from 3
different 8 × 125 µm GaN HEMTs at Vds = 30 V and gm = gm,max : 2-via
no shield, 2-via 1.3 µm shield, and ISV 1.3 µm shield. . . . . . . . . . . .
Comparison of load pull data and Bode-Fano bandwidth for GaN and
GaAs technologies. IAF ISV is an 8 × 125 µm GaN25 device with 0.9 µm
shield, TQ GaN and TQ GaAs are Triquint 10 × 125 µm GaN and
16 × 75 µm GaAs devices, respectively [100, 103]. . . . . . . . . . . . . .
Comparison of small signal intrinsic input element values and BodeFano bandwidth for GaN and GaAs technologies. IAF ISV = 8 × 125 µm
GaN25 with 0.9 µm shield, TQ GaN and TQ GaAs = Triquint
10 × 125 µm GaN and 16 × 75 µm GaAs, respectively [100, 103]
(Vds = 30 V, gm = gm,max ). . . . . . . . . . . . . . . . . . . . . . . . . . .
Designed 8 × 75 µm structures ADG 1 to ADG 5. ADG 1 = basic structure according Fig. 3.35. ADG 2 to ADG 4 = gate bus G2 as electrode of
the MIM capacitor CRF . ADG 5 = identical to ADG 1, but without the
ohmic metal strip between the gates. . . . . . . . . . . . . . . . . . . . .
Compared 6 × 75 µm HEMT structures.
CAS = discrete cascode structure, dual-gate (DG) = conventional dual-gate structure,
ADG = advanced dual-gate structure. . . . . . . . . . . . . . . . . . . . .
Overview of the designed MMICs. Topologies: RMA = reactivelymatched amplifier, NDPA = non-uniform distributed power amplifier,
SRMA = semi-reactively-matched amplifier. Devices: CS = commonsource, DG = dual-gate. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ranges of realizable line widths and characteristic impedances per mm
gate width, for GaN25 and GaN10 technologies. . . . . . . . . . . . . . .
32
37
41
51
55
74
95
A.1 Detailed overview of all designed MMICs discussed in this work. Topologies: RMA = reactively-matched amplifier, NDPA = non-uniform distributed power amplifier, SRMA = semi-reactively-matched amplifier.
Devices: CS = common-source, DG = dual-gate. . . . . . . . . . . . . . . 125
xxi
List of Tables
xxii
Acronyms
2DEG
Two dimensional electron gas
ADG
Advanced dual-gate
ADS
Advanced Design System
AESA
Active electronically scanned antenna
AlGaN
Aluminum gallium nitrid
AlGaN/GaN See AlGaN
BBPA
Broadband power amplifier
CG
Common-gate
CL
Coupled-line
CS
Common-source
CW
Contineous wave
DA
Driver amplifier
DC
Direct current
DE
Drain efficiency
DEC
Dynamic evaluation circuit
DG
Dual-gate
DPA
Distributed power amplifier
DUT
Device under test
ECM
Electronic countermeasure
EW
Electronic warfare
FCC
Federal Communications Commission
FET
Field effect transistor
GaAs
Gallium arsenide
xxiii
Acronyms
GaN
Gallium nitride
GaN10
IAF 100 nm gate length gallium nitride HEMT technology
GaN25
IAF 250 nm gate length gallium nitride HEMT technology
GND
Ground
HB
Harmonic balance
HEMT
High electron mobility transistor
HFET
Heterojunction field effect transistor
HPA
High power amplifier
IAF
Fraunhofer Institute for Applied Solid State Physics
IC
Integrated circuit
IEEE
Institute of Electrical and Electronics Engineers
IMN
Input matching network
ISMN
Interstage matching network
ISV
Individual source via
JM
Johnson’s figure of merit
LP
Load pull
LS
Large signal
MAG
Maximum available gain
MESFET
Metal semiconductor field effect transistor
MIM
Metal-insulator-metal
MMIC
Monolithic microwave integrated circuit
mmW
Millimeter wave
MN
Matching network
MOCVD
Metal organic chemical vapor deposition
MODFET
Modulation-doped field effect transistor
MSG
Maximum stable gain
MSL
Microstrip line
NDPA
Non-uniform distributed power amplifier
NGF
Number of gate fingers
OMN
Output matching network
PA
Power amplifier
xxiv
Acronyms
PAE
Power added efficiency
pHEMT
Pseudomorphic HEMT
RF
Radio frequency
RMA
Reactively-matched amplifier
Si
Silicon
SiC
Silicon carbide
SRMA
Semi-reactively-matched amplifier
SS
Small signal
SSPA
Solid state power amplifier
TGW
Total gate width
TWA
Traveling wave amplifier
TWT
Traveling wave tube
UGW
Unit gate width
UWB
Ultra wideband
xxv
Acronyms
xxvi
Symbol Convention and Constants
Symbol
Lg
tbar
Cgs , Cgd , Cds
Ri , Rs
gm , gds
τgs
Ls
S11 , S22
S12 , S21
h21
MAG
MSG
Vgs , Vds
Ig , Id
Id,DC
Pin , Pout
DE, PAE
λ
fT
fmax
ω
Q
n
B
r
ε0
µ0
εr , µr
Description
Gate length
Barrier thickness of an AlGaN/GaN heterostructure
Gate-source, gate-drain, drain-source capacitance
Intrinsic gate resistance, source resistance
Transconductance, drain-source conductance
Gate-source time constant = Ri Cgs
Source inductance
Input, output reflection coefficient
Reverse, forward transmission gain
Short-circuit current gain
Maximum available gain
Maximum stable gain
Gate-source voltage, drain-source voltage
Gate current, drain current
Quiescent drain current
RF input power, RF output power
Drain efficiency, power added efficiency
Wavelength
Transit frequency or current gain cutoff frequency
Maximum frequency of oscillation
Angular frequency or radian frequency = 2πf
Quality factor
Filter order
Ratio bandwidth
Impedance transformation ratio
Permittivity of free-space ≈ 8.854 × 10−12
Permeability of free-space = 4π × 10−7
Relative permittivity, relative permeability of the material
Unit
nm
nm
pF
Ω
mS
ns
nH
dB
dB
dB
dB
dB
V
mA
mA
dBm
%
mm
GHz
GHz
rad s=1
F m=1
H m=1
-
xxvii
Chapter 1
Introduction
Wideband1 power amplifier (PA) monolithic microwave integrated circuits (MMICs)
are key components that are employed in numerous modern commercial and military
applications such as instrumentation systems, digital radio, electronic countermeasure
(ECM) and general use components. As an example, the development of satellite communications and TV broadcasting requires amplifiers operating at frequencies from C
band to Ku band and further to Ka band. To date, systems covering a wide frequency
range require multiple narrowband power amplifiers, e.g. an amplifier for each band.
These amplifiers are connected by means of switches or triplexers. In either case, losses
are introduced by the additional circuitry and therefore such a system is not favorable.
An example of a system covering multiple bands is illustrated in Fig. 1.1. Being able
4 GHz–6 GHz
PA 1
ZG
Switch
or
triplexer
8 GHz–12 GHz
Switch
or
PA 2
triplexer
12 GHz–18 GHz
4 GHz–18 GHz
BBPA
ZG
PA 3
Figure 1.1: Illustration of the benefits of a broadband power amplifier design over a
narrowband solution.
to replace multiple amplifiers by a single broadband power amplifier (BBPA) to cover
a certain frequency range reduces costs and system complexity. The BBPA in this
example covers the frequency bands from C up to Ku band and is thus, for instance,
compatible with C, X and Ku band satellites. A breakdown of the IEEE frequency
bands is shown in Fig. 1.2. This work is settled in the frequency range from 4 GHz to
1
This term can be regarded as synonym for broadband in the context of this work.
1
Chapter 1 Introduction
L S
12
C
4
X
8
Ku
12
K
18
Ka
27
V
40
Millimeter wave
(mmW)
W
75
110
f (GHz)
Figure 1.2: IEEE frequency bands for electromagnetic frequencies for radio and radar.
40 GHz, where the main focus lies on the frequency range up to the Ku band. However,
using a fast gallium nitride (GaN) technology, broadband amplifiers that reach into the
regime of the Ka band and beyond are demonstrated as well.
When discussing power amplifiers, inevitably five terms come to mind: output power,
gain, efficiency, linearity and bandwidth. Improving power amplifiers with respect to
one or several of the above terms has been a fruitful research topic in recent years. In the
industry-driven field of mobile communications, substantial advances have been made
in the application of linearization techniques such as digital predistortion to satisfy the
requirements set by modern digital modulation schemes. Another area which drew a
lot of attention recently is the enhancement of the efficiency of amplifiers using switchmode concepts such as class-D, class-S or inverse class-F power amplifiers to reach
drain efficiencies of 70 % and beyond, [18, 62, 64]. By using GaN-based active devices,
the output power and especially power density of such amplifiers could be dramatically
increased as compared to other technologies.
1.1 Solid State Broadband Power Amplifiers
As stated above, numerous electronic systems applications require generation, processing, amplification, and emission of signals that have a continuous broadband spectrum
or modulated signals with a relatively narrow spectrum whose frequency may change
in broad ranges. The first group of applications may include ultra wideband (UWB)
systems for short distance data transmission, radar systems with UWB signals of different kinds (pulse, multi-frequency, or quasi-noise) and a number of others. The second
group includes electronic warfare (EW) systems and universal measuring and testing
equipment. Because of the increasing demand for wideband applications, focus has
been put on transistor and circuit concepts able to cope with this new challenge. In the
context of the work at hand, the term broadband is related to systems with a minimum
bandwidth of an octave.
1.1.1 The Potential of Gallium Nitride
Amplifiers with good performance over extremely wide bandwidths have been successfully realized in the past two decades in monolithic technologies. Hence, broadband PAs
are employed in a number of modern military and commercial applications. Still, high
power requirements at frequencies above the X-band are typically satisfied with designs
2
1.2 Motivation
based on vacuum tubes. Considering that tube amplifiers such as traveling wave tubes
(TWTs) require a high voltage power supply, typically require warm-up time, have significant aging related issues and are relatively expensive, the advantages that solid state
technology offers over vacuum tube technology are significant. The requirement for high
power and high frequency requires transistors based on semiconductor materials with
both large breakdown voltage and high electron velocity. The Johnson’s figure of merit
(JM)2 of GaN is about a factor of ten higher than that of gallium arsenide (GaAs) [72].
From this point of view, wide bandgap materials, like GaN and silicon carbide (SiC),
with higher JM are ideal candidates to eventually replace the vacuum tubes by solid
state transistors. The ability of GaN to form heterojunctions makes it superior compared to SiC. GaN can be used to fabricate high electron mobility transistors (HEMTs)
whereas SiC can only be used to fabricate metal semiconductor field effect transistors
(MESFETs). The advantages of the HEMT include its high carrier concentration and
its higher electron mobility due to reduced ionized impurity scattering. The combination of high carrier concentration and high electron mobility results in a high current
density and a low channel resistance, which are especially important for high frequency
operation. The best power performance for GaN transistors has been demonstrated on
SiC substrate, mainly due to its excellent thermal conductivity [20,33,73]. Furthermore,
the high breakdown voltage allows high operation voltages and thus high impedances
are obtained, which are beneficial for broadband matching. A more detailed discussion
on the GaN technology used in this work is given in Chapter 2.
1.2 Motivation
The purpose of this work is to analyze the potential of gallium nitride based monolithic
power amplifiers in the microwave domain with more than an octave bandwidth. One
question to answer is to what extent the circuit concepts used in other material systems
can be applied. Output power, gain and thus power added efficiency (PAE) have to
be traded off against bandwidth. Because a GaN device will operate at roughly five
times the bias voltage of a GaAs device, the optimum load resistance will be about five
times higher. This inevitable impacts the Bode-Fano bandwidth at the output. The
theoretical limitations for the design of broadband matching networks are examined in
Sections 3.5 and 5.4 on device and system level, respectively. For total gate widths
necessary to obtain output powers of more than 5 W, even GaN solid state devices
have impedances much lower than 50 Ω and thus the required transformation ratios for
broadband matching covering an octave or more in bandwidth are difficult to achieve.
The situation gets even more challenging when upper cutoff frequencies are targeted that
exceed fT /3 of the active device. A popular way to overcome the matching limitations
of reactively matched amplifiers is the distributed or traveling wave approach. However,
distributed amplifiers are limited in gain and output power. A very attractive way to
2
The JM gives the power-frequency limit based solely on material properties and can be used to
compare different materials for high frequency and high power applications [50].
3
Chapter 1 Introduction
enhance the gain is to reduce the feedback capacitance by using dual-gate HEMTs. In
order to be able to use dual-gate structures for amplifier design, an accurate model is
needed. Because of the presence of parasitic RF-effects such as coupling between the
fingers of the two transistors, this is a tedious task. A method to describe the extrinsic
and intrinsic parts of the dual-gate structure separated from each other is demonstrated
up to Ku band using a distributed modeling approach in Chapter 4. The interplay
between realizable quality factors and impedances on MMICs is exemplarily shown on
monolithic broadband power amplifiers with various topologies in a 250 nm and 100 nm
gate length technology with upper frequency limits of 20 GHz and 40 GHz, respectively.
The results of the designed and fabricated MMICs are presented in Chapter 5.
1.3 State of the Art Solid State Broadband Power Amplifiers
Because of the increasing demand for broadband power amplifiers for civil and military
applications and the obvious advantages of solid state power amplifiers (SSPAs) over
TWTs, great efforts have been undertaken to build compound material based semiconductor amplifiers in the past two decades. A commonly used material combination
is GaAs with AlGaAs [98]. A heterojunction which serves as the channel is formed
by incorporating a junction between the two materials with different bandgaps. Using
an extremely thin layer of one of the materials, allows the construction of transistors
with larger bandgap differences than otherwise possible, giving them higher breakdown
voltages and thus allowing higher operational voltages which ultimately leads to higher
obtainable output powers. Field effect transistors obtained by this technique are called
pseudomorphic HEMTs (pHEMTs).
A standard design approach is to directly apply well known broadband impedance
matching methods. Good results have been reported with this technique for MMICs
that utilize pHEMT technologies. At the beginning of this work, amplifier MMICs
providing 2 W to 4 W of output power have been commercially available for some time.
Fig. 1.3 gives an overview of some of the most important commercially available GaAs
broadband PA MMICs of three different global players. The x-axis represents the
frequency from 0 GHz to 50 GHz, whereas the left y-axis represents the output power
at the upper band edge from 0 W to 8 W. The center of the ellipses mark the center
frequency and output power at the x-axis and left y-axis, respectively. The horizontal
and vertical axis of the ellipses represent the bandwidth and gain, respectively. The
gain is scaled to 10 dB per division on the right y-axis. The most interesting result in
the context with this work is the TGA2501 PA MMIC from Triquint [101]. It is a 3
stage design with a bandwidth of 6 GHz to 18 GHz and an output power of 2.3 W at the
upper band edge. The high output power is achieved by a rather complex matching and
power combiner network to congregate a large total gate width (TGW). The gather up
of gate width by means of transmission line power combiners is carried to extremes in
the TGA2514 PA MMIC [102]. It is a complex 3 stage balanced amplifier design with
a bandwidth of 13 GHz to 18 GHz and an output power of 5.4 W at the upper band
4
1.3 State of the Art Solid State Broadband Power Amplifiers
8
7
[102]
5
4
TriQuint
Hittite
Macom
[101]
3
[71]
[43]
2
Gain (10 dB/div)
Pout (W)
6
[44]
1
0
0
10
20
30
40
50
Frequency (GHz)
Figure 1.3: State of the art GaAs pHEMT based broadband PA MMICs. Center of
ellipses = center frequency and output power on the x-axis and left y-axis,
respectively. Horizontal axis of ellipses = bandwidth, vertical axis = gain.
edge. This circuit has a limited bandwidth as compared to the previous one but shows a
much higher output power. It is a good example of what is technically possible in GaAs
technology for limited bandwidth, i.e. below one octave. The PA MMICs [43, 44, 71]
are distributed amplifiers which have a much higher bandwidth as compared to the
reactively-matched designs, but also have lower output powers and gains.
1.3.1 GaN Based Solid State Broadband Power Amplifiers
Since the circuits shown in Fig. 1.3 are based on a very matured technology, they represent more or less the maximum performance, that can be achieved by GaAs based
MMICs in terms of output power. Further increasing the output power by simple
scaling is not possible, because additional combiners would be necessary and therefore
additional loss would be introduced. This additional loss would eventually ruin the
power gained by the additional gate width. Another limiting factor is the low output
impedance of GaAs pHEMTs, which leads to high impedance transformation ratios for
large gate widths. Assuming the device output impedance is in the form of a parallel
RC circuit, the parallel resistor for a device operated at 6 V is below 20 Ω mm. This is
the point, where GaN comes into play. Because of its much higher power density, less
circuitry is necessary to assemble gate width to achieve a certain output power. Furthermore, GaN can be operated at higher voltages and therefore smaller transformation
ratios occur, which is beneficial for broadband matching. These benefits make GaN a
very promising candidate to push the boundaries set by other semiconductor materials.
5
Chapter 1 Introduction
At the beginning of this work, some promising results have been published in GaN
on SiC technology. As an example for high output power serves the X band amplifier
in [60]. This amplifier is a two-stage design with a measured pulsed output power
of more than 10 W over a bandwidth of 8.5 GHz to 11.5 GHz and is a much simpler
design as compared to the above-said [102], i.e. requires less power combining due to
the higher power density of GaN. A comparison of 4 GHz to 18 GHz multi-watt PA
MMICs implemented in AlGaN/GaN HEMT and GaAs pHEMT with common circuit
technology is presented in [66]. Both GaN and GaAs MMICs were designed as nonuniform distributed power amplifiers and achieved approximately 4 W over the band.
The paper nicely shows, that the circuit complexity of the GaAs circuit is much greater
than for GaN as shown by the relative transistor output peripheries of 14.4 mm and
2 mm, respectively. These results are encouraging to pursue research in this direction.
The next chapter provides an overview of the GaN based monolithic integrated circuit
(IC) technology with its performance, as it was available for the fabrication of the active
devices and circuits within the scope of this work.
6
Chapter 2
Gallium Nitride Based Monolithic IC
Technology
In the early 1990s, GaN was deemed an excellent, next generation, semiconductor material for high power and high frequency transistors based on the material parameters
of bandgap, electron mobility, and saturated electron velocity. The lack of bulk GaN
source material led to the need for GaN growth on lattice mismatched substrates such as
silicon (Si), SiC and sapphire [86]. Wide-bandgap semiconductor technology for highpower microwave devices has matured rapidly over the last several years as evidenced
by the fact that AlGaN/GaN HEMTs have been available as commercial-off-the-shelf
(COTS) devices since 2005 [72,80]. In this chapter, the principles of GaN based heterojunction field effect transistors (HFETs) will be given with focus on properties relevant
for the design of monolithic broadband high power amplifiers (HPAs). Different AlGaN/GaN heterostructures are the basis for three radio frequency (RF) GaN process
technologies at the Fraunhofer Institute for Applied Solid State Physics (IAF) using a
gate length of 500 nm, 250 nm and 100 nm with full MMIC capability [11,41,113]. They
were developed in strong collaboration with European industry partners and played a
major role to develop a European commercially available GaN technology [132]. The
technologies relevant for the present work are the 250 nm and 100 nm process, named
“GaN25” and “GaN10”, respectively. The latter was achieved by scaling the 250 nm
process regarding gate length to result in a higher cutoff frequency fT .
Survey of GaN Research Activities in Europe
The development of GaN for RF electronics in Europe was greatly promoted by a number of European research programs such as KORRIGAN, HYPHEN, UltraGaN and
GREAT2 [82]. Another program worth mentioning is MANGA, realized by the European Defence Agency (EDA). The main objective of this five nation joint project
is to sustain the industrial development of semi-insulating SiC substrates and prove
the industrial capability of Europe to support GaN HEMT and MMIC foundries with
state-of-the-art GaN HEMT epitaxial wafers on semi-insulating SiC substrates [70]. A
systematic comparison of semi-insulating SiC substrates from Cree and SiCrystal on
7
Chapter 2 Gallium Nitride Based Monolithic IC Technology
substrate, GaN epiwafer, and electronic device level is reported within the the project
EuSiC [114]. EuSiC is aiming at establishing an independent, purely European sustainable supply chain for GaN based space technologies.
2.1 Semiconductor Technology for AlGaN/GaN Transistors
Gate
2.0 µm
Drain
3 nm GaN cap
Ohm
22 nm AlGaN barrier
Ohm
2DEG
1.9 µm GaN buffer
AIN nucleation
Conduction band (eV)
Source 0.7 µm
GaN
channel & buffer
1020
1.5
1019
1.0
1018
0.5
1017
EF
0.0
-0.5
100 µm SI-SiC substrate
(a) Basic 250 nm AlGaN/GaN device
layer structure on semi-insulating SiC.
GaN
cap
2.5
Al0.22 Ga0.78 N
2.0
barrier
0
10
20
30
40
Depth (nm)
50
Electron density (eV)
A GaN HFET consists of a thin GaN cap with an AlGaN barrier on a GaN buffer. The
schematic cross section of a device with typical layer thicknesses for a typical 250 nm
process is shown in Fig. 2.1 (figure is not drawn to scale). The thin AIN nucleation
1016
60
(b) Conduction band diagram and electron concentration.
Figure 2.1: Schematic cross section of a conventional 250 nm AlGaN/GaN heterostructure and simulated conduction band diagram and electron concentration.
layer lowers the lattice mismatch with subsequently grown III-nitride films relative
to that with SiC [29]. A 1.9 µm thick buffer layer is necessary to reduce the defect
and dislocation density and hence realize epitaxial layers with insulating properties.
The ohmic contact between the metal and the two dimensional electron gas (2DEG)
is established by rapid thermal annealing [54, 55]. The obtained contact and sheet
resistances are below 0.3 Ω mm and around 550 Ω/2, respectively [110]. The impact of
GaN cap thickness on electrical and device properties in AlGaN/GaN HEMT structures
is investigated in [115]. The conduction band diagram and electron concentration for a
barrier with 22 % aluminum content is shown in Fig. 2.1(b).
2.1.1 The Conventional GaN HEMT
A two dimensional electron gas in AlGaN/GaN based heterostructures suitable for
HEMTs, is induced by strong polarization gradients [3]. The electrical properties of
the 2DEG are mainly influenced by the AlGaN barrier thickness and Al content. The
8
2.2 Degradation Mechanisms in GaN Heterostructures
sheet carrier density increases approximately linearly with the aluminum content. The
influence of the barrier thickness on the sheet carrier density however is nonlinear.
2DEGs with sheet carrier concentrations up to 2 × 1013 cm=2 can be achieved close to
the interface, well in excess of those observed in other III-V material systems. The
physical properties influencing the sheet carrier concentration and the confinement of
the 2DEGs, such as polarity, alloy composition, strain, thickness, and doping of the
AlGaN barrier, have been thoroughly examined [3, 4].
The HEMT is typically of depletion-mode, or normally-on type, i.e. the channel is
conductive with zero gate bias and a negative gate-source Vgs voltage must be applied to
turn the transistor off, as shown in Fig. 2.2. Although not relevant for the IAF process,
Id
Id
Vgs = 0 V
Vgs
0
0
Vds
0
Vgs
Figure 2.2: Output and transfer characteristics of an n-channel depletion-mode FET.
for the sake of completeness it is worth mentioning, that in addition to polarization
induced carriers, the forming of the channel can be supported by doping of the widebandgap (high-Eg ) See AlGaN (AlGaN/GaN) material. Thereby carriers diffuse to
the undoped narrow-bandgap layer. This technique is called modulation doping and
therefore the name modulation-doped field effect transistor (MODFET) is also used for
the discussed HFET in literature. As a result of this modulation doping, the channel
carriers in the undoped heterointerface are spatially separated from the doped region
and have high mobilities because there is no impurity scattering [95].
2.2 Degradation Mechanisms in GaN Heterostructures
AlGaN/GaN based microelectronic devices offer a variety of advantages like high breakdown voltage and high saturation velocity. However, AlGaN/GaN HEMTs are still
facing reliability problems [26]. Reliability and degradation mechanism of 250 nm AlGaN/GaN HEMTs under RF stress conditions are reported in [28]. Trade-offs exist
between performance and reliability of AlGaN/GaN transistors. In [109] it is shown
that changes in epitaxial growth, transistor design and process may lead to an improvement in performance but are, at the same time, accompanied by a degradation of device
reliability. By using a field plate electrode (also called shield“), the breakdown voltage
”
of a GaN transistor can be dramatically increased. However, the presence of an additional electrode, besides the increase of breakdown voltage and output power density,
9
Chapter 2 Gallium Nitride Based Monolithic IC Technology
causes other changes in the transistor characteristics as well. Most important, there are
significant changes in the cutoff frequencies fT and fmax and the parasitic capacitances
of the active structure. The dependency of various transistor parameters, such as the
parasitic capacitances, on the length of the field plate is investigated in [61, 79, 121].
2.3 250 nm MMIC Technology
The epitaxial structure used for the fabrication of the active devices in this work was
grown by metal organic chemical vapor deposition (MOCVD) on 3-inch semi-insulating
SiC substrates [2, 74, 111]. Fig. 2.3 shows the schematic cross section of the complete
IAF GaN25 process. Again, the figure is not drawn to scale. It is a full MMIC process
Source connected
field plate
Airbridge
MIM
Passivation
METG
MET1
MET1
OHM
SiN
MET1
OHM
NiCr
SI-SiC substrate
SI-SiC substrate
Au
Backside metal
GATE
SiN
Active layer
Resisitor
Au
Via hole
Figure 2.3: Schematic cross section of the full IAF AlGaN/GaN HEMT MMIC process.
including, besides the active devices, resistors, metal-insulator-metal (MIM) capacitors
and spiral inductors. The silicon nitride (SiN) forming the insulation of the MIM
capacitors has a thickness of 250 nm. The metal layer names METG, MET1, OHM,
and GATE stand for galvanic metal, metal1 , ohmic metal, and gate metal, respectively.
As mentioned in Section 2.2, the source connected field plate is an effective way for
increasing the breakdown voltage of the transistor. It is implemented using the metal
layer MET1 as well. Since the applied transmission line technology is microstrip line
(MSL), thinning of the wafer to 100 µm and backside processing including front-toback substrate via holes are involved. The active devices are completely passivated. A
description of the process technology with focus on general technology parameters and
the corresponding design rules can be found in the IAF GaN25 design manual [49]. The
active layer is isolated by ion implantation. It consists of a GaN cap of approximately
3 nm, an AlGaN barrier of 5 nm to 25 nm and a GaN buffer of 1 µm to 2 µm, as shown
in detail in Fig. 2.1(a). The 250 nm gates are defined by electron beam lithography.
10
2.4 100 nm MMIC Technology
In order to support the design of MMICs in the GaN25 process, a design kit including
electrical models for the elements as well as the corresponding layouts is available for
the circuit simulator Advanced Design System (ADS). A description of the design kit
for active and passive microstrip components can be found in [45] and [46], respectively.
2.3.1 250 nm GaN Technology Performance
The typical operational drain-source voltage Vds of the GaN25 process is 30 V. The gatedrain breakdown voltage is higher than 120 V, the HEMTs yield a maximum extrinsic
DC transconductance gm of 300 mS mm=1 at Vds = 30 V and a maximum drain current
of > 1.1 A mm=1 . The extrinsic transit frequency fT and the maximum frequency of
oscillation fmax for small gate devices are 28 GHz and 40 GHz, respectively.
2.4 100 nm MMIC Technology
The motivation for the 100 nm AlGaN/GaN technology is to develop a process, which is
significantly faster than the 250 nm process, i.e. has a higher cutoff or transit frequency
fT . The intrinsic transit frequency is given by
fT ≈
1
gm
≈
2πτt
2π (Cgs + Cgd )
(2.1)
and will be discussed in more detail in Section 3.1.3. Power amplifier MMICs based
on high power AlGaN/GaN/AlGaN double heterojunction structures with gate lengths
of 100 nm and 150 nm have been demonstrated in [68, 69]. The reported devices reach
extrinsic transit frequencies of fT ≈ 90 GHz. In the equation above, Cgs and Cgd are
the gate-source and gate-drain capacitors, respectively and τt is the transit time of the
electrons from source to drain. Therefore, fT gives an idea of the intrinsic delay of
the transistor. By assuming that the carriers are moving at the saturation velocity, the
transit time is simply τt = L/υs , hence the transit frequency is inversely proportional
to the channel length L. For the GaN25 process, Cgs and Cgd are about 1.5 pF mm=1
and 0.1 pF mm=1 , respectively. By assuming an intrinsic gm of 400 mS, a reduction of
(Cgs + Cgd ) to approximately 0.6 pF would be necessary in order to achieve an intrinsic fT > 100 GHz. The increase in intrinsic fT by proper scaling the GaN25 process
regarding gate length is described in the following section.
2.4.1 Scaling Properties of HEMTs Regarding Gate Length
From (2.1) it is obvious, that fT can be increased by decreasing the channel length and
thereby decreasing the transit time τt , which corresponds to a decrease in Cgs . However,
as the gate length is reduced, the horizontal electric field increases and becomes comparable to the vertical field, which confines the carriers on the 2DEG channel. This two
11
Chapter 2 Gallium Nitride Based Monolithic IC Technology
dimensional distribution of the electric field under the gate results in short-channel effects which degrade the device performance by shifting the threshold voltage, increasing
the output conductance, reducing the transconductance and resulting in poor pinch-off
performance [35]. These degrading effects can be significantly reduced by reducing the
barrier thickness tbar by the same factor as the gate length, to keep the aspect ratio
Lg /tbar constant (theoretical scaling rule) - which on the other hand increases Cgs .
The barrier thickness is also the most important scaling parameter for the transconductance. By decreasing the barrier thickness, gm is increased [42]. This leads to an
increase in fT as can be seen in (2.1). In simplified terms this means, that the effective
increase in fT is achieved by simultaneously increasing gm while keeping Cgs constant.
In the situation at hand however, the scaling is not exactly done according the theoretical rules, because the required barrier thickness would lead to an unacceptably
high sheet resistance, i.e. the barrier thickness is not decreased by the same amount
as the effective gate length, which leads to a decrease in Cgs . A small signal parameter extraction on a 4 × 45 µm GaN10 device at Vds = 10 V gives a Cgs = 0.55 pF mm=1 ,
Cgd = 0.13 pF mm=1 , and gm = 450 mS, which results in an intrinsic fT of 105 GHz. By
scaling the transconductance and the gate length, the high parasitic capacitances of the
gate metalization structure become a limiting factor at some point. Hence, efforts to
minimize those parasitic elements by means of scaling and process optimization have
to be made.
A major hurdle to achieve good performance is the degradation of the intrinsic fT
caused by the degradation of the transconductance, mainly due to the parasitic source
resistance Rs [21, 95]:
gm,int
gm,ext ≈
,
(2.2)
1 + Rs gm,int
In order to achieve a high extrinsic transconductance gm,ext , the loss caused by the
source resistance has to be minimized. The source resistance is the sum of the sheet
resistance Rsh and the contact resistance Rcon , which in itself is the sum of the ohmic
contact resistances:
Rs = Rsh + Rcon .
(2.3)
As a consequence of this, efforts must be made to minimize Rs , which is achieved
by minimizing the contact and sheet resistances. Both parameters are influenced by
the quality of the hetero epitaxial layers and the barrier properties [40]. To date, the
contact resistance is comparable to that of the GaN25 process, i.e. somewhere below
0.3 Ω mm. The sheet resistance has been successfully reduced to around 450 Ω/2. For
a gate-source electrode pitch of 0.7 µm, this gives a source resistance of approximately
0.6 Ω mm. By applying (2.2), the intrinsic gm from above is reduced to 350 mS mm=1
to result in an extrinsic fT of about 82 GHz. These numbers illustrate the degradation
of the transit frequency caused by the degradation of the transconductance due to the
parasitic source resistance Rs .
12
2.4 100 nm MMIC Technology
2.4.2 100 nm GaN Technology Performance
The schematic cross section of the full IAF GaN10 process is identical to the GaN25
cross section in Fig. 2.3, except there is no field plate. Due to the scaling discussed
above, the barrier thickness is reduced to 9 nm. As for the GaN25 process, an ADS
design kit including electrical models for the elements as well as the corresponding layouts is available for the GaN10 process. In the description of the design kit a more
detailed description of the process technology is included [47, 48]. As a consequence of
the reduced gate length and the thereby diminished gate-drain breakdown voltage, the
maximum operational voltage of the GaN10 process is reduced to 15 V. The HEMTs
yield a maximum extrinsic DC transconductance of 350 mS mm=1 at Vds = 10 V and a
maximum drain current of > 1.3 A mm=1 . The higher drain current as compared to the
GaN25 process is achieved by the decrease in the sheet resistance. The extracted extrinsic current gain cutoff frequency fT is around 78 GHz. This is somewhat lower than
the estimation above due to additional parasitic effects. For small gate devices, fmax
can get as high as 200 GHz at Vds = 7 V. In order to support the design of transmission
lines at millimeter wave frequencies, the wafers are thinned to 75 µm. A detailed report on the development of the 100 nm gate length high transconductance HEMT can
be found in [40]. The photograph of a multifinger HEMT and cross section scanning
electron micrographs of the gate area are shown in Fig. 2.4. The represented device is
from an early development stage and has a T-gate with a length of 150 nm.
50 µm
2 µm
D
S
S
600 nm
G
S
G
Figure 2.4: Photograph of a fully processed 4 × 100 µm GaN HEMT and cross section
scanning electron micrographs of the gate area.
Conclusion on the Available GaN Technologies
Two different AlGaN/GaN technologies were available for the fabrication of the active
devices and circuits within the scope of this work. The GaN25 process with an extrinsic
fT of about 28 GHz, suitable for circuit design up to the Ku band and the GaN10
process with an extrinsic fT of about 78 GHz, suitable for circuit design up to the Ka
band and beyond. The former technology is typically operated at Vds = 30 V, whereas
the latter uses a typically biased between Vds = 10 V to 15 V. The maximum current
13
Chapter 2 Gallium Nitride Based Monolithic IC Technology
densities of the 250 nm and 100 nm process are 1 A mm=1 and 1.3 A mm=1 , respectively.
Designed and manufactured power HEMT structures employing both of the technologies
described above, are discussed regarding their key characteristics and suitability for
broadband power amplifier design in the next chapter.
14
Chapter 3
Power HEMT Structures for Broadband
Applications
A number of reasons make GaN HEMTs superior for the use as active devices in broadband amplifiers. These reasons have been discussed in Chapters 1 and 2. Since the
performance of the active device defines some of the core attributes of an amplifier such
as output power, gain, and efficiency, a separate chapter is dedicated to power HEMT
structures for broadband applications. Designed and manufactured power HEMTs are
discussed regarding their key characteristics important for the design of broadband
power amplifier MMICs. Various kinds of common-source and dual-gate structures are
investigated regarding their suitability for broadband power amplifier design. The terminology used in the describtion of HEMTs is shown in Fig. 3.1 on a simplified layout
of an MSL eight-finger HEMT. Active channels are formed along the gate fingers emDrain connection
Gate finger Drain bus
Source
Via
GND
Gate width (GW)
Airbridge Gate bus
Drain
Gate connection
Figure 3.1: Simplified layout of an eight-finger HEMT.
bedded between drain and source contacts. The width of a single gate finger is referred
to as unit gate width (UGW) of the transistor. All gate fingers are collected by the
gate bus. The drain bus connects the drains, whereas the sources are connected by
airbridges. The source is ground connected symmetrically by vias to the ground metalization. The HEMT is connected to its periphery by the gate and drain connection.
The TGW of a transistor is defined as number of gate fingers (NGF) times UGW, i.e.
TGW = NGF×UGW, and can therefore be controlled by scaling the gate width and/or
15
Chapter 3 Power HEMT Structures for Broadband Applications
number of fingers. The TGW is directly proportional to the drain current and thus defines the obtainable output power of the device. On the other hand, the TGW impacts
the gain as well, because it defines the transition from the unstable to the stable region
of operation, as will be explained in Section 3.1.2. The unit gate width and number of
fingers have thus to be chosen carefully in order to achieve the demanded output power
without sacrificing gain to an unacceptable extent. In order to examine the interplay
between obtainable output power and gain, effort has been put into the modeling of
GaN HEMTs, as discussed in more detail in Chapter 4 on the basis of dual-gate devices. Transistor layouts other than the one discussed above are shown in Fig. 3.2. All
Drain bus Source
Individual source via (ISV)
Via
Gate bus
Airbridge
(a) 2-via HEMT.
(b) 4-via HEMT.
(c) ISV HEMT.
Figure 3.2: Common-source HEMTs in various via configurations.
of these are used for the design of monolithic amplifiers in this work. An interesting
structure is the individual source via (ISV) HEMT illustrated in Fig. 3.2(c). Instead
of using an airbridge to connect the sources of the individual unit cells, each source
has its own via, therefore the name individual source via. This approach decreases the
source inductance of the device and thereby increases the gain. The influence of the
source inductance on the gain parameters as well as on the stability is shown in [75].
On the other hand, due to the minimum required width of the vias for producibility, the
structure becomes wider as compared to the 2-via or 4-via device and therefore is more
critical at higher frequencies due to distributed effects on the gate and drain buses.
ISV HEMTs find use in the high power amplifier MMIC discussed in Section 5.9.4. A
comparison of extracted small-signal equivalent circuit element values of 2-via and ISV
devices is shown in Table 3.1.
The efficiency of the amplifiers in this work is of secondary concern. However, since
power dissipation in transistors lead to thermal compression, the efficiency indirectly
impacts the output power. As stated in Chapter 2, two technologies were used: the
250 nm gate length GaN25 and the 100 nm gate length GaN10 process. In the following,
the data is referred to the GaN25 technology, unless stated otherwise.
3.1 Figures of Merit of Broadband Active Devices
In order to classify active devices for certain applications in RF and microwave engineering, specific figures of merit are used. This section revisits the terms that are used
throughout this work.
16
3.1 Figures of Merit of Broadband Active Devices
3.1.1 Stability
In literature, two types of stability are defined: unconditional stability and conditional
stability. A network is unconditional stable if |Γin | < 1 and |Γout | < 1 for all passive
source and load impedances. A network is conditional stable if |Γin | < 1 and |Γout | < 1
only for a certain range of passive source and load impedances. This case is also referred
to as potentially unstable. The range of values for ΓS and ΓL where the amplifier will
be stable can be facilitated by plotting the input and output stability circles, [81]. A
simpler way to determine unconditional stability involves the stability factor K, defined
as
1 − |S11 |2 − |S22 |2 + |∆|2
K=
,
(3.1)
2 |S12 S21 |
where ∆ is the determinant of the scattering matrix S, defined as
∆ = S11 S22 − S12 S21 .
(3.2)
A device is unconditionally stable if the conditions K > 1 and |∆| < 1 are simultaneously satisfied. This condition is called the Rollet’s condition. A criterion that combines
the two separate parameters into a single parameter, µ, has been proposed by [31]:
µ=
1 − |S11 |2
∗ | + |S S | > 1.
|S22 − ∆S11
12 21
(3.3)
If µ > 1, the device is unconditionally stable. Larger values of µ imply greater stability.
3.1.2 Two-Port Power Gain Definitions
In RF and microwave engineering, a vast number of different gain definitions exist.
This section discusses the terms that are used in this work. A commonly used concept
to describe the gain of an active device in terms of small signal (SS) parameters, is
the concept of maximum available gain (MAG) and maximum stable gain (MSG). If a
transistor is unconditionally stable, so that K > 1, the MAG can be defined as follows:
MAG = Gmag =
p
|S21 | K − K2 − 1 .
|S12 |
(3.4)
The maximum available gain is also sometimes referred to as the maximum transducer
power gain or matched gain. If the device is only conditionally stable, i.e. K < 1, a
useful figure of merit is the MSG, defined as the MAG with K = 1:
MSG = Gmsg =
|S21 |
.
|S12 |
(3.5)
17
Chapter 3 Power HEMT Structures for Broadband Applications
Definition of the K-Point
A typical GaN device is conditional stable up to a certain frequency and then becomes
unconditional stable, i.e. the device’s gain transitions from MSG into MAG, where it
drops at a rate of 10 dB/dec and 20 dB/dec, respectively (obvious when plotted over a
logarithmic frequency scale as in Fig. 3.6). At the frequency, where the device reaches
unconditional stability, the Rollet stability factor becomes unity (K= 1). The “Kpoint” is dependent on the total gate width of the device. As an example, Fig. 3.3 shows
the simulated MSG/MAG and stability factor curves of an 8 × 75 µm GaN25 device
with a K-point at 17 GHz. In order to achieve sufficient gain, amplifiers are typically
6
Gmsg , Gmag
K
25
5
4
20
K-point
15
3
10
2
5
1
MSG MAG
0
0
10
20
30
Frequency (GHz)
Stability factor K
MSG, MAG (dB)
30
0
40
50
Figure 3.3: Definition of the K-point on the example of an 8 × 75 µm GaN25 device.
designed such that the active devices are operated at frequencies below the K-point.
However, to obtain the targeted high output power of e.g. > 10 W in this work, it is
inevitable to choose large transistor peripheries for the power amplifier stage, resulting
in an operation above the K-point. The gain penalty can be compensated by using a
multistage amplifier design. The simulated dependence of the K-point on TGW of an
eight and a six-finger device in GaN25 technology and a four-finger device in GaN10 is
shown in Fig. 3.4, where scalable 8-term small signal models have been used. In the
model, distributed effects on the gate and drain buses of the transistors are neglected.
As a result, the K-point is solely determined by the finger gate width of a transistor,
i.e. the NGF does not affect the K-point. This explains the higher K-point of the
8-finger device as compared to the 6-finger device for the same TGW in Fig. 3.4. To
minimize parasitic effects caused by the bus structure, a maximum of eight fingers are
used up to a frequency of 20 GHz and a maximum of four fingers up to a frequency of
40 GHz.
In order to achieve sufficient gain, amplifiers are typically designed such that the
active devices are operated below the K-point. Thus, the gate width is limited by the
18
3.1 Figures of Merit of Broadband Active Devices
80
8 finger GaN25
6 finger GaN25
4 finger GaN10
K-point (GHz)
70
60
50
40
30
20
10
0
0
0.1
0.2
0.3
0.4 0.5 0.6
TGW (mm)
0.7
0.8
0.9
1
Figure 3.4: Simulation of the dependence of the K-point on TGW by means of scalable
8-term small signal HEMT models.
upper band edge of the design frequency range. The dashed lines in Fig. 3.4 indicate
the maximum TGWs in order to fulfill K < 1 at 20 GHz for the GaN25 process and at
40 GHz for the GaN10 process. The TGW yields 0.5 mm and 0.37 mm for an eight and
six-finger device, respectively in the GaN25 process and 0.37 mm for a four-finger device
in the GaN10 process. A typical transistor size to be employed in reactively matched
power amplifiers up to Ku band in GaN25 technology is 8 × 75 µm and 4 × 60 µm for
distributed amplifiers up to Ka band in GaN10 technology.
3.1.3 Transit Frequency and Maximum Frequency of Oscillation
The transit frequency fT is an important figure of merit to assess intrinsic frequency
response of transistors. Defined as the short-circuit current gain cutoff frequency, it is
the frequency, at which the short-circuit current gain β becomes unity:
iout β = |h21 | = = 1.
(3.6)
iin vout =0
The corresponding simplified equivalent circuit of an intrinsic HEMT is shown in
Fig. 3.5. The output is shorted to satisfy the vout = 0 condition for h21 . Applying
Kirchoff’s point rule at the input and output of the circuit yields
iin = vgs jω (Cgs + Cgd )
(3.7)
iout = vgs (gm − jωCgd ) .
(3.8)
and
19
Chapter 3 Power HEMT Structures for Broadband Applications
iin
vgs
Cgd
Cgs
iout
vgs gm
Figure 3.5: Simplified shorted equivalent circuit of an intrinsic HEMT for the determination of the transit frequency fT .
Dividing (3.8) by (3.7) gives
h21
gm − jωCgd
iout =
=
.
iin vout =0 jω (Cgs + Cgd )
The short-circuit current gain is found by taking the magnitude of (3.9):
q
gm 2 + (ωCgd )2
β = |h21 | =
.
ω (Cgs + Cgd )
(3.9)
(3.10)
Since for the frequencies of interest ωCgd gm ,
β≈
gm
.
ω (Cgs + Cgd )
(3.11)
fT ≈
gm
,
2π (Cgs + Cgd )
(3.12)
β becomes unity at
which indicates, that the short-circuit current gain is inversely proportional to the
frequency and can be expressed as
β≈
fT
.
f
(3.13)
fT is a useful and reasonably unambiguous figure of merit that is convenient to measure
and relates directly to the primary equivalent circuit elements in Fig. 3.5 that determine
the device RF gain. Because of the low-pass behavior of an active device, amplifier
design close to the transit frequency is challenging, e.g. for frequencies above fT /3.
The targeted upper frequencies of the broadband amplifiers in this work lie around
2/3fT , which makes the designs very delicate due to the lack of gain margin. The
GaN25 process has an intrinsic fT ≈ 30 GHz and an extrinsic fT ≈ 28 GHz. Since
fT is defined via the current gain h21 for the case of an input current generator with
infinite output conductance, it does not account of device input resistance. However, a
device chosen for power amplification should have a low input resistance and high power
gain. A figure of merit that addresses this requirement is the maximum frequency of
20
3.1 Figures of Merit of Broadband Active Devices
oscillation fmax , defined as the frequency, at which the maximum available gain MAG
becomes unity, i.e. the frequency, where the power gain becomes unity. The expression
for fmax can be determined for the network of Fig. 3.16 and is given in (3.14) which
illustrates the relative significance of the various parasitic components [108].
fT
fmax ≈ p
,
2 (Ri + Rs + Rg ) gds + 2πfT Rg Cgd
(3.14)
where Cgd is the gate-drain capacitance, gds is the output conductance, and Ri , Rs ,
and Rg are the input, source, and gate resistances, respectively. The optimization of
fmax relies closely on the maximization of fT as well as on the reduction of the parasitic
elements. As discussed in Section 2.4, the reduction of gate length is an important
factor to improve fT and therefore fmax . Fig. 3.6 shows the simulated fT and fmax on a
double-logarithmic scale. A difficulty with fmax is that there is no universally adopted
approach to its determination and it is usually obtained by extrapolation of measured
data.
h21 , MSG, MAG (dB)
50
h21
Gmsg , Gmag
40
fmax
30
fT
20
10
0
0.1
0.3
1
3
10
Frequency (GHz)
30
80
Figure 3.6: Simulated fT and fmax of an 8 × 75 µm HEMT using a small signal model.
3.1.4 Drain Efficiency and Power Added Efficiency
In microwave engineering, amplifier or device efficiency is calculated in several ways.
The two commonly used definitions shall be discussed here. In a FET device, DC power
is supplied to the drain. Drain efficiency (DE) is the ratio of RF output power Pout,RF
to DC input power PDC . It is usually expressed as a percentage:
DE = 100%
Pout,RF
PDC
(3.15)
Drain efficiency is a measure of how much DC power is converted to RF power for
a single device. PAE is similar to drain efficiency, but takes into account the RF
21
Chapter 3 Power HEMT Structures for Broadband Applications
power that is added to the device at the input. Again, PAE is usually expressed as a
percentage:
Pout,RF − Pin,RF
Pin,RF
PAE = 100%
= DE − 100%
(3.16)
PDC
PDC
PAE is applied to amplifiers as a figure of merit, as well as to devices. If the gain of an
amplifier is sufficiently high, PAE will approximate DE.
3.2 DC Performance
Under DC consideration, a FET can be regarded as a voltage controlled current source
with an internal resistance Rds , according Fig. 3.7. By presenting a load with the
Iin
Iout
Vgs Rgs
Vgs gm
Rds
Figure 3.7: DC equivalent circuit of a HEMT.
same value as the internal resistance Rds , power match is achieved and therefore the
output power of the active device is maximized. The DC output power is the maximum
obtainable power. When the transistor is operated under RF conditions, the output
power will inevitably degrade with increasing frequency due to parasitic effects such as
trapping, which causes DC-to-RF dispersion. Trapping has rather long time constants
associated with it, which lead to anomalous dispersion with onset at lower frequencies
already. Pulsed I-V measurements, which visualize the dispersion can be found in [58], a
modeling concept for the low-frequency dispersion aspect of large signal (LS) modeling
of microwave III-V field-effect transistors is presented in [105]. In order to estimate the
obtainable output power of an active device, studying its DC performance is essential.
Fig. 3.8 shows the normalized current-voltage (I-V) characteristics of a 2 × 50 µm device.
The small transistor size is chosen in order to minimize thermal effects. The DC output
characteristics were measured up to a drain voltage of Vds = 30 V, with a gate-source
voltage =2 V < Vgs < 2 V. A saturation current of 1130 mA mm=1 is obtained. In order
not to exceed a power density of 12 W mm=1 , the measured voltage range is reduced
towards higher drain currents, to protect the device from damage, i.e. avoid P > Pmax .
The earlier introduced transconductance, denoted by gm in Fig. 3.7, is defined as the
change in the drain current divided by the change in the gate-source voltage:
gm
22
∂Id =
∂Vgs Vds =const.
(3.17)
3.2 DC Performance
1200
Pmax
Id (mA/mm)
1000
800
Vgs = −2 V . . . 2 V
600
400
200
0
0
5
10
15
Vds (V)
20
25
30
Figure 3.8: Measured normalized DC I-V characteristics for a 2 × 50 µm HEMT. Vgs is
varied from =2 V to 2 V, the saturation current is 1130 mA mm=1 .
Fig. 3.9 shows the measured DC transconductance gm and corresponding drain current Id for the same device sample as above for two different drain-source voltages. The
transconductance shows an asymmetric behavior, i.e. a steep rise near turn-on independent on Vds and a smooth decay towards gm = 0 mS. A maximum gm of 360 mS mm=1
400
gm (mS/mm)
1250
at Vds = 7 V
at Vds = 30 V
1000
300
750
200
500
100
250
Id (mA/mm)
500
0
0
-3
-2
-1
0
Vgs (V)
1
2
3
Figure 3.9: Measured normalized DC transconductance gm and drain current Id for a
2 × 50 µm HEMT at Vds = 7 V and Vds = 30 V.
and 320 mS mm=1 was measured at Vds = 7 V and Vds = 30 V, respectively with a correlating drain current of Id ≈ 120 mA mm=1 . The complete channel pinch-off lies at
around =2.4 V and is rather independent of the drain-source voltage.
23
Chapter 3 Power HEMT Structures for Broadband Applications
3.2.1 Power Density
The obtainable power density of a GaN HEMT can be approximated by drawing a
reasonable loadline in the DC output characteristics in Fig. 3.8, as shown in Fig. 3.10.
The maximum current Imax is chosen to be 1000 mA mm=1 . By considering Fig. 3.8,
Id (mA)
Imax
Q-point class-A
Imax /2
Loadline
0
0
Vknee
Vmax
Vds (V)
Figure 3.10: DC output characteristics with loadline and quiescent point Q for class-A
operation of a HEMT.
this is a reasonable value to achieve an acceptable knee voltage Vknee of 6 V. The knee
voltage is the voltage drop over the open channel resistor Rds,on of the FET. It is defined as the voltage of the I-V curves transition from linear“ to saturation“. Since
”
”
Vknee ∝ Imax /Rds,on , the knee voltage is independent of device size. By exceeding
1000 mA mm=1 for Imax , Vknee increases disproportionately and thus results in an unacceptable drain efficiency of the transistor. The maximum drain-source voltage Vmax is
60 V. This value guarantees a safe operation below the breakdown voltage of the device.
In class-A operation, the maximum output power of a transistor can be calculated as
follows:
Pout,max =
Vmax − Vknee Imax
(V
− Vknee ) Imax
√
√ = max
,
8
2 2
2 2
(3.18)
√
where 2 are the crest factors for a pure sinusoid. For the values above, a power
density of 6.75 W mm=1 is obtained. This is the theoretical maximum obtainable power
density for a sinusoidal excitation. For a rectangular excitation, the power density
would be doubled due to the drop out of the crest factors in the denominator of (3.18).
However, a practicable FET would break by the massive overdrive at the gate caused by
rectangular excitation and therefore this power density cannot be reached. A detailed
discussion on amplifier operation classes can be found in literature, e.g. [24].
24
3.3 RF Performance
3.3 RF Performance
The optimum load impedance with respect to power of a HEMT depends on the frequency, the operation class determined by Vgs and Vds , and the input power level.
According the DC output characteristics in Fig. 3.10, the optimum load resistance for
a class-A amplifier results in
RL,opt =
Vmax − Vknee
.
Imax
(3.19)
The method of determining the optimum load resistance of an active device by considering the loadline is sometimes also referred to as “Cripps method”, based on [23].
The simplified large signal output circuit of a GaN HEMT is obtained by extending
the DC equivalent circuit in Fig. 3.7 by an effective drain-source capacitance Cds,eff , as
shown in Fig. 3.11. Together with Rds , Cds,eff forms the frequency dependent output
ΓL,opt
Vgs gm
Rds
Cds,eff
Figure 3.11: Simplified RF equivalent output circuit of a HEMT.
admittance of the transistor or generator admittance
Yout,FET = Ygen =
1
+ jωCds,eff ,
Rds
(3.20)
or expressed as output and generator impedance
Zout,FET = Zgen =
Rds
1
=
.
Yout,FET
1 + jωRds Cds,eff
(3.21)
The effective drain-source capacitance approximately has a value of
Cds,eff ≈ Cds + Cgd ≈ 0.4 pF mm−1
(3.22)
for a typical GaN25 HEMT as considered here. The frequency dependence of the generator impedance Zgen is illustrated in Fig. 3.12 for an 8 × 125 µm device. Cds,eff causes
the generator reflection coefficient Γgen to travel along the red trajectory with increasing frequency. The maximum output power of the HEMT is obtained by compensating
the effective drain-source capacitance Cds,eff and then presenting the optimum load resistance to the internal resistance Rds , i.e. presenting the complex conjugate of the
generator reflection coefficient at the output terminal of the transistor
ΓL,opt = Γ∗gen .
(3.23)
25
Chapter 3 Power HEMT Structures for Broadband Applications
1
0.5
2
0.2
0
5
0.2
0.5
1
2
5
∞
f = 0 Hz
Γgen
f↑
-0.2
0.4 pF
62 Ω
-5
f = 20 GHz
-2
-0.5
-1
Figure 3.12: Frequency trajectory of the generator reflection coefficient Γgen of a 1 mm
HEMT from DC to 20 GHz.
3.3.1 Load Pull Device Characterization
The standard procedure to determine ΓL,opt of an active device is load pull (LP). LP
involves varying the load impedance presented to a device under test (DUT) and measure performance parameters such as output power, gain, and PAE as a function of
load impedance presented to the DUT. In their most basic forms, traditional load pull
systems comprise of a signal source used to generate a test signal, an output tuner to
vary the load impedance seen by the DUT, and a power meter to measure the resulting
power. As a result, iso-contours of, e.g., output power can be plotted in the Smith
chart, as shown in Fig. 3.13 in blue. Caused by Cds,eff , the optimum load ΓL,opt travels
along the red trajectory with increasing frequency. A more profound discussion on the
determination of optimum RF operating conditions of GaN HEMTs is given in [58].
For the characterization of transistors for power applications, the LP setup is mainly
used to match the DUT either for maximum PAE or maximum Pout . The maximum
power density obtained by a fundamental load pull measurement of an 8 × 125 µm device
with a source connected 0.8 µm shield at a frequency of 10 GHz and a drain voltage of
30 V is in the range of 5.5 W mm=1 . Fig. 3.14 shows the measured power sweep of the
transistor. The device was load pull matched for maximum PAE in class-AB operation.
However, the impedances for maximum Pout and maximum PAE are closely neighbored
in the Smith chart. Therefore, the device delivers nearly maximum output power even
26
3.3 RF Performance
1
0.5
2
f↑
0.2
5
f = 20 GHz
0.2
0
0.5
1
2
5
∞
ΓL,opt
50 Ω
f = 0 Hz
-0.2
Tuner
-5
-2
-0.5
-1
Figure 3.13: Iso-contours of output power obtained by LP simulation of a 1 mm device
with dependence of ΓL,opt on frequency from DC to 20 GHz.
Pout (dBm), Gain (dB), PAE (%)
if matched for maximum PAE. The discrepancy in power density from the load pull
measurement to the calculated value from the DC I-V curves occurs mainly due to
60
50
Pout
Gain
PAE
40
30
20
10
0
5
10
15
20
Pin delivered (dBm)
25
Figure 3.14: Measured output power of an 8 × 125 µm HEMT with 0.8 µm shield at
10 GHz (Vds = 30 V, Id,DC = 100 mA mm=1 ).
27
Chapter 3 Power HEMT Structures for Broadband Applications
DC-to-RF dispersion and, since the DC measurements were performed on a 2 × 50 µm
device, thermal compression of the transistor.
In order to investigate the behavior of the output power, gain, and efficiency of a GaN
HEMT over frequency, load pull measurements were performed on a 6 × 75 µm device
in the frequency range from 6 GHz to 18 GHz. At each frequency point, the transistor
was tuned for maximum PAE and the power characteristics were traced at this point.
The maximum PAE is a precisely defined point, since it peaks at a certain drive level,
whereas the maximum output power is uncertain because of the compression behavior
of the device. The peaking of the PAE arises due to the definition in (3.16) and the
fact that from a certain drive level the compression of the gain is overproportional to
the increase in output power and therefore the PAE starts to decrease. A third-order
polynomial curve fit to measured data is shown in Fig. 3.15. The output power is ap-
70
Pout
Gain
PAE
DE
3
60
2
50
1
40
0
6
8
10
12
14
Frequency (GHz)
16
DE (%), PAE (%)
Pout (W), Gain/10 (dB)
4
30
18
Figure 3.15: Load pull frequency sweep of a 6 × 75 µm HEMT from 6 GHz to 18 GHz
(3rd -order polynomial data fit). Output power, gain, and efficiencies are measured at a load tuned for maximum PAE (Vds = 30 V,
Id,DC = 100 mA mm=1 ).
proximately constant, whereas the DE degrades dramatically with increasing frequency.
One reason for the decease in DE is attributed to DC-to-RF dispersion, which reduces
the saturation current and increases the knee voltage at high frequencies and bias conditions [22]. Another reason limiting the high frequency performance for devices operated
at high voltages is the feedback effect caused by the feedback capacitance Cgd and resistance Rgd . At high frequencies, current is absorbed in the voltage dependent Rgd and
thus the DE is diminished. A more detailed discussion on the impact of feedback on the
PAE of a HEMT can be found in [58]. The spreading between DE and PAE becomes
wider with increasing frequency because of the decreasing gain (low-pass behavior).
28
3.4 The Common-Source HEMT as a Reference
3.4 The Common-Source HEMT as a Reference
The common-source (CS) configuration for a FET is one of three basic single-stage
amplifier topologies. Because it provides both a voltage and a current gain, it is the
most commonly used topology for RF power amplifier MMICs. The signal enters the
gate and exits the drain. The terminal remaining is the source, which is referred to
as common“. Another interesting topology used in this work is the cascode, which is
”
formed by combining a CS FET with a common-gate (CG) FET. Cascode HEMTs are
discussed in detail in Section 3.6 and Chapter 4.
3.4.1 Small Signal Model
The small signal equivalent circuit of a HEMT is given in Fig. 3.16. It is a simplified
Gate
Lg
Intrinsic shell
Cgd Rgd
Rg
+
vi
−
Ri
Rd
Cgs
vi gm e −jωτ
gds
Ld
Drain
Cds
Rs
Ls
Source
Figure 3.16: Small signal equivalent circuit of a HEMT.
model to an extent adequate to give an overview of the intrinsic and extrinsic parameters, used throughout this work. The intrinsic small signal model consists of eight
components (8-term model). Cgs and Ri represent the gate-to-channel impedance, Cgd
denotes the feedback capacitance with losses Rgd . Cds and gds represent the SS output
impedance. Note, that due to the discrepancy between SS output impedance and loadline output impedance, 1/gds 6= Rds introduced in Section 3.2. The transconductance
gm is defined as the ratio ids /vgs and the gate-drain time delay τ indicates the transit
time associated with the carrier transport through the channel. It can be approximately
expressed as the gate-source time constant τgs = Ri Cgs .
Derivation of MSG as a Function of Frequency
The equivalent circuit in Fig. 3.16 is a two-port network. A common representation of
a two-port network is the admittance matrix as shown in Fig. 3.17. The admittance
29
Chapter 3 Power HEMT Structures for Broadband Applications
i1
v1
i2
v2
Y
Figure 3.17: Two-port network representation using Y parameters.
matrix is described by Y -parameters which are defined as
i1
Y11 Y12 v1
=
.
i2
Y21 Y22 v2
(3.24)
The Y -parameters are calculated using short-circuit tests at the terminals of the twoport network defined as
Ii Yij = .
(3.25)
Vj Vk =0 for k6=j
By expressing (3.25) in terms of the elements of the intrinsic shell of the equivalent
circuit in Fig. 3.16 and performing some algebraic simplifications, the admittance matrix
Y is found as
jω (Cgs + Cgd )
−jωCgd
.
(3.26)
Y =
gm − jωCgd
gds + jω(Cds + Cgd )
For the sake of simplicity, Ri and Rgd are neglected in the equation above. The feedback resistance Rgd is vital when considering feedback loss mechanisms as discussed in
Section 3.3.1. By considering Ri , Y is found as
" jωC
#
gs
+
jωC
−jωC
gd
gd
gs Ri
Y = 1+jωC
.
(3.27)
gm
1+jωCgs Ri − jωCgd gds + jω(Cds + Cgd )
The maximum stable gain MSG is defined as
MSG ≡
|S21 |
,
|S12 |
(3.28)
S21 and S12 can be expressed in terms of Y -parameters as
S21 = −
Y21 Y0
,
∆Y
(3.29)
Y12 Y0
,
(3.30)
∆Y
where ∆Y is the determinant of the Y -parameter matrix. Therefore the definition of
MSG holds also true for Y -parameters:
S12 = −
MSG ≡
30
|S21 |
|Y21 |
=
.
|S12 |
|Y12 |
(3.31)
3.4 The Common-Source HEMT as a Reference
By using (3.27) and (3.31), the MSG for the common-source FET in Fig. 3.16 is
gm
.
MSG = 1 +
(3.32)
ωCgd (ωCgs Ri − j) For ωCgs Ri 1 and gm /(jωCgd ) 1,
MSG ≈ 1 −
gm gm
.
≈
jωCgd
ωCgd
(3.33)
The approximated MSG (GMSG,app ) and the exact MSG (GMSG ) versus frequency for
an 8 × 125 µm 2-via GaN HEMT without shield according Table 3.1 are shown in
Fig. 3.18(a). Fig. 3.18(b) shows the deviation GMSG,app − GMSG . The approximated
30
0.35
GMSG,app
25
0.3
MSGdiff (dB)
MSG (dB)
0.4
GMSG
20
15
0.25
0.2
0.15
0.1
10
0.05
5
0
0
10
20
30
Frequency (GHz)
40
50
(a) GMSG and GMSG,app versus frequency.
0
10
20
30
Frequency (GHz)
40
50
(b) MSG diff versus frequency.
Figure 3.18: Comparison of the approximated MSG after (3.33) and the exact MSG
after (3.32) versus frequency for an intrinsic 8 × 125 µm HEMT.
MSG shows a deviation of below 0.1 dB up to a frequency of 25 GHz and is therefore a
reasonable estimation for the GaN25 process.
Numerical Values of Equivalent Circuit Elements
Table 3.1 shows typical small signal equivalent circuit element values of three different
8 × 125 µm GaN25 HEMTs. Compared are two 2-via devices with and without 1.3 µm
source connected field plate (shield) and an ISV device with 1.3 µm shield. The data
was extracted at a drain-source voltage of Vds = 30 V. The drain current was chosen
Id = 100 mA mm=1 to yield maximum transconductance gm,max . From the element values it can be seen, that the shield decreases the gate-drain capacitance Cgd but on the
other hand increases the gate-source capacitance Cgs . The ISV HEMT features a lower
gate-source capacitance Cgs as compared to the 2-via devices, because of the omission
31
Chapter 3 Power HEMT Structures for Broadband Applications
Table 3.1: Typical small signal equivalent circuit element values, extracted from 3 different 8 × 125 µm GaN HEMTs at Vds = 30 V and gm = gm,max : 2-via no shield,
2-via 1.3 µm shield, and ISV 1.3 µm shield.
Element
Intrinsic gate resistance Ri
Gate-source capacitance Cgs
Gate-source time constant τgs
Transconductance gm
Gate-drain capacitance Cgd
Gate-drain resistance Rgd
Drain-source capacitance Cds
Drain-source conductance gds
Gate resistance Rg
Drain resistance Rd
Source resistance Rs
2-via no SH
0.58
1.46
0.85
313
0.10
30.6
0.179
4.66
0.45
1.68
0.67
2-via SH
0.46
1.86
0.95
331
0.07
31.8
0.364
5.05
0.45
1.68
0.67
ISV SH
0.56
1.17
0.66
330
0.08
21.8
0.223
5.13
0.33
0.98
0.40
Unit
Ω mm
pF/mm
ps
mS/mm
pF/mm
Ω mm
pF/mm
mS/mm
Ω
Ω
Ω
of the airbridge to connect the sources of the individual unit cells, as can be seen in
Fig. 3.2. The main reason for applying the field plate in the GaN25 process is its ability
to reshape the electric field distribution in the channel and to reduce its peak value
on the drain side of the gate edge. As a consequence the breakdown voltage of the
transistor is increased.
The intrinsic circuit parameters in the table above were extracted from S-parameter
measurements at various bias conditions for different device geometries and direct solvR
ing the equations for the Y -parameters using the Matlab
program TOP extra1“ [104].
”
Fig. 3.19 shows the definition of the reference planes for the model extraction of the
HEMT. The reference planes are set back from the edge of the drain and gate buses
Reference plane
drain
Reference plane
gate
Figure 3.19: Reference planes at the gate and drain of a HEMT for model extraction.
by 2.5 µm. The connecting ports of the layouts in the ADS design kit are set back by
2.5 µm as well. Thereby, by connecting two elements, the reference planes match and a
layout overlap is provided, which is relevant for the fabrication of the circuit.
32
3.5 The Bode-Fano Criterion Applied on GaN HEMTs
3.5 The Bode-Fano Criterion Applied on GaN HEMTs
Bode-Fano criterion or Bode-Fano limit are terms often cited in research publications
on broadband amplifiers. However, the topic is mostly discussed insufficiently. Calculations are done, if anything, for the output of an active device, and the input is glossed
over. Because of its fundamental character, the Bode-Fano criterion shall be treated in
more detail here. Numerical examples will be given for the GaN25 technology as well
as for an industrial GaN process. The results will then be confronted with an industrial
GaAs pHEMT process.
Given an impedance, including at least one resistive and one reactive element, the
Bode-Fano criterion answers the question: How low a reflection coefficient can a match”
ing network achieve, in a given frequency band, with the only restriction that the
matching network be physically realizable?“. The substance of the Bode-Fano criterion
is illustrated in Fig. 3.20 in the Smith chart. The example in the figure states, that for a
1
0.5
2
1.6 pF
Γmax
0.2
0
0.2
5
0.5
fb
1
fs
2
5
15 Ω
∞
fa
-0.2
1.6 pF
15 Ω
-5
-2
-0.5
-1
Figure 3.20: Illustration of the meaning of the Bode-Fano criterion; note that the Smith
chart is normalized to 15 Ω.
given parallel circuit of a capacitor and a resistor, the capacitance can be compensated
within the boundaries of Γmax (red circle) over a frequency range from fa to fb . A
perfect compensation of the capacitor, i.e. Γmax = 0, would be possible at a single frequency fs only. The illustration makes clear, that the Bode-Fano criterion discusses the
theoretical limits for the compensation of the reactive element only, a transformation
of the resistive part is not considered, e.g. say from 15 Ω to 50 Ω. The Bode-Fano cri-
33
Chapter 3 Power HEMT Structures for Broadband Applications
terion is a technology related figure of merit. The discussion on theoretical limitations
of matching networks, including the transform of real impedances will be carried on in
Section 5.4.
3.5.1 Bode-Fano Criterion for the Output of a GaN HEMT
The matching problem was first analyzed theoretically by Bode [10] for the simple case
of a resistor shunted by a capacitor as shown in Fig. 3.21(a). This network is a valid
Γ
Lossless
matching
network
Cds,eff Rds
(a) Parallel RC as a model for the output
impedance of a HEMT.
Γ
Lossless
matching
network
Cgs,eff
Rg,eff
(b) Series RC as a model for the
input impedance of a HEMT.
Figure 3.21: Definition of τ and Γ for Bode-Fano networks.
option to model the output impedance, i.e. the complex conjugate of the optimum load
impedance of a HEMT, as discussed in Section 3.3. The lossless matching network (MN)
is designed to match such a load into a generator generator having a purely resistive
output impedance, typically 50 Ω. Γ is the magnitude of the corresponding reflection
coefficient, Cds,eff and Rds are the effective drain-source capacitance and the output
resistance of the HEMT, respectively. Bode showed that the reflection coefficient Γ is
constrained by the integral equation
Z ∞
1
π
ln
dω ≤ ,
(3.34)
|Γ (ω)|
τp
0
where the time constant τp for the parallel RC circuit is defined as
τp = Rp Cp .
(3.35)
Later, the theoretical analysis was expanded by Fano [32], who derived closed-form
expressions for a number of special cases. The fundamental limit on the matching
bandwidth is examined for cases with three and four elements in [51]. A simplified
analysis of the Bode-Fano criterion is given in [90].
The goal of a broadband matching network is to achieve a Γ as small as possible
within a specified bandwidth ωb − ωa . Therefore the contribution of the integral outside
the bandwidth ωb − ωa should ideally be 0. The response of such an ideal matching
network is shown in Fig. 3.22. It is indistinguishable from that of an ideal filter. The
reflection coefficient of an ideal filter must be 1 outside the band and must remain below
a maximum value Γmax within the band. By further assuming that Γ = const. = Γmax
34
3.5 The Bode-Fano Criterion Applied on GaN HEMTs
R
=0
|Γ|
1
Γmax
ωa
ωb
ω
Figure 3.22: Illustration of the Bode-Fano criterion.
within the band, the integral in (3.34) can be rewritten as [90]
Z ωb
1
ln
dω.
Γmax
ωa
(3.36)
Solving the integral for ω yields
ln
1
(ωb − ωa ) .
Γmax
(3.37)
By recalling (3.34), the simplified Bode-Fano criterion can be obtained as
ln
1
Γmax
≤
π
.
(ωb − ωa ) τp
(3.38)
1
.
2 (fb − fa ) τp
(3.39)
Since ω = 2πf , (3.38) can be rewritten as
ln
1
Γmax
≤
Rearranging (3.39) for Γmax and ∆f = fb − fa yields
Γmax ≥ e
and
∆f ≤ −
1
− 2∆f
τ
p
1
,
2τp ln Γmax
(3.40)
(3.41)
respectively. According Fig. 3.21(a), the time constant is τp = Rds Cds,eff . The reflection
coefficient Γ can also be expressed as a ratio in decibels (dB), called the return loss (RL),
and is defined as
1
(3.42)
RL = 10 lg 2 dB = −20 lg |Γ| dB.
Γ
35
Chapter 3 Power HEMT Structures for Broadband Applications
The return loss is the ratio of incident power Pin to reflected power Pref at a generatorload interface in dB
Pin
RL = 10 lg
dB,
(3.43)
Pref
and is therefore a measure of how good a generator is matched to a load. The Bode-Fano
criterion can also be expressed in terms of the quality factor Q [84]:
Γmax ≥ e
−
πQloaded
Qof load
,
(3.44)
where Qloaded is defined as
f0
,
∆f
(3.45)
|BL |
|XL |
=
.
RL
GL
(3.46)
Qloaded =
and Qof load is defined as
Qof load =
|XL | and |BL | are the absolute values of the reactance and susceptance of the load,
respectively and RL and GL are the load resistance and conductance, respectively.
Rearranging (3.44) for Qloaded yields
Qloaded ≤ −
Qof load ln Γmax
.
π
(3.47)
The quality factor will be discussed in more detail in Section 5.5.1. By inserting (3.45)
and (3.46) into (3.44) and using the relations |BL | = 2πf0 Cds,eff and GL = 1/Rds , the
Bode-Fano criterion as formulated in (3.40) is obtained. Qof load will be referred to
single letter Q for the subsequent discussions.
Numerical Example for the Output of Typical GaN and GaAs HEMT Devices
The optimum load reflection coefficient ΓL,opt of a transistor are obtained by load pull
measurements. ΓL,opt can be converted in a parallel circuit of a resistor and a capacitor according the equivalent circuit shown in Fig. 3.21(a). The Bode-Fano bandwidth
can then be calculated using (3.41). Numeric values for the elements of the parallel equivalent circuit and the calculated Bode-Fano bandwidth are listed in Table 3.2
for various devices. The devices were load pull tuned for maximum power at 10 GHz.
The table contrasts the load pull data and Bode-Fano bandwidth for a maximum return loss of 10 dB of an 8 × 125 µm IAF GaN device with a 10 × 125 µm GaN and a
16 × 75 µmGaAs device from Triquint [100,103]. The IAF GaN device was measured at
a drain voltage of 30 V, the Triquint GaN device at 28 V and the GaAs device at 12 V.
The load reflection coefficient of the Triquint devices includes the bond pad, whereas
the value of the IAF device is de-embedded, i.e. does not include bond pads. The
values of the parallel resistor and capacitor are normalized to a gate width of 1 mm.
Since Rds ∝ 1/Cds,eff , τp = const over device size and consequently, the achievable
36
3.5 The Bode-Fano Criterion Applied on GaN HEMTs
Table 3.2: Comparison of load pull data and Bode-Fano bandwidth for GaN and GaAs
technologies. IAF ISV is an 8 × 125 µm GaN25 device with 0.9 µm shield,
TQ GaN and TQ GaAs are Triquint 10 × 125 µm GaN and 16 × 75 µm GaAs
devices, respectively [100, 103].
Parameter
Load reflection coeff ΓL a
Parallel resistance Rds
Parallel capacitance Cds,eff
Bode-Fano bandwidth ∆f b
a
b
GaN
IAF ISV
TQ GaN
◦
0.59∠119
0.64∠130◦
59.5
62.1
0.42
0.43
16.6
15.6
GaAs
TQ GaAs
0.56∠145◦
34.3
0.43
28.2
Unit
Ω mm
pF/mm
GHz
Optimum ΓLoad for maximum power, not normalized
Maximum achievable bandwidth for Γmax = 0.3
bandwidth at the output is independent of the TGW of the device. Because Rds ∝ Vds ,
the trend towards higher operational voltages in GaN leads to higher optimum load resistors. Therefore the Bode-Fano criterion gets more limiting for high voltage devices.
A hypothetical operation of the IAF GaN device in the table above at 50 V, would yield
a Bode-Fano bandwidth of 10 GHz. Therefore, it is obvious, that GaAs is beneficial
over GaN in terms of maximum achievable Bode-Fano bandwidth. For the typical operation conditions as used to construct Table 3.2, the Bode-Fano bandwith of the IAF
HEMT is 16.6 GHz and thus it is very difficult to cover 6 GHz to 18 GHz bandwidth
with a return loss better than 10 dB by reactively matching a GaN transistor at the
output. However, this theoretical limitation does not pose the dominating difficulty.
The main limiting factor is the large impedance transformation ratio to be dealt with
in the output matching network, attributable to large gate width devices. Since this
limitation is not discussed by the Bode-Fano criterion, it needs special consideration
and is addressed by reference to filter theory in Section 5.5.
3.5.2 Bode-Fano Criterion for the Input of a GaN HEMT
Since the input of an intrinsic HEMT is of series RC nature, the considerations in
the previous section are not straightforwardly adoptable to the input of the transistor.
Fig. 3.23(a) shows the simplified equivalent circuit of the input of a GaN HEMT in
common-source configuration. The three resistors Rg , Ri and Rs can be joined together
to form the complex gate impedance Zg . This impedance has to be assumed complex
because the currents trough the resistors Rg , Ri and Rs are not in phase due to the
presence of Cgs . The simplified configuration is shown in Fig. 3.23(b). It is of the
form of the Bode-Fano network in Fig. 3.21(b) and therefore useful to determine the
Bode-Fano bandwidth of the input of a HEMT. By applying Kirchoff’s circuit laws on
37
Chapter 3 Power HEMT Structures for Broadband Applications
igd Cgd
igs Rg
vgs
+
vi
−
ids
igs
Cgs
igs
gm vi
Ri
vgs
+
vi
−
Rs
Cgs
vgs
(b) Complex gate
impedance Zg .
Cgs
0
Cgs
Rg,eff
Zg
(a) Equivalent circuit of the input
of a GaN HEMT.
+
vi
−
(c) Zg =Rg,eff +
0
1/ jωCgs
.
Figure 3.23: Equivalent circuit of the input of a GaN HEMT in common-source configuration and simplified configurations with complex input impedance Zg .
the circuit in Fig. 3.23(a), the gate impedance Zg can be derived:
igs = vi jωCgs + igd ,
(3.48)
ids = gm vi − igd
(3.49)
vgs = igs Rg + vi + (igs − igd ) Ri + (igs + ids ) Rs .
(3.50)
and
The gate impedance in Fig. 3.23(b) is
Zg =
vgs − vi
.
igs
(3.51)
By substituting (3.50) for vgs in (3.51), the gate impedance can be expressed as
Zg = Rg + Ri + Rs +
igd
ids
Rs −
Ri .
igs
igs
(3.52)
By expressing the ratio ids /igs as complex current gain β,
igd
Zg = Rg + Ri + Rs β + 1 −
Ri .
igs
(3.53)
Zg ≈ Rg + Ri + Rs β + 1 .
(3.54)
Since igd igs ,
By applying (3.48) and (3.49) and neglecting igd , the complex current gain is expressed
as
gm
β≈
.
(3.55)
jωCgs
38
3.5 The Bode-Fano Criterion Applied on GaN HEMTs
Obviously, the gate impedance Zg can be regarded as an effective gate resistor Rg,eff ,
formed by the sum of Rg , Ri , and Rs , plus an imaginary part:
gm
Rs ,
jωCgs
(3.56)
Rg,eff = Rg + Ri + Rs .
(3.57)
Zg ≈ Rg,eff +
with
In order to obtain the simplified equivalent circuit according Fig. 3.23(c), (3.56) can be
rewritten as
1
Zg ≈ Rg,eff +
,
(3.58)
0
jωCgs
where
0
Cgs
=
Cgs
.
gm Rs
(3.59)
0 and C
The series connection of Cgs
gs forms the effective gate-source capacitance
Cgs,eff =
0
Cgs Cgs
Cgs
,
=
0
C
Cgs + Cgs
1 + Cgs
0
(3.60)
gs
and since
0
Cgs
Cgs is valid independent of gate width, because gm Rs 1 and ≈ const.,
Cgs
.
(3.61)
Cgs,eff ≈ Cgs 1 − 0
Cgs
Substituting (3.59) into (3.61) yields
Cgs,eff ≈ Cgs (1 − gm Rs ) .
(3.62)
As a result, the equivalent circuit in Fig. 3.23(a) can be expressed by the series connection of Rg,eff and Cgs,eff and therefore in the wanted form of the Bode-Fano network in
Fig. 3.21(b). Furthermore, (3.62) implies, that the source resistance Rs has a scaling
effect on the effective gate-source capacitance Cgs,eff .
In order to find Bode’s integral equation for the input of a HEMT, the parallel RC
output network in Fig. 3.21(a) can be expressed in terms of its series equivalent:
Rp =
Rs 2 + Xs 2
,
Rs
Cp = −
Xs
,
ω0 (Rs 2 + Xs 2 )
(3.63)
where Xs is the capacitive reactance of the series capacitance Cs :
Xs =
1
.
ω0 C s
(3.64)
The time constant of the parallel RC from (3.35) becomes
τp = Rp Cp =
Xs
1
1
= 2
= 2 ,
ω0 Rs
ω0 Rs Cs
ω0 τs
(3.65)
39
Chapter 3 Power HEMT Structures for Broadband Applications
with τs representing the time constant for the series RC circuit τs = Rs Cs . By plugging
(3.65) into (3.34), Bode’s integral can be rewritten as
Z ∞
1
ln
dω ≤ ω0 2 πτs ,
(3.66)
|Γ
(ω)|
0
where the center frequency ω0 is the geometric mean of the frequency band
√
ω0 = ωa ωb .
(3.67)
By solving the integral and proceeding in a similar way as for the output, the Bode-Fano
criterion for the input yields
ω0 2 τs
∆f ≤ −
.
(3.68)
2 ln Γmax
The time constant for the input of the HEMT is defined as τs = Rgs,eff Cgs,eff , corresponding with the Bode-Fano network in Fig. 3.21(b). The element values for Rgs,eff
and Cgs,eff can be calculated after (3.57) and (3.62), respectively. It is interesting to
note that the Bode-Fano bandwidth of the input of a HEMT is dependent on the center frequency, whereas the Bode-Fano bandwidth of the output is not. Furthermore,
the time constant τ is now in the nominator, whereas it is in the denominator in the
equation for the output (3.41). The consequences of this results for broadband amplifier design will be discussed in Section 3.5.3. The numerical example for the output of
a typical GaN device on page 36 showed, that the Bode-Fano criterion is potentially
limiting the obtainable bandwidth at the output of an amplifier. In the following, a
numerical example for the input of a typical GaN HEMT will show, to what extend the
Bode-Fano criterion limits the obtainable bandwidth at the input of an amplifier.
Numerical Example for the Input of Typical GaN and GaAs HEMT Devices
The intrinsic circuit parameters required to calculate Rgs,eff and Cgs,eff were extracted
R
in the same way as described on page 32, using the Matlab
program TOP extra1“
”
[104]. The Bode-Fano bandwidth was then calculated using (3.68). Numeric values
for the intrinsic elements and the calculated Bode-Fano bandwidth at a frequency of
10 GHz are listed in Table 3.3 for the same transistors as used in the output in Table 3.2.
The table contrasts the extracted intrinsic small signal element values and Bode-Fano
bandwidth for a maximum return loss of 10 dB of an 8 × 125 µm IAF GaN device with
a 10 × 125 µm GaN and an 8 × 75 µm GaAs device from Triquint. The GaAs data are
extracted from a 0.6 mm unit cell. The element values are normalized to eight-finger
devices with a total gate width of 1 mm. The reference planes of the Triquint devices
include the bond pads, as opposed to the de-embedded IAF device shown in Fig. 3.19.
Because Rg increases with increasing UGW, whereas Ri and Rs decrease, Rg,eff and
Cgs,eff do not scale linearly with gate width. As a result, Rg,eff 6∝ 1/Cgs,eff and thus
τs 6= const over device size. The Bode-Fano bandwidth of the input is not independent
of the TGW, as it was the case for the output, i.e. the Bode-Fano bandwidth increases
40
3.5 The Bode-Fano Criterion Applied on GaN HEMTs
Table 3.3: Comparison of small signal intrinsic input element values and Bode-Fano
bandwidth for GaN and GaAs technologies. IAF ISV = 8 × 125 µm GaN25
with 0.9 µm shield, TQ GaN and TQ GaAs = Triquint 10 × 125 µm GaN and
16 × 75 µm GaAs, respectively [100, 103] (Vds = 30 V, gm = gm,max ).
Parameter
Gate resistance Rg
Intrinsic gate resistance Ri
Source resistance Rs
Gate-source capacitance Cgs
Transconductance gm
Effective gate resistance Rg,eff a
Eff. gate-source capacitance Cgs,eff
Bode-Fano bandwidth ∆f b
a
b
GaN
IAF ISV TQ GaN
1.02
0.98
0.56
0.33
0.40
0.16
1.67
1.43
0.280
0.216
1.98
1.47
1.48
1.38
4.8
3.3
GaAs
TQ GaAs
0.40
1.04
0.30
2.85
0.305
1.74
2.59
7.4
Unit
Ω/mm
Ω mm
Ω mm
pF/mm
S/mm
Ω
pF/mm
GHz
For the definitions of Rg,eff and Cgs,eff see (3.57) and (3.62)
Maximum achievable bandwidth for Γmax = 0.3 and f0 = 10 GHz
with increasing UGW. Because of its higher value of Cgs , GaAs again is beneficial
over GaN in terms of maximum achievable Bode-Fano bandwidth at the input. For
the typical intrinsic element values of the 1 mm devices in Table 3.3, the Bode-Fano
bandwith of the IAF HEMT is 4.8 GHz. For a center frequency of f0 = 12 GHz, the
Bode-Fano bandwith is increased to 6.9 GHz, and thus it is impossible to cover 6 GHz
to 18 GHz bandwidth with a return loss better than 10 dB by reactively matching a 1 mm
GaN transistor at the input. A remedy can be provided by relaxing the requirements
for Γmax or using additional circuitry at the gate of the transistor, which sacrifices gain.
Using devices with larger TGW is not an option for targeted frequencies above 11 GHz
due to the limitation set by the K-point as depicted in Fig. 3.4.
3.5.3 Conclusions on the Bode-Fano Criterion
The Bode-Fano criterion is a technology related figure of merit, which quantifies the
attainable reflection coefficient in a given frequency band, when compensating the reactive element of a Bode-Fano network according Fig. 3.21 by a matching network of
arbitrary complexity. For the input of a transistor, the reactive element to be compensated is represented by the effective gate-source capacitance Cgs,eff , for the output it
is the effective drain-source capacitance Cds,eff . The Bode-Fano criterion does not give
any information on the required complexity of a matching network in order to realize
a certain impedance transformation ratio over a given frequency range. By considering
the Bode-Fano criterion only, the following statements can be made:
• GaN is not beneficial over GaAs for broadband amplifier design.
41
Chapter 3 Power HEMT Structures for Broadband Applications
• The Bode-Fano bandwidth of the output of a HEMT in GaN25 technology for
typical operation conditions is in the vicinity of 16 GHz.
• The Bode-Fano bandwidth of the output is independent of device geometry and
the center frequency of the matching network.
• The Bode-Fano bandwidth of the input of a 1 mm HEMT in GaN25 technology
is below 5 GHz and therefore more critical than the limit at the output.
• The Bode-Fano bandwidth of the input is dependent on the total gate width of
the device and on the center frequency of the matching network.
• Since in (3.68) τs is in the nominator, increasing Rg,eff and Cgs,eff leads to an
increase of the Bode-Fano bandwidth at the input.
The last bullet suggests, that it is allegedly easy to design a HEMT with a high BodeFano bandwidth of the input. But according (3.32) and (3.12), high Rg and Cgs contradict the effort to obtain a high MAG and fT . In practical broadband amplifiers Rg can
be artificially enhanced to achieve matching at low frequencies (f fT ), e.g. to 50 Ω.
This technique is called forced matching“. It is applied, if the gain of the transistor is
”
sufficiently high at the lower band edge. The Bode-Fano criterion poses a severe problem
for the input matching network of an amplifier, which is even more critical in multistage
designs, where two complex impedances face at the interstage. In Section 5.9, a novel
power amplifier architecture is proposed, which evades the aggravated matching aspects
introduced by designing multistage reactively-matched amplifiers. Because of the high
output resistance of GaN transistors, the Bode-Fano limit at the output is aggravated
dramatically as compared to lower voltage technologies such as GaAs. However, this
theoretical limitation does not pose the dominating difficulty. The main limiting factor
is the large impedance transformation ratio to be dealt with in the output matching
network. In this regard, the high output resistance of GaN is beneficial, as will be
discussed in more detail in Section 5.5.
3.6 Dual-Gate and Cascode GaN HEMTs
Because of the high power requirement on the amplifiers in this work, active devices are
chosen with a TGW as large as possible by still sufficing the condition K < 1, or at least
not exceeding it excessively, i.e. at the upper edge of the frequency band of operation,
the devices are operated close to the K-point. As discussed in Section 3.1.2, 8 × 75 µm
is a typical transistor size to be employed in reactively matched power amplifiers up to
Ku band in GaN25 technology. Because the K-point of such a device is at 18 GHz, and
thereby at around 2/3fT of the technology, gain is a critical factor at the upper limit of
the design frequency. A very attractive way to enhance the gain of an active device is to
reduce the Miller effect“1 by using a cascode topology. Beneficial effects of dual-gate
”
1
The Miller effect accounts for the increase in the equivalent input capacitance of a transistor due to
amplification of the effect of the feedback capacitance Cgd .
42
3.6 Dual-Gate and Cascode GaN HEMTs
devices at a frequency of 2 GHz have been demonstrated in, e.g., [106]. This section
treats the basic properties of dual-gate transistors and shows results of manufactured
devices in a variety of different geometries. A method to accurately model dual-gate
GaN HEMT structures using a distributed modeling approach is discussed in Chapter 4.
3.6.1 Definition of Cascode and Dual-Gate Devices
The cascode is a two-stage amplifier composed of a HEMT in common-source configuration followed by a HEMT in common-gate configuration, where the former acts as
a current controlling device. The schematic representation of a cascode is shown in
Fig. 3.24. The gate, drain and source of the common-source FET Q1 are denoted G1 ,
D1 /S2
Q2
Q1
S1 G
2
G1
D2
Rbias
Bias G2
CRF
Figure 3.24: Simplified schematic of the cascode topology.
D1 , and S1 , respectively, whereas G2 , D2 , and S2 denote the ports of the common-gate
FET Q2 . The DC biasing of the CG device is done via the resistor Rbias . The capacitor CRF provides an RF-short. The photograph of a manufactured discrete 6 × 75 µm
cascode is shown in Fig. 3.25. The cascode is formed by the concatenation of the CS on
DC bias G2
CS HEMT
Rbias
CG HEMT
CRF /2
G1
D2
CRF /2
Figure 3.25: Photograph of a 6 × 75 µm discrete cascode structure.
the left and the CG device on the right. The bias resistor Rbias and the RF capacitor
CRF are also indicated in the picture.
By combining the two transistors of the cascode into one single active device, the dualgate (DG) transistor structure is obtained. The layout of such a structure with a total
43
Chapter 3 Power HEMT Structures for Broadband Applications
gate width of 8 × 75 µm is shown in Fig. 3.26. The structure has two gate buses, one for
the CS transistor and one for the CG transistor, where the gate fingers of both devices
are interdigitated. In order to reduce the extrinsic parasitics, an ohmic metal area
Airbridge Gate bus CG
CRF /2
GND
Via
Gate finger Gate bus CS
D2
Drain bus
G2
CRF /2
S1
G1
Via
Ohmic metal
Figure 3.26: Layout of an 8 × 75 µm dual-gate HEMT. Yellow = METG, red = MET1,
brown = OHM, orange = GATE (see Fig. 3.26 for layer definitions).
Gray = MET1 + METG metal stack, blue = airbridge.
(brown color) is placed between the gates and thereby forms the interconnection between
the CS and the CG device. In the following discussion, for the sake of clarity, the
layer names and colors are held consistent with the process layer definition in Fig. 2.3.
Additionally, the stacked metal layers metal1 (MET1) and galvanic metal (METG),
and the airbridge formed in galvanic metal, are introduced in Fig. 3.26 in gray and blue
colors, respectively. Compared to the discrete cascode circuit, the DG structure is much
more compact and thus the matching between the CS and CG device can be managed
more efficiently. On the other hand, the description of such structures by a model is
tedious mainly due to the RF interaction which can occur between the three accessible
ports, i.e. the two gates and the drain of the common-gate HEMT. This problem is
addressed in Chapter 4. The equivalent circuit configuration and the schematic cross
section of a dual-gate HEMT in GaN25 technology with typical layer thicknesses and
electrode pitches is shown in Fig. 3.27 (figure is not drawn to scale). Dual-gate HEMTs
have been previously applied at the IAF for MMICs in GaAs technology, e.g. [97].
3.6.2 Stability Considerations of Dual-Gate HEMTs
A major challenge in dual-gate devices is to handle their potential instability. A typical
phenomenon is that the magnitude of S22 exceeds unity at a certain frequency, as
illustrated in Fig. 3.28 for an 8 × 100 µm dual-gate device, where |S22 | crosses the unity
circle of the Smith chart at a frequency of 25 GHz.
The origin of the effect causing |S22 | to exceed unity and thereby giving reason for the
potential instability of a DG device can best be investigated when having a closer look
at the cascode topology shown in Fig. 3.24. Figs. 3.29(a) and 3.29(b) show the two-port
representations of a HEMT in CS and CG configuration, respectively. In a two-port
network, the elements that comprise a common voltage or current of the inputs and
44
3.6 Dual-Gate and Cascode GaN HEMTs
Drain 2
G1
0.7 µm
Source
1
CG HEMT
Ohm
4.7 µm D1 /S2
G1
G2
2.0 µm
3 nm GaN cap
Drain
2
22 nm AlGaN barrier
Ohm
D1 /S2
1.9 µm GaN buffer
G1
CS HEMT
100 µm SI-SiC substrate
Source 1
(a) Connection of
two single gated
HEMTs.
(b) Cross section of a basic AlGaN/GaN
dual-gate HEMT.
Figure 3.27: Equivalent circuit configuration and schematic cross section of a dual-gate
HEMT in GaN25 technology.
1
0.5
2
0.2
5
0.2
f = 25 GHz
0.5
1
2
5
-0.2
∞
-5
-2
-0.5
-1
Figure 3.28: S22 versus frequency of an 8 × 100 µm dual-gate HEMT.
outputs are critical for stability considerations. In the CS configuration, these are Ls
and Cgd and in the CG configuration Lg and Cds . In Fig. 3.29, the common voltages and
currents are denoted v12 and i12 , respectively. In the following analysis, it is assumed,
45
Chapter 3 Power HEMT Structures for Broadband Applications
v12
v12
Cgd
i1
D
D
v1
G
S
i12
Cds
i1
i2
v1
v2
S
v2
G
i12
Ls
(a) Common-source HEMT.
i2
Lg
(b) Common-gate HEMT.
Figure 3.29: HEMT in common-source and common-gate configuration with feedback
elements critical for device stability.
that the CS FET of the cascode topology in Fig. 3.24 is high-ohmic and thus the source
of the CG FET is open. Fig. 3.30 shows the two-port representation of the FET for this
scenario. The capacitors in dashed lines represent the intrinsic parasitic capacitance
Lg
Lg
V2
V1
≡
V1
Figure 3.30: FET with open source.
shell. Fig. 3.31 shows the equivalent circuit of the FET with open source. We consider
Cgd
Lg
V1
+
vi
−
Ri
Cgs
vi gm
gds
Cds
Figure 3.31: Equivalent circuit of a FET with open source.
Lg as simply connected in front of the gate terminal of the FET and therefore neglect it
in the further analysis. By using the admittance matrix representation of Section 3.4.1,
the FET with open source can be described according Fig. 3.32. The voltage V and
46
3.6 Dual-Gate and Cascode GaN HEMTs
V
i1
i2
v1
I
v2
Y
Figure 3.32: Two-port network representation of the FET with open source.
current I are defined as
V = v2 − v1 ,
(3.69)
I = i2 = −i1 .
(3.70)
In terms of Y -parameters, the two-port network is described by
−I = Y11 v1 + Y12 v2 ,
(3.71)
I = Y21 v1 + Y22 v2 .
(3.72)
By adding (3.71) and (3.72), we obtain
0 = (Y11 + Y21 ) v1 + (Y12 + Y22 ) v2 ,
(3.73)
which can be rearranged to
v2 =
− (Y11 + Y21 )
v1 .
Y12 + Y22
(3.74)
Substituting v2 by (3.74) in (3.69) and (3.72) yields
− (Y11 + Y21 )
V =
− 1 v1
Y12 + Y22
and
I = Y21 v1 − Y22
Y11 + Y21
Y12 + Y22
(3.75)
v1 ,
(3.76)
respectively. By using (3.75) and (3.76), the two-port network in Fig. 3.32 can be
expressed in terms of I, V and Y as
−V
Y11 + Y21
Y21 − Y22
I=
.
(3.77)
+Y21
Y12 + Y22
1 + YY11
12 +Y22
Simplifying and rearranging (3.77) gives
[Y21 (Y12 + Y22 ) − Y22 (Y11 + Y21 )]
Y11 + Y12 + Y21 + Y22
−Y12 Y21 + Y11 Y22
=V
.
Y11 + Y12 + Y21 + Y22
I = −V
(3.78)
47
Chapter 3 Power HEMT Structures for Broadband Applications
Inserting the Y-parameters for the simplified equivalent circuit from (3.26) (neglecting
Ri and Rgd ) into (3.78) yields
I=V
[(−gm + jωCgd ) (gds + jωCds ) + (gds + jω (Cds + Cgd )) (gm + jωCgs )]
.
gm + gds + jω (Cgs + Cds )
(3.79)
Dividing I in (3.79) by V gives the effective admittance Yeff of the common-gate HEMT
with open source:
Yeff =
−w2 [Cds (Cgd + Cgs ) + Cgs Cgd ] + jω [gm Cgd + gds (Cgs + Cgd )]
I
=
.
V
gm + gds + jω (Cgs + Cds )
(3.80)
For f fT we have gm jω (Cgs + Cds ) and therefore the denominator in (3.80) can
be approximated as gm + gds . Since all the capacitances in the nominator are positive,
it is obvious, that < {Yeff } < 0 for f fT . When the frequency of operation f is
approaching fT , the approximation gm jω (Cgs + Cds ) is no longer valid. The real
part of (3.80) is given as
< {Yeff } =
ω 2 Cgs (Cgs gds − Cds gm )
.
ω 2 (Cds + Cgs ) 2 + (gds + gm ) 2
(3.81)
Having regard to the typical values for the intrinsic elements of an 8 × 125 µm GaN
HEMT in Table 3.1, it is obvious that Cgs gds < Cds gm and thus < {Yeff } is negative,
and the dual-gate HEMT is potentially unstable for all frequencies. When taking Ri in
Fig. 3.31 into account and repeating the calculations above, the effective admittance is
found to be
Yeff = jωCgd −
gm + gds
ωCgs (ωCds − jgds )
.
+ jω (Cds + Cgs ) + ωCgs (−ωCds + jgds ) Ri
(3.82)
The sign of < {Yeff } is now dependent on frequency. Fig. 3.33 shows < {Yeff } as a
function of frequency for an intrinsic 8 × 125 µm HEMT according Fig. 3.31. The
values for the intrinsic elements were obtained from Table 3.1. A negative value for
< {Yeff } means, that the device is unstable, i.e. the device is potentially unstable from
0 up to 150 GHz where it becomes stable for f > 150 GHz. The analysis with this
simplified model shows, that dual-gate devices feature potential instability by nature.
However, the measured trajectory of S22 of the 8 × 100 µm dual-gate HEMT in Fig. 3.28
suggests, that the device is stable up to a certain frequency, before it turns unstable.
In order to investigate this behavior, the simplified equivalent circuit from Fig. 3.31
is extended by the feedback resistance Rgd and the gate-source time constant τgs , to
obtain the complete intrinsic 8-term model as shown in Fig. 3.16. Due to the higher
complexity of the circuit, the analysis to obtain < {Yeff } as a function of frequency was
not performed analytically as for the simplified case. However, it was simulated in ADS,
using the intrinsic element values of an 8 × 125 µm 2-via HEMT without shield, shown
in Table 3.1. The result for < {Yeff } as a function of frequency is shown in Fig. 3.34.
48
3.6 Dual-Gate and Cascode GaN HEMTs
10
< {Yeff } (mS)
5
0
-5
-10
-15
-20
0
20
40
60
80
100
Frequency (GHz)
120
140
160
Figure 3.33: < {Yeff } as a function of frequency for the simplified intrinsic equivalent
circuit (neglecting Rgd and τgs ) of an 8 × 125 µm HEMT.
8
< {Yeff } (mS)
6
4
2
0
-2
-4
-6
0
10
20 25 30
40
50
Frequency (GHz)
60
70
80
Figure 3.34: < {Yeff } as a function of frequency for the complete 8-term intrinsic equivalent circuit of an 8 × 125 µm HEMT.
The value for < {Yeff } is positive up to 25 GHz before it turns negative at 25 GHz, i.e.
the device is stable below 25 GHz. Above 25 GHz it is potentially unstable and becomes
stable again at frequencies much higher than fT of the device. This result matches the
observation for the measured 8 × 100 µm dual-gate HEMT in Fig. 3.28. A stabilization
method for DG devices is described in Section 4.2.1.
49
Chapter 3 Power HEMT Structures for Broadband Applications
3.7 Advanced Dual-Gate Structures
By using the distributed model described later on in Section 4.2 and the analysis from
Section 3.6.2, it can be seen, that it is beneficial for the performance of a dual-gate
device, to provide the RF-short to the gate G2 as close as possible, i.e. to minimize the
distance between the capacitor CRF and the gate bus of gate G2 and thereby minimize
the inductance of the interconnection. By doing so, the point where S22 exceeds unity
can be moved to higher frequencies and therefore the stability of the device can be
improved. Based on this knowledge, an experimental analysis to achieve this goal was
performed. The resulting advanced dual-gate (ADG) structures are discussed in this
section.
3.7.1 Fabricated Advanced Dual-Gate Structures
As mentioned above, the motivation of the advanced dual-gate structures is to minimize the distance between the RF capacitor and the gate bus of the CG device. In
the proposed structures, this is achieved by using the gate metal and metal1 to form a
MIM capacitor. Fig. 3.35 shows the layout of an 8 × 75 µm advanced dual-gate HEMT.
The gate bus in question is implemented in gate metal as well and therefore directly
Detail areas see Fig. 3.36
Gate bus CG
D2
Airbridge
GND
CRF /2
Via
Gate finger Gate bus CS
Drain bus
CRF /2
S1
G1
G2
Via
Ohmic metal
Figure 3.35: Layout of an 8 × 75 µm ADG HEMT. Green = MET1 + GATE MIM capacitor, red = MET1, brown = OHM, orange = GATE, gray = MET1 + METG
metal stack, blue = airbridge.
connected to one electrode of the capacitor. The other electrode is ground (GND)
connected by means of airbridges connected to the metal stack of the via hole. This
arrangement allows for a closer placement of the capacitor as compared to the conventional dual-gate device in Fig. 3.26, where the capacitor is formed by the layers
metal1 and galvanic metal. Since in this scenario the MET1 electrode of the capacitor
is directly connected to ground, the gate bus of the CG device (also implemented in
MET1) requires an airbridge to connect to the METG electrode of the capacitor. In
addition to the conventional DG layout in Fig. 3.26, the green color is used to denote
50
3.7 Advanced Dual-Gate Structures
the MIM capacitor formed by the layers gate metal and metal1 . Along with the basic
ADG device in Fig. 3.35, four alterations of said structure were investigated. Table 3.4
gives an overview of the designed and fabricated ADG devices. To simplify the comTable 3.4: Designed 8 × 75 µm structures ADG 1 to ADG 5. ADG 1 = basic structure
according Fig. 3.35. ADG 2 to ADG 4 = gate bus G2 as electrode of the MIM
capacitor CRF . ADG 5 = identical to ADG 1, but without the ohmic metal
strip between the gates.
Device
ADG 1
ADG 2
ADG 3
ADG 4
ADG 5
OHM
3.7 µm
w/o
SH
w/o
w/o
w/o
1.3 µm
w/o
Gate bus G2 implementation
Gate metal (GATE)
Gate metal + metal1 (GATE + MET1)
GATE + MET1, source connected
GATE + MET1, source connected
Gate metal (GATE)
ing discussion, the five different advanced dual-gate structures are named from ADG 1
throughout to ADG 5. All devices have dimensions of 8 × 75 µm. ADG 1 corresponds
to the basic ADG structure in Fig. 3.35, the detail areas of the four structures ADG 2
to ADG 5 are shown in Fig. 3.36. ADG 1 to ADG 3 differ in the way, the gate bus of
(a) ADG 2: gate bus G2 (b) ADG 3: source con- (c) ADG 4: source con- (d) ADG 5: ohmic metal
as capacitor electrode.
nected GND electrode. nected field plate.
omitted.
Figure 3.36: Detail extracts of ADG 2 to ADG 5. ADG 2 to ADG 4 = gate bus G2 as
electrode of the MIM capacitor CRF . ADG 5 = identical to ADG 1, but
without the ohmic metal strip between the gates.
the CG device (G2 ) is implemented. In ADG 1, the gate bus G2 is implemented in
gate metal and directly connected to one electrode of the capacitor. ADG 2 to ADG 4
additionally use a metal1 layer on top of the gate bus G2 to form a MIM capacitor,
i.e. the capacitor CRF is partially implemented in the gate bus. ADG 3 is identical
to ADG 2, but with source connected capacitor GND electrode on the gate bus G2 via
metal bridges. ADG 4 additionally has a source connected field plate or shield (SH)
with a length of 1.3 µm for the CS device. ADG 5 is identical to ADG 1, but without
the ohmic metal strip between the drain of the CS and the source of the CG device.
51
Chapter 3 Power HEMT Structures for Broadband Applications
A photograph of a manufactured ADG 1 HEMT with GATE + MET1 MIM capacitor
is shown in Fig. 3.37(a). Fig. 3.37(b) shows the photograph of an ADG 3 HEMT with
gate bus G2 MIM capacitor and source connected capacitor GND electrode.
(a) ADG 1 HEMT with GATE + MET1 capacitor.
(b) ADG 3 HEMT with gate bus capacitor
and source connected GND electrode.
Figure 3.37: Photographs of two variants of
GATE + MET1 MIM capacitor CRF .
8 × 75 µm
ADG
HEMTs
with
3.7.2 Advanced Dual-Gate Results
In the following, the performance of the five different advanced dual-gate structures is
compared regarding gain, output power, PAE, and stability in terms of Section 3.6.2,
i.e. the frequency, where the magnitude of S22 exceeds unity. First, the two simplest
structures ADG 1 and ADG 5 are compared. The only difference between these two devices is, that ADG 1 has an ohmic metal strip placed between the gates, whereas ADG 5
does not. Fig. 3.38 shows the small and large signal comparison of the two devices. For
the power measurements, the devices were load pull matched for maximum PAE in
class-AB operation. The biasing was Vds = 30 V, Vg2 = 6 V, and Id,DC = 100 mA mm=1 .
It is obvious from Fig. 3.38(a), that the ohmic metal strip between the gates of the
CS and CG devices results in a higher gain due to a shift of the K-point towards
higher frequencies. Thereby the overall performance of the device is improved, as can
be seen in Fig. 3.38(b). Because of this result, only dual-gate devices using the ohmic
metal connection between the gates are considered in coming discussions concerning
DG HEMTs.
The impact of the source connected MIM capacitor GND electrode via metal bridges
according Fig. 3.36(b) on the stability of the DG structure can be demonstrated by
comparing the magnitude of S22 of the two structures ADG 2 and ADG 3 over frequency.
|S22 | versus frequency from 0 GHz to 25 GHz is shown in Fig. 3.39. ADG 2 does not have
source connected capacitor GND electrodes on the gate bus G2 , whereas ADG 3 does.
It is clearly recognizable, that the source connections on the capacitor GND electrode
52
w/ OHM
w/o OHM
25
Pout (W), PAE (%)
MSG, MAG (dB)
30
20
15
10
35
16
30
14
25
12
10
20
Gain
15
10
Pout
PAE
5
5
(a) MSG and MAG of ADG 1 and ADG 5.
6
4
w/ OHM
w/o OHM
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26
Frequency (GHz)
0
5
8
Gain (dB)
3.7 Advanced Dual-Gate Structures
10
15
20
25
Pin delivered (dBm)
2
30
(b) Power sweep of ADG 1 and ADG 5 at
f = 18 GHz .
Figure 3.38: Small and large signal comparison of two ADG structures with and
without ohmic metal strip between the gates (Vds = 30 V, Vg2 = 6 V, and
Id,DC = 100 mA mm=1 ).
1
|S22 |
0.9
0.8
w/o S cons
w/ S cons
0.7
0
4
8
12
16
Frequency (GHz)
20
24
Figure 3.39: |S22 | of ADG 2 and ADG 3 without and with source connected capacitor
(S cons), respectively (Vds = 30 V, Vg2 = 6 V, and Id = 100 mA mm=1 ).
improve the stability of the DG structure by shifting the point where the magnitude
of S22 exceeds unity towards higher frequencies, i.e. from ≈ 25 GHz to > 30 GHz, by
extrapolating the curves in Fig. 3.39. Therefore, in terms of stability, ADG 3 with
source connected capacitor GND electrode is favorable over the structure without the
source connection bridges (ADG 2).
Compared to ADG 3, ADG 4 additionally has a source connected field plate or shield
53
Chapter 3 Power HEMT Structures for Broadband Applications
25
w/o SH
w/ SH
Pout (W), PAE (%)
MSG, MAG (dB)
30
20
15
10
35
16
30
14
25
12
20
10
Gain
15
PAE
10
5
(a) MSG and MAG of ADG 3 and ADG 4.
4
w/o SH
w/ SH
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26
Frequency (GHz)
6
Pout
5
0
5
8
Gain (dB)
(SH) with a length of 1.3 µm for the CS device, see Fig. 3.36(c). The impact of the
shield on the performance of the DG structure is examined by comparing ADG 3 and
ADG 4. Fig. 3.40 shows the small and large signal comparison of the two devices. For
10
15
20
25
Pin delivered (dBm)
2
30
(b) Power sweep of ADG 3 and ADG 4 at
f = 18 GHz.
Figure 3.40: Small and large signal comparison of two ADG devices without and
with source connected field plate (SH) (Vds = 30 V, Vg2 = 6 V, and
Id,DC = 100 mA mm=1 ).
the power measurements, the devices were load pull matched for maximum PAE in
class-AB operation. The biasing was Vds = 30 V, Vg2 = 6 V, and Id,DC = 100 mA mm=1 .
Due to the higher K-point, the small signal gain of the device without shield is higher
for frequencies > 15 GHz as compared to the device with shield, shown in Fig. 3.40(a).
What is remarkable, on the other hand, is that for the large signal measurement at
18 GHz, the device with shield has a higher gain as compared to the device without
shield, particularly at lower input power, shown in Fig. 3.40(b). The explanation for
this behavior is found by looking at the constant output gain circles of both devices at
18 GHz in Fig. 3.41. Drawn are six circles for each device with a step size of 1 dB. The
circles in red represent the device without shield and the circles in blue the device with
shield. The green dots denote the optimum power loads, determined by load pull measurements. The gain circles of the device with shield are more fanned out as compared
to the circles of the device without shield. As a consequence, the shield version is less
prone to small signal mismatch occurring due to optimum power matching. The inner
most circles stand for the MSG of 17 dB and 15 dB, in correspondence with Fig. 3.40(a).
The gain values at the optimum power loads are 12 dB and 14 dB in correspondence
with Fig. 3.40(b). Having significantly more gain and therefore a significantly higher
PAE, especially at lower compression levels, the advanced dual-gate structure with
shield ADG 4 is superior and perfectly suited to act as active device in driver stages.
However, the structure with shield compresses stronger and reaches a slightly lower
maximum output power as compared to the device without shield. Therefore, ADG 3
54
3.7 Advanced Dual-Gate Structures
GnoSH = M SG = 17 dB
1
GSH = M SG = 15 dB
0.5
2
Γload,SH
GSH = 14 dB
Γload,noSH
GnoSH = 12 dB
0.2
0
5
0.2
0.5
1
2
5
-0.2
∞
-5
-2
-0.5
-1
Figure 3.41: Constant output gain circles and optimum output power loads at 18 GHz
of an ADG HEMT without and with shield, ADG 3 and ADG 4, respectively. Red = w/o SH, blue = w/ SH, step size = 1 dB, green = optimum
power loads.
is beneficial when the last bit of output power is required and the device is operated at
high compression levels.
In a subsequent study, a 6 × 75 µm structure of the ADG 3 type was fabricated and
compared to conventional and discrete cascode structures. Table 3.5 gives an overview
of the compared 6 × 75 µm dual-gate and cascode structures. 6 × 75 µm is a reason-
Table 3.5: Compared 6 × 75 µm HEMT structures. CAS = discrete cascode structure, DG = conventional dual-gate structure, ADG = advanced dual-gate
structure.
Device
CAS
DG
ADG
ADGsb
Dual-gate type
Discrete cascode, separate CS and CG devices
Conventional dual-gate structure
GATE + MET1, source connected
As above but with 15 µm set back CS gate-bus
55
Chapter 3 Power HEMT Structures for Broadband Applications
able device size, e.g. for the design of distributed amplifiers. The first device is a
discrete cascode (CAS), formed by the concatenation of a CS and a CG device as already shown in Fig. 3.25. The second is a conventional dual-gate structure (DG) as
shown in Fig. 3.26. The third is an advanced dual-gate structure according ADG 3 in
Fig. 3.36(b) for improved stability performance. The last structure is equivalent to the
ADG, but with an extended gap for the gate-bus of the common-source device, i.e. the
gate-bus was set back by 15 µm. This measure decreases the gate-to-source capacitance.
Fig. 3.42 shows the MSG and MAG of the investigated structures in the frequency range
from 0.1 GHz to 50 GHz. In terms of MSG and MAG, the discrete cascode structure
MSG, MAG (dB)
30
CAS
DG
ADG
ADGsb
25
20
15
10
5
0
0
10
20
30
Frequency (GHz)
40
50
Figure 3.42: Maximum stable gain and maximum available gain of the different investigated 6 × 75 µm cascode structures versus frequency from 1 GHz to 50 GHz
(Vds = 30 V, Vg2 = 6 V, and Id = 100 mA mm=1 ).
is beneficial over the other cascode structures, because it has the highest K-point and
therefore the highest gain. The ADGsb structure shows an improved gain behavior over
the standard bus gap for frequencies below the K-point. In terms of stability however,
the discrete cascode shows a much worse performance as compared to the dual-gate
devices, as can be seen in Fig. 3.43, where again the magnitude of S22 is plotted versus
frequency from 0.1 GHz to 50 GHz. For the discrete cascode, the frequency where the
magnitude of S22 exceeds unity is at ≈ 20 GHz, whereas |S22 | of the dual-gate and advaced dual-gate structures exceeds unity at ≈ 26 GHz and 30 GHz, respectively. This
shows the advantage of dual-gate structures over discrete cascode structures in general,
and the improvement of the advanced dual-gate structure over the conventional dualgate structure in particular. The large signal comparison of the discussed structures is
shown in the power sweep at a frequency of 18 GHz in Fig. 3.44. The devices were load
pull matched for maximum PAE in class-AB operation. The biasing was Vds = 30 V,
Vg2 = 6 V, and Id,DC = 100 mA mm=1 . The figure shows, that the advanced dual-gate
device also has the best power performance of all the compared structures. The ADGsb
56
3.7 Advanced Dual-Gate Structures
1.2
|S22 |
1.1
1
0.9
CAS
DG
ADG
ADGsb
0.8
0.7
0
10
20
30
Frequency (GHz)
40
50
35
18
30
16
25
14
20
12
Gain
15
Pout
10
5
PAE
0
0
5
10
CAS
DG
ADG
ADGsb
10
15
Pin delivered (dBm)
Gain (dB)
Pout (W), PAE (%)
Figure 3.43: Magnitude of S22 of the investigated cascode structures versus frequency
from 0.1 GHz to 50 GHz (Vds = 30 V, Vg2 = 6 V, and Id = 100 mA mm=1 ).
8
6
4
20
25
Figure 3.44: Power sweep at f = 18 GHz for the investigated cascode structures
(Vds = 30 V, Vg2 = 6 V, and Id,DC = 100 mA mm=1 ).
structure confirms the higher gain observed in Fig. 3.42. The high MSG of the discrete cascode, however, cannot be confirmed for large signal excitation due to a strong
compression behavior.
3.7.3 Conclusions on Dual-Gate HEMTs
Because of the high power requirement on the amplifiers in this work, active devices with
large total gate widths are required. Designing at frequencies close to or above 2/3fT of
57
Chapter 3 Power HEMT Structures for Broadband Applications
the technology makes gain a critical resource at the upper limit of the design frequency.
The cascode topology is a very attractive way to enhance the gain of an active device,
because it reduces the effective feedback capacitance of a HEMT. By combining the
two transistors of the cascode structure into one single active device, the DG transistor
is obtained. Compared to the discrete cascode circuit, the DG structure is much more
compact and thus the matching between the CS and CG device can be managed more
efficiently. In terms of stability, the dual-gate device shows an improved performance as
compared to the discrete cascode, because the magnitude of S22 of a 6 × 75 µm device
exceeds unity at ≈ 26 GHz, whereas |S22 | of the discrete cascode structure exceed unity
at ≈ 20 GHz. Discrete cascodes show a significant compression behavior and therefore
dual-gate HEMTs are also better suited for large signal operation.
By providing the RF-short as close as possible to the gate G2 , the point where S22
exceeds unity is moved to higher frequencies and therefore the stability of the device can
be improved. The minimization of the distance between the capacitance CRF and the
gate-bus of the second gate G2 in a dual-gate structure is manifested in the advanced
dual-gate structure by using the gate metal and metal1 to form a MIM capacitor.
Several versions of this basic idea have been investigated and compared. They differ in
the way, how the MIM capacitor is implemented, how the interconnection between the
CS and CG device is realized and if a source connected field plate (shield) is applied. All
fabricated versions of the advanced structures show an improvement in performance over
the conventional dual-gate structure. The magnitude of S22 of a 6 × 75 µm advanced
dual-gate device exceeds unity at ≈ 30 GHz, whereas |S22 | of the conventional dual-gate
structure exceed unity at ≈ 26 GHz. Furthermore, the ADG has ≈ 1 dB more power gain
at maximum PAE as compared to the conventional DG structure. Due to improved
gain capabilities combined with a lower obtainable output power, the shielded ADG
structure is beneficial for driver stages operated at low compression.
This section treated the basic properties of dual-gate transistors and showed results of
manufactured devices in a variety of different geometries. In order to make optimum use
of dual-gate HEMTs for broadband power amplifier design, an accurate model is needed.
However, the modeling of dual-gate structures is difficult due to the RF interaction
which occurs between the individual gate fingers. The next chapter discusses a method
to accurately model dual-gate GaN HEMT structures using a distributed modeling
approach.
58
Chapter 4
GaN Dual-Gate HEMT Characterization
and Modeling
The concept of combining the cascode connection of a common-source and a commongate HEMT into a single dual-gate device was introduced in the previous chapter, where
the basic properties of dual-gate transistors and results of manufactured devices in a
variety of different geometries were discussed. The cascode topology reduces the Miller
effect and therefore increases the MSG and MAG of an amplifier. Compared to the
discrete cascode circuit, the DG structure is much more compact and thus simplifies
circuit design. In order to understand the behavior of dual-gate structures and to
make optimum use for amplifier design, an accurate model is needed. Because of the
presence of RF interaction such as coupling between the fingers of the two transistors,
this is a tedious task. In this chapter, a method to describe the extrinsic and intrinsic
parts of the dual-gate structure separated from each other using a distributed modeling
approach is demonstrated up to the Ku band. The proposed modeling approach is the
first of its kind to accurately describe dual-gate transistors and was published within
the frame of this work in [125].
4.1 Layout and Realization of Dual-Gate HEMTs
This section focuses on the realization of dual-gate HEMTs for high power amplifier
MMICs up to 20 GHz. Reasonable devices for such MMICs have 250 nm gate length
and dimensions of 8 × 100 µm and 6 × 50 µm to 6 × 125 µm. A DG HEMT consists
of a HEMT in common-source configuration, cascode-connected to a HEMT in CG
configuration, where the former acts as a current controlling device. The schematic
representation of the dual-gate topology was shown in Fig. 3.24. Fig. 4.1 shows the
small signal equivalent circuit of a dual-gate HEMT. Rmet represents the metalization
resistance of the interconnection between the drain of the CS device and the source
of the DG device. The DC biasing of the CG device is done via a resistor Rbias of
200 Ω. The capacitor CRF has a value of 2.1 pF and provides an RF-short. Due to
its cascode nature, the dual-gate topology is often referred to as cascode cell in the
59
Chapter 4 GaN Dual-Gate HEMT Characterization and Modeling
Cds,g
gds,g
Cgd,s Rgd,s
Gate
Rmet
Drain
+
vi,s
−
Cgs,s
gm,s vi,s
Ri,s
Ri,g
gds,s Cds,s
Source
+
vi,g
−
gm,g vi,g
Rgd,g
Cgs,g
Cgd,g
CRF Rstab
Rbias
DC bias, CG
Figure 4.1: Equivalent small signal circuit of a dual-gate HEMT.
literature. A photograph of an eight-finger dual-gate device is shown in Fig. 4.2(a).
The gate fingers have a length of 250 nm and a UGW of 100 µm. In order to reduce the
CRF /2
D2
CRF /2
2 × Rstab
G2
G2
D1 /S2
D2
S1
Via
G1
Via
Detail
S1
G1
(a) 8 × 100 µm dual-gate HEMT.
(b) Detail of the DG area.
Figure 4.2: Chip photograph of an 8 × 100 µm dual-gate HEMT with stabilization resistor and RF-capacitor with enlarged dual-gate region.
extrinsic parasitics, an ohmic metal area is placed between the gates and thereby forms
the interconnection between the CS and the CG device as indicated in Fig. 4.2(b). A
reasonable biasing of the dual-gate structure under LS operation yields higher draingate voltages (Vdg ) at the DG device as compared to the CS device, i.e. the structure
is operated asymmetrically. Therefore, the gate-to-drain separation at the CG device is
larger as compared to the CS device. A typical biasing at Vds = 30 V, Vgs,CS = =2.2 V
and Vgs,CG = 6 V results in Vdg,CG = 24 V and Vdg,CS = 10.6 V.
60
4.2 Distributed Dual-Gate HEMT Model
4.2 Distributed Dual-Gate HEMT Model
The intrinsic and extrinsic circuit parameters of a FET can be extracted by performing
S-parameter measurements at various bias conditions for different device geometries.
After determination of the extrinsic parasitic elements, the intrinsic (i.e. 8-term) parameters are obtained by direct solving the equations for the Y -parameters, e.g. [6, 27].
In a dual-gate device, however, the extrinsic circuit parameters are more tedious to be
extracted due to the presence of RF interaction between the gate fingers of the two transistors. To counter this problem, a distributed dual-gate model was developed. A major
advantage of this approach is, that it helps in understanding the individual coupling
mechanisms inside the dual-gate structure. By cutting the dual-gate HEMT structure
in Fig. 4.2(a) in equidistant slices across the gates, one obtains a slice-model as shown
in Fig. 4.3. The purpose of this distributed approach is to model the passive, extrinsic
CRF /2
Via
CLnF
CL2
G1
CL1
Gate
bus
Passive
slice 1
QnF
Q2
Q1
Active
slice 1
Via
CLnF
CL2
CL1
Passive
slice 2
QnF
Q2
Q1
Active
slice 2
CRF /2
CLnF
CL2
D2
CL1
Passive
slice nS
Drain
bus
Bias G2
Rbias
Figure 4.3: Simplified block diagram of the dual-gate slice model for a total number of
nF gate fingers and nS slices.
part of the dual-gate structure separated from the active, intrinsic part. Therefore,
each individual slice has to be divided into an active and a passive slice. An active slice
consists of multiple cascode-connected intrinsic scalable SS HEMT models, i.e., one for
each individual gate finger. A simplified small signal model for one finger is shown in
Fig. 4.4. The intrinsic parameters were extracted by measuring common-source single
gate devices and applying a procedure similar to [6]. The passive slices are described by
frequency-domain analytical distributed coupled-line (CL) models included in the ADS
design environment. The capacitor CRF is modeled using a parallel-plate approach.
The gate and drain buses are modeled by separate slices. The obtained number of
61
Chapter 4 GaN Dual-Gate HEMT Characterization and Modeling
G2
G1
Intrinsic HEMT
Cgd
Intrinsic HEMT
Cgd
+
vi
−
+
vi
Cgs
−
vi gm
Ri
Cgs
vi gm
Ri
gds
Cds
S1
D2
gds
Cds
D1 /S2
Figure 4.4: Simplified equivalent circuit of a GaN dual-gate FET.
slices (nS) for a specific UGW is given by nS = UGW/SW, where SW is the width
of a single slice. The SW chosen in this work is 10 µm for the 8 × 100 µm device. A
finer resolution did not improve the accuracy of the model. The overall validity of the
model is demonstrated in Fig. 4.5 for an 8 × 100 µm device. The most critical small
signal modeling parameters, namely the MAG/MSG, Rollet factor (K), the magnitude
of S22 and phase of S12 , are shown. The device was biased at Vds = 30 V, Vg1 = =2.2 V,
2
20
1
15
10
5
120
meas
sim
100
1.5
80
60
1
40
20
0
0
0.5
0
5
10
15
20
Frequency (GHz)
(a) MSG/MAG, Rollet factor.
25
arg(S12) (deg)
25
2
mag(S22)
30
MSG, MAG (dB)
3
meas
sim
Stability factor K
35
0
0
5
10
15
20
Frequency (GHz)
25
(b) |S22 | and arg(S12 ).
Figure 4.5: Measured and modeled critical small signal parameters of an 8 × 100 µm
device in the 0.1 GHz to 25 GHz range (Vds = 30 V, Vg1 = =2.2 V, Vg2 = 6 V,
and Id = 100 mA mm=1 ).
Vg2 = 6 V, and Id = 100 mA mm=1 . Good agreement between measured and modeled
S-parameters over the entire frequency range from 0.1 GHz to 25 GHz is achieved, also
for the critical stable region around 10 GHz.
62
4.3 Large Signal Model
4.2.1 Stability Considerations
A major draw-back in dual-gate devices is their potential instability. The reason for
the instability was deduced in section 3.6.2 by means of the intrinsic small signal equivalent circuit of a HEMT with floating source. The instability manifests itself in the
form of the magnitude of S22 , which exceeds unity at a certain frequency, shown in
Fig. 3.28. Because of this behavior, it is essential to precisely describe |S22 |, among K
and arg(S12 ), in order to perform accurate stability analyses. Using the slice model for
the 8 × 100 µm device as described in Section 4.1, it was found, that adding a resistor
Rstab of 5 Ω in series with CRF prevents |S22 | from exceeding unity. This stabilization effect is demonstrated in Fig. 4.6 on an 8 × 100 µm device in the frequency range 0.1 GHz
to 30 GHz. The location of the stability resistor in the dual-gate cell is indicated in
1.2
no Rstab
Rstab = 5 Ω
1.1
|S22 |
1
0.9
0.8
0.7
0.6
0
5
10
15
20
Frequency (GHz)
25
30
Figure 4.6: Simulation of the effect of Rstab on |S22 | for an 8 × 100 µm device.
Fig. 4.2(a). For symmetry reasons two resistors with a value of 2 × Rstab were located
at both vias. Because of the degenerating effect of Rstab on the CG device, the gain and
output power of the dual-gate structure are reduced, as will be shown in Section 4.3.
4.3 Large Signal Model
In order to describe dual-gate HEMTs under RF-power operating conditions, it is indispensable to have a nonlinear model available. Simulations using the distributed
approach described in Section 4.2 are time consuming. In advancing towards a large
signal model, it is essential to make simplifications and thereby avoid potential convergence problems. By applying the knowledge gained from the distributed model, an
extrinsic equivalent circuit consisting of lumped elements was derived with a structure
similar to the one described in [97]. The coupling effects between the CS and CG devices are described by feedback capacitances and mutual inductors. In the next step,
63
Chapter 4 GaN Dual-Gate HEMT Characterization and Modeling
the intrinsic SS cascode model from Fig. 4.4 is replaced by a scalable intrinsic large signal state-space kernel described in [91]. The state-space approach allows to construct
LS models from multibias S-parameter measurements. Such models are equivalent to
the initially used model in terms of SS behavior and therefore good candidates for our
purpose. The same LS kernel was used to model both the intrinsic CS and CG device.
The validity and scalability of the LS modeling approach is demonstrated in Fig. 4.7
for two six-finger dual-gate devices at the two gate width extrema of 50 µm and 125 µm.
The devices were biased at Vds = 30 V, Vg1 = =2.2 V, Vg2 = 6 V, and Id = 100 mA mm=1 .
30
2
25
20
1
15
10
0
5
0
3
meas
sim
2
25
20
1
15
10
Stability factor K
35
MSG, MAG (dB)
30
MSG, MAG (dB)
3
meas
sim
Stability factor K
35
0
5
0
0
5
10
15
20
Frequency (GHz)
25
0
(a) 6 × 50 µm device.
5
10
15
20
Frequency (GHz)
25
(b) 6 × 125 µm device.
Figure 4.7: Measured and modeled gain and K-factor of two 6-finger devices in
the 0.1 GHz to 25 GHz range (Vds = 30 V, Vg1 = =2.2 V, Vg2 = 6 V, and
Id = 100 mA mm=1 ).
The measured and modeled S-parameters show good agreement for both gate widths
over the entire frequency range. Again, the critical stable regions around 15 GHz and
12 GHz are precisely described. The validity of the model at large signal operation is
demonstrated on a contineous wave (CW) load pull power sweep at 16 GHz in Fig. 4.8.
The load was tuned for maximum output power. The impact of Rstab on the performance is shown for two versions (V1, V2) of the 8 × 100 µm device. Version 1 in
Fig. 4.8(a) shows an unstabilized device and version 2 in Fig. 4.8(b) shows a stabilized
device with Rstab = 5 Ω. The devices were biased at Vds = 35 V, Vg1 = =2.3 V, Vg2 = 6 V,
and Id,DC = 100 mA mm=1 . Again, the measured and modeled power sweeps show good
agreement up to the saturation region of the devices.
4.4 Dual-Gate HEMT Power Amplifier
Using the LS model described above, a single stage 14 GHz to 18 GHz, 2.5 W MSL high
power amplifier MMIC with a total gate width of 1.6 mm (two 8 × 100 µm DG devices
in parallel) was designed and realized. All the designed power amplifier MMICs within
64
4.4 Dual-Gate HEMT Power Amplifier
40
Pout
35
Pout (dBm), Gain (dB)
Pout (dBm), Gain (dB)
40
30
25
20
15
Gain
10
meas
sim
5
0
5
35
Pout
30
25
20
15
10
Gain
meas
sim
5
0
10
15
20
25
Pin delivered (dBm)
(a) V1, no Rstab .
30
5
10
15
20
25
Pin delivered (dBm)
30
(b) V2, Rstab = 5 Ω.
Figure 4.8: Measured and modeled power sweeps of V1 and V2 of an 8 × 100 µm
device. (Vds = 35 V, Vg1 = =2.3 V, Vg2 = 6 V, and Id,DC = 100 mA mm=1 ,
f = 16 GHz)
the
the
the
the
scope of this work are presented in chapter 5. However, in order to demonstrate
suitability of the developed dual-gate models for MMIC design, the discussion of
above mentioned dual-gate PA is held here. Fig. 4.9 shows a chip photograph of
designed and manufactured HPA MMIC. The DC bias is fed to both transistors
Figure 4.9: Photograph of the MSL single-stage Ku band high power cascode amplifier
MMIC (2.75 × 2.25 mm2 ).
65
Chapter 4 GaN Dual-Gate HEMT Characterization and Modeling
symmetrically to the outer sides of the gate buses of G2 via 200 Ω resistors. The inner
sides of the gate buses are connected by a short transmission line in order to suppress
odd-mode oscillations. Besides the stabilization resistor Rstab = 5 Ω mentioned above,
an RC high-pass filter was placed at the input of the amplifier in order to achieve
unconditional stability. The simulated and measured small signal parameters of the
amplifier are shown in Fig. 4.10. The small signal gain is an exceptionally high 10 dB at
15
Sij (dB)
S21
meas
sim
10
5
0
-5
S22
-10
S11
-15
5
10
15
Frequency (GHz)
20
25
Figure 4.10: Simulated and measured small signal parameters of the single-stage
dual-gate PA in the frequency range 14 GHz to 18 GHz (Vds = 30 V,
Vg1 = =2.4 V, Vg2 = 6 V, Id = 100 mA mm=1 ).
the upper Ku band frequency of 18 GHz, which is a direct consequence of the reduction
in Miller effect of the dual-gate topology. A power sweep of the HPA at a frequency of
16 GHz for a biasing at Vds = 35 V, Vg1 = =2.0 V, Vg2 = 8.2 V, and Id,DC = 150 mA mm=1
is shown in Fig. 4.11. The agreement between measured and modeled power sweeps
prove to be excellent up to the saturation region.
4.5 Conclusion
Using a distributed modeling approach, an efficient way to describe the extrinsic and intrinsic equivalent circuit model parameters of a dual-gate HEMT was presented. Based
on this approach, a small signal model was developed. Focus was put on the parameters
relevant for stability, namely K, |S22 | and arg(S12 ). Through introduction of a resistor
in series to the blocking capacitor at the common-gate device of the dual-gate HEMT,
an effective stabilization method was presented, which prevents |S22 | from exceeding
unity. A scalable nonlinear model was derived by introducing an intrinsic large signal
state-space kernel into the existing extrinsic dual-gate structure. The validity of the
model was demonstrated on fabricated 8 × 100 µm, 6 × 50 µm, and 6 × 125 µm dual-gate
66
4.5 Conclusion
Pout (dBm), Gain (dB)
35
30
Pout
25
20
15
10
Gain
5
meas
sim
0
10
15
20
25
Pin available (dBm)
30
Figure 4.11: Simulated and measured power sweeps of the single-stage dual-gate PA at
f = 16 GHz (Vds = 35 V, Vg1 = =2.4 V, Vg2 = 6 V, Id,DC = 100 mA mm=1 ).
HEMTs, for both small and large signal operation. A Ku band 2.5 W power amplifier
with a small signal gain of 10 dB at 18 GHz was designed and realized to illustrate the
suitability of the developed models for MMIC design.
Having discussed designed and manufactured power HEMT structures regarding their
key characteristics important for the design of broadband power amplifier MMICs in
Chapter 3 and introduced a modeling approach for dual-gate HEMT device structures
in the chapter at hand, the next chapter is dedicated to the verification of broadband
amplifier concepts on MMIC level, i.e. the monolithic broadband power amplifier design
challenge is examined from a circuitry point of view. Various broadband power amplifier
MMICs in varying architectures are demonstrated using the GaN25 and GaN10 process
technology introduced in Chapter 2.
67
Chapter 4 GaN Dual-Gate HEMT Characterization and Modeling
68
Chapter 5
Verification of Broadband Amplifier
Concepts on MMIC Level
The motivation for Chapter 3 was to find, analyze and characterize appropriate HEMT
structures suitable for the design of broadband power amplifier MMICs. The Chapter
at hand examines the monolithic broadband power amplifier design challenge from a
circuitry point of view. Specific theoretical limitations for the design of broadband circuits exist, among whom the most basic are the Kramers-Kronig relations which relate
the frequency dependent real and imaginary parts of a linear response function. The
impact of these relations on broadband circuit design are discussed in Section 5.4.1. Important figures of merit and broadband amplifier architectures are reviewed. However,
it would be out of place, to discuss the basics of power amplifier design in detail. To
gain insight into the basic design principles for power amplifiers, the reader is referred to
literature at this point [24,37,81]. A thorough study of power amplifiers with optimized
PAE for X band applications based on the IAF AlGaN/GaN HEMT process is published in [58]. The main focus of this chapter lies on the illumination of the correlation
between theoretical limitations and real world results, exemplarily shown on designed
and fabricated monolithic broadband power amplifiers with various topologies based on
the GaN25 and GaN10 technologies at 20 GHz and 40 GHz, respectively. Thereby, the
usability of the structures for broadband power amplifier design, as introduced in the
Chapters 3 and 4, is demonstrated.
5.1 Bandwidth Definitions
Bandwidth is a measure of how much spectrum a microwave system can respond to. In
literature, various definitions of bandwidth are used. In order to avoid confusion, the
most commonly used terms and definitions shall be repeated in the following.
The absolute bandwidth is defined as
Babs = fH − fL ,
(5.1)
where fH is the upper frequency and fL the lower frequency of the passband. Dividing
69
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
the absolute bandwidth by the center frequency yields the relative bandwidth
Brel =
fH − fL
Babs
=
.
fC
fC
(5.2)
The center frequency fC is defined as (fH + fL )/2 and therefore the relative bandwidth
can be rewritten as
fH − fL
Brel = 2
.
(5.3)
fH + fL
The relative bandwidth is usually used for narrowband systems. It can be expressed as
a percentage and is sometimes referred to as percent bandwidth or percentage bandwidth
B% = 100 %
fH − fL
.
fC
(5.4)
The theoretical limit to percent bandwidth is 200 %, which occurs for fL = 0. Due to
the compression that occurs mathematically with percent bandwidths above 100 %, the
ratio bandwidth is introduced. It is defined as
B=
fH
,
fL
(5.5)
and is typically presented in the form of B : 1. Hence, a percent bandwidth of 100 %
corresponds to a ratio bandwidth of 3 : 1. The ratio bandwidth is usually used for
wideband systems. A term mainly used in UWB communication systems, is the fractional bandwidth. It corresponds to the relative bandwidth in (5.2), where fH and
fL represent the upper and lower frequencies, respectively, at the =10 dB point1 . Per
definition of the Federal Communications Commission (FCC) [1], UWB is a signal with
a bandwidth larger than 500 MHz or a fractional bandwidth of larger than 20 %. In this
work, the term bandwidth will refer to ratio bandwidth according (5.5) unless stated
otherwise.
5.2 Review of Various Broadband Architectures
Recently, considerable efforts have been made in the realization of GaN solid-state
power amplifiers in the L band and X band with power added efficiencies of more than
50 %. The improvement in power added efficiency has resulted from improvements in
the AlGaN/GaN technology, e.g. by minimizing the trapping behaviour [60, 72, 112]
and novel efficiency enhancing circuit concepts such as harmonic tuning [52, 122, 123].
Compared to the narrowband power amplifier, the broadband power amplifier’s poweradded efficiency performance is considerably lower, typically below 15 %. This arises
due to the fact, that the emphasis placed on the design of such amplifiers is achieving
maximum output power over a multioctave bandwidth, which comes at the expense of
1
The =10 dB point represents the power of a signal at 10 dB lower than its peak power spectral density.
70
5.2 Review of Various Broadband Architectures
efficiency performance. A comprehensive reference on broadband microwave amplifiers
including a discussion of amplifier theory and architecture, can be found in [107]. The
following circuit techniques employed in the design of broadband amplifiers will be
discussed in this work:
• Reactively matched amplifier
• Distributed power amplifier (DPA) or traveling wave amplifier (TWA)
• Combination of the reactively matched and distributed circuit concept
The first two techniques are well-established, the latter is a novel approach and will be
discussed in detail in Section 5.9.
5.2.1 Reactively Matched Amplifiers
In the reactively matched amplifier, the active device is matched by reactive matching
networks at the input and output. Fig. 5.1 shows the schematic diagram of such an
amplifier configuration. The reactive matching approach is often used for building
ZG
Input
matching
network
ΓS Γin
Γout ΓL
Output
matching
network
ZL
Figure 5.1: Schematic diagram of a reactively matched amplifier.
MMIC amplifiers with a bandwidth of up to 3 : 1 at maximum, e.g. in EW, where
broadband HPAs are employed in the frequency range from 6 GHz to 18 GHz, e.g. for
long distance jammers. As will be discussed in Section 5.6.2, 3 : 1 is about the maximum
bandwidth, that can be achieved by reactively matched PAs at an upper band edge of
2/3fT for maximized power performance. The most popular technique to overcome the
difficulties of reactively-matching involves the concept of traveling wave amplification, as
discussed in Section 5.2.2. However, traveling wave amplifiers also have some substantial
disadvantages. Unlike the multiplicative nature of a cascade of conventional amplifiers,
gain is additive in distributed amplifiers. Therefore, they produce less gain and power
per area and have a lower power added efficiency as compared to their reactivelymatched counterparts. For that reason, using the reactively-matched amplifier topology
has still its eligibility when the required bandwidth allows its application.
5.2.2 Traveling Wave Amplifiers
In traveling wave amplifiers (TWAs), the input and output capacitances of the active
devices Cgs and Cds , respectively are absorbed in a distributed structure. Thereby,
artificial transmission lines are formed. Traveling wave amplifiers are not reactively
71
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
matched in the sense described in Section 5.2.1 and are thus not prone to the BodeFano limitations investigated in Section 3.5. In practice, the number of stages is limited
by the diminishing input signal resulting from attenuation on the input line. Means
of determining the optimal number of stages are discussed in literature, e.g. [7, 19].
Bandwidth is typically limited by impedance mismatches brought about by frequency
dependent device parasitics. Fig. 5.2 shows a simplified schematic of a conventional
TWA. The input and output capacitances of the active devices Cgs and Cds , respectively
TL
TL
TL
TL
TL
RFout
RT,d
Cds
Cgs
Cds
Cgs
Cds
Cgs
Cds
Cgs
RFin
TL
TL
TL
TL
RT,g
Figure 5.2: Simplified schematic of a traveling wave amplifier (TWA).
are indicated by dashed lines. These parasitic elements are absorbed in a distributed
structure and thereby form artificial transmission lines. Due to their distributed nature,
traveling wave amplifiers are often referred to as distributed amplifiers in the literature,
e.g. [36]. A profound discussion on distributed amplification is given in [120].
By eliminating the drain line reverse termination resistor, all the current from the
FETs is fed in the forward direction only and passes into the load. This is accomplished
by tapering the drain line. However, in order to maintain realizable transmission line
widths, the gate width of the first transistor has to be chosen larger than the one of
the subsequent stages. distributed power amplifiers using non-uniform transistor sizes
are called non-uniform distributed power amplifiers (NDPAs). The NDPA topology
increases the maximum output power and PAE of the circuit by presenting an optimized
load impedance or “Cripps load” (see Section 3.3) to each of the transistor sections.
Since the drain line impedance is decreasing rapidly, there is a limit to the number
of stages that can be employed. A more profound discussion on distributed power
amplifiers using GaN HEMTs is given in Section 5.7. Recently, several GaN HEMT
distributed amplifier MMICs using the NDPA topology have been published in the Ku
band and beyond [15, 30, 34, 53, 87]. A Ku band NDPA using dual-gate HEMTs for
enhanced gain capability is demonstrated in Section 5.7.3. Millimeter wave (mmW)
GaN power amplifier MMICs, that pushed the NDPA concept using GaN HEMTs
into the millimeter-wave regime, were demonstrated within the frame of this work
in [126, 130] and are covered in Section 5.8.
72
5.3 The Broadband Amplifier Design Problem
5.3 The Broadband Amplifier Design Problem
A broadband power amplifier is a circuit consisting of one or multiple active devices
with an arbitrary total gate width and some sort of broadband matching networks
or equalizers at the input and output of the active devices, whereas these networks
may also include some kind of power splitter and combiner, respectively. The power
amplifier design problem can be illustrated in the form of the block schematic shown
in Fig. 5.3. Ak is the complex incident wave |Ak | ∠ϕk . |Ak | is defined by TGWk , ϕk by
ΓL,1
ZG
A1
IMN
=
A2
splitter
+
equalizer
AN −1
AN
TGW1
ΓL,2
TGW2
ΓL,N −1
Γout
OMN
=
combiner
+
equalizer
ZL
TGWN −1
ΓL,N
TGWN
Figure 5.3: Illustration of the broadband power amplifier design problem.
the electrical length necessary to achieve a desired phase shift. The output matching
network (OMN) must be designed in such way, that for a given excitation |Ak | ∠ϕk the
load reflection coefficients ΓL,k (f ) correspond optimally to the individual optimum load
reflection coefficients Γopt (f, TGWk ) for all f and k, where Γopt is to be understood
as an optimum power or optimum PAE match. The output reflection coefficient Γout
is irrelevant at first. It can be taken care of later by using certain circuit topologies
such as the balanced amplifier using 90◦ hybrid couplers [58, 59]. Solving the matching
problem can be understood as optimizing the transducer power gain
GT (f ) =
4RL (f )Rq (f )
Power to load
=
,
Power available from generator
|ZL (f ) + Zq (f )|2
(5.6)
where ZL (f ) = RL (f ) + jXL (f ) is the real frequency load over the band of interest.
Zq (f ) = Rq (f ) + jXq (f ) is the Thévenin impedance2 of the equalizer as seen from the
load [76, 92]. For the output matching network, the FET acts as the generator. It
is important to note that either Rq (f ) or Xq (f ) can be arbitrarily selected, but then
the other is defined via its Hilbert transform. Were it not for this requirement, the
2
Any steady-state linear electrical network containing impedances, voltage and current sources only,
can be substituted by an equivalent voltage source in series connection with a Thévenin impedance.
73
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
equalizer impedance would simply be chosen as ZL∗ (f ), and infinite bandwidth designs
would be possible. In this sense, the requirement of the Hilbert transform can be
viewed as the fundamental limitation in the design of broadband equalizer networks.
These mentioned restrictions will be further discussed in terms of the Kramers-Kronig
relations in Section 5.4.
There are basically two possible possibilities to design an amplifier according Fig. 5.3:
ϕk = ϕk +n ,
n=1...N
and
ϕk =
6 ϕk +n ,
n=1...N
where a realization according the first condition yields a reactively-matched amplifier
and a realization according the latter condition a distributed power amplifier. A third
variant, which is a mixed form of the two approaches above is proposed in Section 5.9.
This novel amplifier architecture for multistage designs was introduced by the author as
semi-reactively-matched amplifier (SRMA) [127]. An overview of all designed MMICs
using the three different approaches is depicted in Table 5.1.
Table 5.1: Overview of the designed MMICs. Topologies: RMA = reactively-matched
amplifier, NDPA = non-uniform distributed power amplifier, SRMA = semireactively-matched amplifier. Devices: CS = common-source, DG = dualgate.
Circuit name
Units
DEC 18 GHz V1
DEC 18 GHz V2
1-Stage DG PA
2-Stage DG PA
2-Stage DG PA V2
ACADIA
DREAM
Beastie
BeastieBoy
NastyBoy
74
Tech.
–
GaN25
GaN10
Top.
–
RMA
RMA
RMA
RMA
RMA
NDPA
SRMA
NDPA
NDPA
NDPA
Dev.
–
CS
CS
DG
DG
DG
DG
CS
CS
CS
DG
CS
BW
GHz
16–20
16–20
14–18
15–18
13–18
3–16
6–20
8–42
8–42
6–37
|S21 |
dB
11
11
10 ± 1
22 ± 2
22 ± 3
10 ± 2
18 ± 4
7±1
14 ± 1
17 ± 1
Pout
dBm
34.7
34.7
34
31.9
33.5
35
36.6
27
27
32.1
Remarks
–
Shunt cap
Shunt stub
Rstab = 5 Ω
Rstab = 5 Ω
Rstab = 3 Ω
1-stage
2-stage
DG driver
CS PA
5.3 The Broadband Amplifier Design Problem
5.3.1 Design Procedure
The procedure of designing RF or microwave amplifiers as applied throughout this work
can be roughly summarized in eight steps, independent of the architecture or field of
application of the amplifier. Fig. 5.4 gives a general overview of the design flow of a
typical power amplifier. In the following, each of the individual design steps is examined
Evaluate opt.
HEMT size
1
Large signal
simulation
Find Gopt for
each HEMT
2
Stability
5
considerations
Design output 3
matching network
Design input
4
matching network
6
Layout
generation
7
Tape-out &
processing
8
Figure 5.4: General design procedure for a power amplifier.
in more detail:
1. The optimum device geometry is evaluated considering obtainable output power,
upper frequency limit, gain and hence the location of the K-point, as described
in Chapter 3
2. The optimum power load conductance Gopt is found by means of loadline considerations and load pull measurements, as discussed in Section 3.3, or using a large
signal model, if available.
3. The task of the output matching network is to provide the optimum complex load
impedance to the transistor, i.e. transform a purely resistive output impedance,
typically 50 Ω, into an impedance to obtain an optimum power or optimum PAE
match.
4. The task of the input matching network is to provide a conjugate complex match
at the input of the transistor in order to optimize the gain over the bandwidth of
the amplifier circuit.
5. In order to ensure the stability of the amplifier, a small signal stability analysis has
to be performed by using concepts such as Rollet’s stability analysis or similar [31,
77, 78]. A global-stability analysis tool using harmonic balance (HB) calculation
based procedures is proposed in [94]. In order to achieve unconditional stability
of an amplifier, it may be necessary to apply stabilization mechanisms on device
level, as shown for the dual-gate HEMTs in Section 4.2.1.
6. If large signal models are available, the complete amplifier is simulated to evaluate
the overall performance of the design such as frequency range, Pout and PAE.
75
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
7. The layout is generated using the ADS auto-layout“ function. The final lay”
R
out including the DC biasing networks and circuit labels is made in Cadence
R
Virtuoso Layout Suite, where also the process design rule check is performed.
8. In-house processing on the IAF GaN25 or GaN10 process.
For multistage designs, the input matching network (IMN) in step 4 is the OMN of the
previous stage at the same time. This obviously adds complexity, because two complex
impedances have to be matched to one another by means of an interstage matching
network (ISMN). A novel power amplifier architecture which evades the aggravated
matching aspects introduced by designing multistage reactively-matched amplifiers will
be discussed in Section 5.9. Because of possible space limitations on the chip, it might
be reasonable to start the design procedure with some layout considerations (step ),
7
after the evaluation of the device geometry took place in step .
1 Generally speaking,
the layout of designed blocks has to be reviewed constantly, in order to avoid structures
with unrealizable dimensions.
5.4 Theoretical Limitations for the Design of Equalizers
The freedom in the design of broadband equalizers or matching networks necessary to
build an amplifier as shown in Fig. 5.3 is subject to certain theoretical restrictions. This
section discusses the origin of these basic restrictions and the consequential limitations
for the design of broadband equalizers. The most basic analysis of the relationship between the frequency dependent real and imaginary parts of a linear response function
was done by H. A. Kramers and R. Kronig in the 1920ies [56, 57] and are now known
as the Kramers-Kronig relations. They showed, that there is an inescapable relation
between the real and imaginary parts of complex permittivity - if one varies with frequency then the other must do the same and the variations are not independent. This
form of response in materials is found in many circumstances that are of technical concern. Electrical circuits too show such responses. In the 1940ies, H. W. Bode deduced
an analogous connection between amplitude and phase [9], which is more informative
for circuit analysis.
5.4.1 The Kramers-Kronig Relations
The Kramers-Kronig relations connect the frequency dependent real and imaginary
parts of a causal linear response function, g(t), which describes the response of a system
at time t after being excited by a delta function at time 0. Fig. 5.5 shows a system
with impulse-response function g(t). The fundamental principle of causality, that every
physical model must respect, is expressed mathematically by
g (t) = 0
76
for
t < 0.
(5.7)
5.4 Theoretical Limitations for the Design of Equalizers
x(t)
g(t)
y(t)
Figure 5.5: Input and output signal for a system with impulse-response function g(t).
Linearity implies that the system output y(t) in response to a system input x(t) is given
by
Z
∞
x(τ )g(t − τ ) dτ.
y(t) =
(5.8)
−∞
This integral is called convolution integral. From Fourier transforming and applying
the convolution theorem follows Y (ω) = G(ω)X(ω). The input and output matching
networks of an amplifier can be regarded as systems with an impulse response function
G(ω). The derivation of the Kramers-Kronig relations requires some complex contour
integration using Cauchy’s theorem, e.g. [93]. In carrying out the integrations around a
contour it is necessary to make small detours around any poles of the function (where
the function goes off to infinity) and then determine the contributions or residues arising
from these detours, separately [39]. A rigorous proof of the Kramers-Kronig relations
can be found in [38]. A pictorial proof is given in [116].
In order to obtain physically realizable equalizer impedances, their real and imaginary
parts must be related by the Kramers-Kronig relation. This means that one of these can
be arbitrarily selected, but then the other is defined. Were it not for this requirement,
the equalizer impedance would simply be chosen as ZL∗ (f ), and infinite bandwidth
designs would be possible. In this sense, the Kramers-Kronig relations can be viewed
as the fundamental limitation in the design of broadband equalizer networks. In terms
of a quantity Z(f ) = R(f ) + jX(f ), the relations are:
Z ∞ 0
2
ω X(ω 0 )
R(ω) = P
dω 0 ,
(5.9)
π
ω 02 − ω 2
0
Z ∞
2ω
R(ω 0 )
X(ω) = − P
dω 0 .
(5.10)
π
ω 02 − ω 2
0
Here ω = 2πf and the semi-infinite integrals are obtained by using the fact that R(ω)
and X(ω) are an even or odd function of ω, respectively [17, 76]. P denotes the Cauchy
principal value, which is defined by excluding from the integration domain an infinitesimal region, that is symmetrically distributed about the singular point, ω [5]. (5.9) and
(5.10) indicate, that R(f ) and X(f ) in a matching network cannot be independently
chosen. Mathematically, the Kramers-Kronig relations are closely related to Hilbert
transforms, i.e. any one of them can be obtained by Hilbert transform from the other.
5.4.2 The Bode Gain-Phase Relation
The Kramers-Kronig relations lead to an analogous connection between amplitude and
phase. Bode deduced the corresponding relationships and gave them in a form that is
77
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
more informative for circuit analysis [9, 10]. The phase shift ϕ(ω) in radian is related
to the amplitude response A(ω) as a function of frequency by [96]:
π
ϕ(ω) =
12
dA
dµ
ωc
1
+
6π
Z
∞
−∞
! |µ|
dA dA ln coth
dµ,
−
dµ
dµ ωc
2
(5.11)
where
dA/dµ = slope of the attenuation curve in dB per octave,
µ = ln(ω/ωc ),
coth(|µ| /2) denotes the real part since it is complex for negative µ,
W = ln(coth(|µ| /2)) is the weighting function.
This result shows that the minimum phase change at any frequency ωc depends on
the gain slopes over the whole frequency range, weighted by the weighting function
W , which is plotted in Fig. 5.6. The shape of the weighting function changes in the
Weighting function W
6
5
4
3
2
1
0
0.1
1
Relative radian frequency ω/ωc (s=1 )
10
Figure 5.6: Illustration of the broadband power amplifier design problem.
slope of the attenuation characteristic close to ωc make the major contribution to phase
shift. These considerations provide a general constraint. The variation in gain will be
associated with a related change in phase. This constraint accounts for all matching
networks. All ladder networks are automatically of the minimum-phase-shift type,
since it is impossible to form an all-pass filter section from alternate series and shunt
impedances. Because equalizers are of the minimum-phase-shift type, there is always
an attenuation and therefore a respective phase shift. Once occurred, a phase shift
cannot be undone since it is not possible to build a transmission line with negative
length (causality).
78
5.5 Impedance Level Transformation for GaN Devices
5.5 Impedance Level Transformation for GaN Devices
The simplest way to connect two different characteristic impedances Z1 and Z0 is by
using a resistive matching network. Fig. 5.7(a) shows a schematic of such a network
with minimal possible loss. The minimum possible loss a in dB and the resistors R1
R1
Z2
jX1
R2
Z1
(a) Resistive matching network with minimum loss.
Z2
Z3 −jX2
jB1
−jB2
Z1
(b) Transformation circuit with positive and negative X and B.
Figure 5.7: Resistive and reactive matching networks after [67].
and R2 can be calculated as follows (Z2 > Z1 ) [67]:
p
2 Z2 − Z2 (Z2 − Z1 ) − Z1
a = 10 lg
,
Z1
p
p
R1 = Z2 (Z2 − Z1 ),
R2 = Z1 Z2 / (Z2 − Z1 ).
(5.12)
(5.13)
The bandwidth of a resistive matching network is solely limited by its power class
induced by the necessary dimensions of the resistors and thus maximum obtainable
reflection coefficient. However, the loss is intolerably high for the design of power
amplifiers. For example, in order to transform a 10 Ω impedance into a 50 Ω impedance,
a purely resistive network according Fig. 5.7(a) would have a loss of a = 12.5 dB. A
lossless transformation network is achieved by replacing R1 and R2 by the reactances
jX1 and jB1 , respectively. However, non-reflective matching for such a network would
occur at a single frequency only. A larger bandwidth can be achieved by concatenating
another two reactances to the network with opposite sign and same transformation ratio
r, as shown
√ in Fig. 5.7(b). The two transformation sections are geometrically graded,
i.e. Z3 = Z1 Z2 . If fa and fb are the lower and upper band edges, respectively, the
center frequency is
p
fc = fa fb .
(5.14)
In order to further improve the compensation of the frequency dependence, the network
in Fig. 5.7(b) can be extended by a parallel and a series resonance circuit, as shown in
Fig. 5.8. A procedure to determine the values of the reactive elements including a table
with normalized element values is given in [67].
5.5.1 Constant Q Matching
For the following discussion, it is essential, to introduce the concept of Q matching.
The quality factor Q is used for several properties. To ease some of the confusion with
79
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
jX1
jB11
Z2
−jB11
−jX2
jX22 −jX22
−jB2
jB1
Z1
Figure 5.8: Frequency compensated matching network after [67].
these Q factors, they have been assigned distinct terms [37, 84]. In Section 3.5, the
terms Qloaded and Qof load have already been defined in (3.45) and (3.46), respectively.
In a similar way to Qof load , the unloaded Q is defined for an LC series resonant circuit:
Qunloaded =
ω0 L
1
=
.
RL + RC
ω0 C (RL + RC )
(5.15)
Plotting Qof load or simply Q as constant ratio on the Smith chart will define a constant
Q curve, as illustrated in Fig. 5.9 for Q = 1. These curves are often used as guideline
1
0.5
2
Q=1
0.2
0
0.2
0.25
0.5
5
1
2
5
∞
r=4
-0.2
-5
-2
-0.5
-1
Figure 5.9: Illustration of the concept of constant Q matching.
boundaries for broadband transformations. For an n-section transformation where the
resistive line and a constant Q of the load curve bound the transformation, the relationship between the Q of the load and the resistive transformation ratio r is given by [119]
1 + Q2 =
80
√
n
r.
(5.16)
5.5 Impedance Level Transformation for GaN Devices
The equation shows that for decreasing Q, the number of sections increases and therefore the bandwidth increases. The example for Q = 1 in Fig. 5.9 shows, that with a
two-section matching network a transformation ratio of r = 4 can be achieved. Note
that Q should not be substituted with Qunloaded . Applying single Q matching by using the guideline boundaries does not yield the optimum broadband design [8]. Other
topologies, such as the Chebyshev response transformation, have a significant bandwidth advantage. For this reason, Chebyshev impedance transforming networks in
low-pass filter form will be discussed in detail in Section 5.5.2. However, single Q offers
good transformation efficiency with smaller component values and design simplicity.
This is an advantage for the design of MMICs, because complex matching networks are
not realizable in practice. A discussion on basic matching concepts can be found in
literature [37, 81, 83].
5.5.2 Chebyshev Impedance Transforming Networks of Low-Pass Filter
Form
Chebyshev impedance transforming networks consist of ladder networks formed using
series inductances and shunt capacitances, giving an impedance match between resistor
terminations of arbitrary ratio. Fig. 5.10 shows the general form of the impedance
transforming structures with g0 and gn+1 being the resistor terminations. The main
g2
gn
g0
g1
gn−1
gn+1
(a) Low-pass impedance transformation network for
g0 < gn+1 .
g2
gn
g0
g1
gn−1
gn+1
(b) Low-pass impedance transformation network for
g0 > gn+1 .
Figure 5.10: General form of low-pass impedance transforming structures with definition for normalized prototype element values.
difference between these structures and those of conventional low-pass filter structures
is that the latter have termination resistors of equal or nearly equal size at both ends.
81
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
In the case of the filters used for impedance transformation purposes, the terminating
resistors may be of radically different size. The transformation ratio is defined as
r=
gn+1
.
g0
(5.17)
70
0.8
60
0.7
Transducer loss (dB)
Transducer loss (dB)
For example, a typical GaN HEMT with 4 mm TGW has an equivalent load resistor of
≈ 11 Ω. Therefore an impedance transformation network with a transformation ratio of
r = 4.5 would be required to match the device to 50 Ω. Because of the different size of
the terminating resistors, there is a sizable reflection loss at zero frequency (DC). The
normalized frequency response of a Chebyshev filter of this type is shown in Fig. 5.11
for a transformation ratio of r = 12, a ratio bandwidth of B =3 and a maximum ripple
of αmax 0.4 dB.
50
40
30
20
10
0.6
0.5
0.4
0.3
0.1
0
0
0
0.5
1
1.5
2
Normalized radian frequency (s=1 )
2.5
(a) f response in the range 0 ≤ ω 0 ≤ 2.5.
αmax
0.2
ωa 0
0.6
0.8 ω0 0 = 1 1.2 ωb 0
Normalized radian frequency (s=1 )
(b) f response in the range ωa 0 ≤ ω 0 ≤ ωb 0 .
Figure 5.11: Normalized frequency response of an 8th order low-pass Chebyshev
impedance transforming network (r = 12, B = 3, αmax = 0.4 dB).
The transducer loss in dB is defined as
TL = −10 lg GC .
(5.18)
The corresponding definition of the transducer power gain of a 2mth order low-pass
impedance transforming network is given as [124]
GC ,in =
1
02
1 + Γ2 cos2 m arccos ω A−1
(5.19)
for the operating band ωa 0 ≤ ω 0 ≤ ωb 0 , and
1
GC ,out =
1+
82
Γ2 cosh
2
2 0
m arccosh ω A−1 (5.20)
5.5 Impedance Level Transformation for GaN Devices
for the stop band ω 0 < ωa 0 and ω 0 > ωb 0 . ωa 0 and ωb 0 are the normalized lower and
upper radian cutoff frequencies, respectively:
√
ωa 0 = 1 − A
(5.21)
and
ωb 0 =
√
1 + A,
where
1
A=
cosh
1
m
arccosh
√
2
r−1
r(1−10−0.1αmax )
(5.22)
.
(5.23)
The normalized radian frequency variable is defined as
ω0 =
where
r
ω0 =
ω
,
ω0
ωa 2 + ωb 2
.
2
(5.24)
(5.25)
From (5.24) and (5.25) follows that ω0 0 = 1, as indicated in Fig. 5.11(b). The factor m
can be calculated as


r−1
arccosh √
2 r(1−10−0.1αmax )
.
m=
(5.26)


ωa 2 +ωb 2
arccosh


ωb 2 −ωa 2
The minimum operating reflection coefficient Γ from (5.19) and (5.20) is related to the
maximally allowed ripple αmax in dB as follows:
p
Γ = 1 − 10−0.1αmax .
(5.27)
By using the definition for the return loss in (3.42), the ripple αmax of 0.4 dB in
Fig. 5.11(b) corresponds thus to a return loss of approximately 10 dB. By plotting
the positive integer m in (5.26) versus bandwidth and transformation ratio, the number 2m of reactive elements required for a certain bandwidth–impedance ratio pairing
can be determined. A contour plot for αmax = 0.4 dB is shown in Fig. 5.12. In order to
obtain a real number for m, the conditions r > 1 and
r−1
p
≥1
2 r (1 − 10−0.1αmax )
(5.28)
must be fulfilled. The element values of the normalized impedance transformation
network according Fig. 5.10 can be either obtained by look up tables [65] or arithmetic
calculations [124]. The realizable quality factors on GaN substrate typically allow filters
of maximum 6th order, i.e. m = 3. Assuming a realistic power density of 2 W mm=1 on
MMIC level yields a necessary total gate width of 5 mm to obtain a total output power
83
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
20
18
16
m=7
14
m=6
r
12
m=5
10
m=4
8
m=3
6
4
m=2
2 m=1
1
2
3
4
5
6
B
Figure 5.12: Contour plot to determine the filter order required for a certain
bandwidth-impedance ratio pairing for αmax = 0.4 dB. 2m = filter order,
r = transformation ratio of the matching network, B = ratio bandwidth,
αmax = maximum ripple.
of 10 W. According Table 3.2, Rds is around 12 Ω for such a transistor, which gives a
transformation ratio of r = 4. By consulting Fig. 5.12, the obtainable bandwidth ratio
for a 10 W monolithic GaN power amplifier is between B = 3 and B = 4, e.g. 6 GHz
to 18 GHz. Because Vds ∝ Rds and therefore inversely proportional to the impedance
transformation ratio r, GaN is clearly beneficial over other technologies such as GaAs,
because a lower filter order is required to build a matching network covering the same
bandwidth. A similar procedure to find the element values for maximally flat impedance
transforming networks can be found in [25].
5.6 Reactively Matched GaN Power Amplifier MMICs
As discussed in Section 5.2.1, TWAs have several drawbacks and therefore it is reasonable to build amplifiers using the reactively matched approach as long as the intended
operational bandwidth allows it. The limitations of the reactively matched amplifier
topology have been discussed in detail in Sections 3.5 and 5.5.2. A basic example of a
reactively matched amplifier is the dynamic evaluation circuit (DEC). Fig. 5.13 shows
the chip photographs of two versions of a DEC in GaN25 technology with a total gate
width of 600 µm. The DEC is a single stage broadband reactively matched amplifier
used to monitor the high frequency performance of the AlGaN/GaN process [131, 132].
The MMICs are fabricated in MSL technology and are operating in the frequency
84
5.6 Reactively Matched GaN Power Amplifier MMICs
(a) V1 with matching network using capacitors.
(b) V2 with matching network using shunt stubs.
Figure 5.13: Chip photographs of two versions of the broadband 18 GHz DEC
(2 × 1.5 mm2 ).
range from 16 GHz to 21 GHz, thus they have a relative bandwidth of 27 %. Both
versions have similar performance. However, they differ in the manner of the realization of the matching networks. The input and output matching networks of version 1
in Fig. 5.13(a) are realized using MIM capacitors, whereas the matching networks in
version 2 in Fig. 5.13(b) are realized using shunt stubs. By doing so, the influence of
the MIM capacitors on the frequency behavior of the circuit is eliminated which supports the purpose of the DEC, namely to monitor the active device independently of
deviations in the passive components. Because of this advantage, the DEC with shunt
stubs is placed on each wafer run to monitor the high frequency performance of the
IAF AlGaN/GaN process. Variations in the technology can lead to shifts in frequency.
To be tolerant to such shifts, the DEC is realized as a broadband amplifier. Fig. 5.14
shows the small signal wafer mapping of the DEC MMIC in the frequency range from
0.1 GHz to 26 GHz. The measurement proves the excellent homogeneity of the active
devices across a complete 3-inch wafer. Power measurements were made over a wide
bandwidth from 13 GHz–24 GHz using an on-wafer 50 Ω probe setup. The chuck was
kept at room temperature. The amplifier MMIC was nominally biased at 30 V and
100 mA mm=1 current density. Fig. 5.15(a) shows the measured frequency sweep at
Pin = 25 dBm input power. The corresponding power sweep at a frequency of 20 GHz is
shown in Fig. 5.15(b). The MMIC delivers a power of more than 32 dBm with a corresponding gain of more than 8 dB over the entire designed frequency band from 16 GHz
to 21 GHz. The circuit shows a PAE of 37 % with a corresponding saturated power
and gain of 34.7 dBm and 8 dB at 20 GHz, respectively. The measured data provide
information on the performance of the used GaN25 MMIC technology such as power
density, gain, and PAE on circuit level.
85
Sij (dB)
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
15
10
5
0
-5
-10
-15
-20
-25
-30
S11
S21
S22
0
5
10
15
Frequency (GHz)
20
25
40
Pout (dBm), Gain (dB), PAE (%)
Pout (dBm), Gain (dB), PAE (%)
Figure 5.14: Measured small signal parameters wafer mapping in the frequency range
from 0.1 GHz to 26 GHz (Vds = 30 V, Id = 100 mA mm=1 ) of 22 out of 24
cells of the 18 GHz DEC V2.
Pout
Gain
PAE
35
30
25
20
15
10
5
0
12
14
16
18
20
Frequency (GHz)
22
(a) Frequency sweep at Pin = 25 dBm.
24
40
Pout
Gain
PAE
35
30
25
20
15
10
5
0
5
10
15
20
Pin available (dBm)
25
30
(b) Power sweep at f = 20 GHz.
Figure 5.15: Measured frequency and power sweep of the 20 GHz DEC V2 (Vds = 30 V
and Id,DC = 100 mA mm=1 ).
5.6.1 Dual-Gate HEMT Reactively Matched Amplifiers
A 2.5 W single-stage dual-gate PA MMIC was presented in Section 4.4 to underline
the suitability of the developed large signal DG model for MMIC design. In order to
increase the gain of the amplifier, the design was enhanced to a dual-stage topology.
Using again the LS model described in Chapter 4, two high power amplifier MMICs
with two different total gate widths of the driver amplifiers (DAs) were designed and
realized. Both versions have the same total gate width of the PA stage of 1.6 mm.
86
5.6 Reactively Matched GaN Power Amplifier MMICs
Fig. 5.16 shows a chip photograph of the designed and manufactured HPA MMICs. The
(a) V1 with 6 × 50 µm driver stage and Rstab = 5 Ω. (b) V2 with
Rstab = 3 Ω.
8 × 75 µm
driver
stage
and
Figure 5.16: Chip photographs of the two versions of the dual-stage dual-gate power
amplifiers (4 × 2.5 mm2 and 3.5 × 2.5 mm2 ).
30
25
20
15
10
5
0
-5
-10
-15
S11
S21
S22
Sij (dB)
Sij (dB)
DC bias is fed to the gate buses of G2 via 200 Ω resistors. Version 1 uses a stabilization
resistor Rstab = 5 Ω for all dual-gate HEMTs, whereas Version 2 uses a stabilization
resistor Rstab = 3 Ω. The measured small signal parameters of the amplifiers are shown
in Fig. 5.17. As was expected, the small signal gain is around 10 dB higher as compared
5
10
15
20
Frequency (GHz)
(a) 2-Stage DG PA V1.
25
30
25
20
15
10
5
0
-5
-10
-15
S11
S21
S22
5
10
15
20
Frequency (GHz)
25
(b) 2-Stage DG PA V2.
Figure 5.17: Measured small signal parameters of the dual-stage dual-gate PAs
in the frequency range from 5 GHz to 25 GHz (Vds = 30 V, Vg2 = 6 V,
Id = 100 mA mm=1 ).
to the single-stage design. Due to the smaller stabilization resistor, the gain of version 2
is higher than the one of version 1, but on the other hand V2 is also more prone to
oscillation, as can be seen on S11 and S22 exceeding unity at around 18 GHz. A power
87
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
Pout (dBm), Gain (dB), PAE (%)
Pout (dBm), Gain (dB), PAE (%)
sweep of the HPAs at a frequency of 16 GHz for a biasing at Vds = 35 V, Vg2 = 6 V, and
Id,DC = 100 mA mm=1 is shown in Fig. 5.18. The two amplifiers V1 and V2 deliver a
35
30
25
20
15
10
Pout
Gain
PAE
5
0
10
12
14
16
18
20
Pin available (dBm)
(a) 2-Stage DG PAs V1.
22
24
35
30
25
20
15
10
Pout
Gain
PAE
5
0
10
12
14
16
18
20
Pin available (dBm)
22
24
(b) 2-Stage DG PAs V2.
Figure 5.18: Measured power sweeps of the dual-stage dual-gate PAs at f = 16 GHz
(Vds = 30 V, Vg1 = =2.4 V, Vg2 = 6 V, Id,DC = 100 mA mm=1 ).
saturated output power of 31.9 dBm and 33.5 dBm, respectively. The higher output
power of version 1 as compared to version 2 is attributed to the higher DA- to final
PA-stage total gate width ratio of V1. This relation is also manifested by the stronger
gain compression of V1. A detailed discussion on the impact of the PA/DA TGW ratio
on output power and PAE for GaN X band amplifier MMICs on the GaN25 process
can be found in [58].
5.6.2 Bandwidth Limiting Effects in Multistage Power Amplifiers
In reactively matched amplifiers, the bandwidth is limited by the input, output and
- for multistage amplifiers - interstage matching networks. Matching is necessary for
the best possible energy transfer from stage to stage. In RF-power transistors the real
part of the input impedance which is relevant for matching is of low value, decreasing
with increasing size of the device, e.g. 2 Ω for an 8 × 125 µm GaN HEMT in the GaN25
process. This impedance must be matched either to a generator or a preceding stage.
In a similar way, the output impedance of the transistor must be matched to a load or
following stage.
Fig. 5.19 shows the output reflection coefficient of a power amplifier Γout,PA broadband matched to a load Γload as a function of frequency. Since the load is purely
resistive, i.e. < {Z} 6= 0 and = {Z} = 0, Γload does not move over frequency, whereas
Γout,PA is complex, i.e. < {Z} =
6 0 and = {Z} =
6 0 and therefore travels over frequency.
In order to overcome the decrease in gain of the active devices conditioned by the operation at microwave frequencies close to fT , the use of multiple stages in broadband
88
5.6 Reactively Matched GaN Power Amplifier MMICs
1
0.5
2
Γout,PA
0.2
5
Γload
0.2
0
0.5
1
2
5
∞
f↑
-0.2
-5
-2
-0.5
-1
Figure 5.19: Illustration of output reflection coefficient traveling over frequency.
power amplifiers is mostly inevitable. However, the challenge of broadband impedance
matching gets more severe when designing amplifiers with multiple stages. In a multistage amplifier (e.g. dual-stage), the active devices of two consecutive stages have to
be matched to one another. Therefore, complex interstage impedances occur. Fig. 5.20
shows the simplified schematic of a conventional reactively-matched dual-stage power
amplifier. The input, interstage and output matching networks are denoted IMN, ISMN
Power amplifier
Driver amplifier
RFin
IMN
DA
Real, e.g. 50 Ω
ISMN
Γout,DA
Γin,PA
OMN
PA
RFout
Real, e.g. 50 Ω
Complex, = {Zint,i } =
6 0
Figure 5.20: Schematic of a conventional reactively-matched dual-stage power amplifier.
and OMN, respectively. It is obvious, that the IMN and OMN only have to match a
purely real impedance to a complex impedance Zint,i , whereas the ISMN has to match
two complex impedances with a matching condition given by
Γin,PA = Γ∗out,DA .
(5.29)
89
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
Γin,PA is the input reflection coefficient of the PA and Γout,DA is the output reflection
coefficient in the sense of the Cds,eff compensated Cripps load of the DA according (3.23).
In the Smith chart, Γin,PA and Γ∗out,DA travel in opposite directions over frequency. This
correlation is illustrated in Fig. 5.21, where increasing frequency is indicated by f ↑.
The opposed traveling directions of Γin,PA and Γ∗out,DA is a direct consequence of the
1
Γin,PA
0.5
2
Γ∗out,DA
f↑
0.2
0
0.2
0.5
1
5
2
5
∞
f↑
-5
-0.2
-2
-0.5
-1
Figure 5.21: Illustration of reflection coefficients between two consecutive stages traveling in opposite directions.
Kramers-Kronig relations, discussed in Section 5.4.1. Consequently, even if by carefully
designing the interstage matching network the two trajectories happen to be exactly
congruent, a phase mismatch would result for all but one single frequency. Therefore,
matching two complex impedances is much more cumbersome than matching a complex
impedance to a purely resistive impedance. A novel power amplifier architecture which
evades these aggravated matching aspects is presented in Section 5.9.
5.7 Distributed GaN Power Amplifier MMICs
If bandwidth ratios of B > 4 are targeted, the use of a traveling wave amplifier topology
is inevitable. For power amplifiers, typically the NDPA topology is applied, because
it increases the maximum output power by presenting an optimized load impedance
to each of the transistor sections. Furthermore, it improves the PAE of the circuit by
eliminating the drain termination resistor.
90
5.7 Distributed GaN Power Amplifier MMICs
5.7.1 The NDPA Approach for GaN Based Distributed Amplifiers
Fig. 5.22 shows a simplified schematic of the NDPA topology. G0g are the characteristic
G0,1
Cg,1
Q1
G0,2
Cg,2
Q2
G0,3
Cg,3
Q3
Cg,N
G0,N
QN
GL
RFin
G0g
G0g
G0g
G0g
GLg
Figure 5.22: Simplified schematic of the basic NDPA topology.
conductances of the gate line sections. GLg is the gate dumping load, GL is the output
load conductance of the circuit. The optimum characteristic conductances of the drain
line sections G0,1 , . . . , G0,N are given by [16]
G0,i =
i
X
Gopt,n
(5.30)
n=1
where Gopt,1 , . . . , Gopt,N are the optimum power loads of each FET Q1 , . . . , QN . The
FET output capacitances are absorbed in the artificial transmission line. The idea
behind tapering the drain line characteristic conductances G0,i is to better maintain
an optimum load for all of the FET cells. This leads to a limitation in the achievable
output power as will be discussed in Section 5.7.2. In order to meet the conditions of
equal phase velocities on the gate and drain lines, the electrical lengths ΦG,i and ΦD,i
of the corresponding artificial gate and drain line sections, respectively, must satisfy
ΦG,i = ΦD,i
∀i = 1, . . . , N.
(5.31)
The capacitors Cg,1 , . . . , Cg,N in series with the gate of each FET increase the cutoff
frequency of the gate transmission line by reducing its distributed capacitance. These
series capacitors are also tapered to ensure equal drive levels on the transistor gates. A
NiCr resistor is placed in parallel with each gate capacitor to provide a DC path for the
gate bias. A detailed discussion on the design of distributed amplifiers can be found
in [16, 30]. The challenge in designing NDPAs is to find the optimum G0,i for large
signal drive conditions over bandwidth, especially at the upper band edge. Thus the
optimum power loads Gopt,1−N of the FETs used in the design have to be determined
by carefully performing loadline and load pull simulations for all frequencies over the
bandwidth, e.g. up to 42 GHz for the mmW MMICs in Section 5.8.
Omitting the Drain Termination Resistor
As the signal travels down the gate line, each transistor is excited by the traveling
wave and transfers the signal to the drain line through its transconductance. In the
91
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
conventional TWA, the waves traveling in the reverse direction are not in phase and
any uncanceled signal is absorbed by the drain-line termination, as indicated by RT ,d
in Fig. 5.2. In order to avoid RF power being absorbed, the drain termination resistor
is omitted in the NDPA in Fig. 5.22. To maintain the RF performance of the circuit,
the first active device of the amplifier acts as drain termination, i.e. in a 50 Ω system,
< {Y22 ,Q1 } ≈ 20 mS.
5.7.2 Design Limitations for GaN Distributed Amplifiers
The limitations for the design of reactively matched amplifiers originate in the theoretical limit of compensating the reactive element of a series or parallel RC circuit described
by the Bode-Fano criterion discussed in Section 3.5 and the realizable transformation
ratio over a certain bandwidth discussed in Section 5.5. Both limitations directly impact the obtainable bandwidth of the matching networks at the input and output of the
amplifier. Since traveling wave amplifiers do not require matching networks by design,
the limitations above do not apply. However, due to the need to present an optimum
load for all of the transistor cells, distributed amplifiers are limited in power in a similar way as reactively matched amplifiers. These limitations will be investigated in this
section.
Power Limitations
As discussed above, in order to better maintain an optimum load for all of the transistor
cells in DPAs, tapering the drain line is necessary. Fig. 5.23 shows the layout of a tapered
drain line. Z0 ,1 , . . . , Z0 ,N are the characteristic impedances of the individual drain line
Z0 ,1
Q1
Z0 ,N
Z0 ,3
Z0 ,2
RFout
Q2
Q3
QN
Wl,N
Figure 5.23: Layout of the tapered drain line of an NDPA.
segments, Wl,N is the width of the N th segment. For a substrate according Fig. 5.24,
the dependence of Wl on Z0 can be calculated. A closed form approximate expression
to calculate Z0 = f (Wl ) of a microstrip line including a correction to account for the
non-zero thickness of the metalization was developed by [117] and is recited in (A.2) and
(A.3). A graph of the resulting line width as a function of the characteristic impedance
92
5.7 Distributed GaN Power Amplifier MMICs
Wl
T
h
r
GND
(a) Microstrip line cross section.
(b) GaN25 and GaN10 substrate parameters.
Parameter
Substrate thickness h
Conductor thickness T
Relative dielectric constant εr
Relative permeability µr
GaN25
100
7
9.7
1
GaN10
75
3
9.7
1
Unit
µm
µm
-
Figure 5.24: Microstrip line with substrate parameters for the GaN25 and GaN10
processes.
and a table for some chosen impedances are shown in Fig. 5.25, LineCalc 3 was used
to produce the data. For the following discussion a maximum microstrip line width of
400 µm is assumed. Line widths exceeding this limit are physically conceivable, however
not feasible for MMIC design, because they are too bulky to handle and consume too
much chip area. Therefore, according Fig. 5.25(b), the lowest characteristic impedance
achievable is around 20 Ω for both GaN technologies. By using (5.30), this limitation
can be expressed in terms of conductance as follows:
Gopt,tot =
i
X
Gopt,n < 50 mS,
(5.32)
n=1
where Gopt,tot is the sum of the optimum power load conductances of all the active
devices in a DPA. However, exploiting the full line width of 400 µm and therefore
ending up at an impedance of said 20 Ω at the RF output of the distributed amplifier,
some kind of matching network is required to transform the output impedance to the
nominal impedance of 50 Ω, which inevitably trades off bandwidth.
The upper limit for the realizable impedance is defined by the minimum allowed
width of the galvanic metal according the design rules of the process (10 µm for GaN25
and GaN10) and the maximum allowed current density for the metal stack. For
the IAF GaN process, the maximum allowed normalized average DC current density J · T in the stacked metal layers metal1 (MET1) and galvanic metal (METG)
(see Fig. 2.3 for process layer definitions) is 10 mA µm=1 . According Fig. 3.8, the
3
LineCalc is an analysis and synthesis program for calculating electrical and physical parameters of
single and coupled transmission lines embedded in ADS from Agilent Technologies.
93
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
104
GaN25
GaN10
Wl (µm)
103
102
101
100
10-1
0
20
40
60
80
Z0 (Ω)
100
120
140
(a) Line width Wl as a function of the characteristic impedance Z0 .
(b) Sample impedances and corresponding line widths.
Z0 / Ω
10
20
50
80
100
Wl / µm
GaN25 GaN10
1000
760
422
320
92
71
24
20
9
8
Figure 5.25: Microstrip line width as a function of impedance for the GaN25 and GaN10
MSL processes.
normalized output characteristics of a typical HEMT in the GaN25 process has a saturation current of Isat = 1130 mA mm=1 . In a practical circuit, such a device would
deliver a maximum current of around 1000 mA mm=1 , yielding an average DC current
of Isat /2 = 500 mA mm=1 . Therefore, the critical minimum line width for a GaN25 device operated under RF power is 50 µm per mm gate width. According Fig. 5.24(b), the
conductor thickness in the GaN10 process is approximately half the one of the GaN25
process and thus the normalized minimum line width is around 100 µm per mm gate
width. Empirical data showed, that the maximum allowed current density may be exceeded by a factor of two, yielding J · T = 20 mA µm=1 , without loss in performance
or risk of damaging the metal layers. Consequently, the minimum line width for the
GaN25 and GaN10 process would reduce to 25 µm and 50 µm per mm gate width, respectively. Table 5.2 shows a summary of the upper and lower limits for the line widths
and impedances determined above for the GaN25 and GaN10 processes for both considered maximum current densities. For the following considerations the more restrictive
94
5.7 Distributed GaN Power Amplifier MMICs
Table 5.2: Ranges of realizable line widths and characteristic impedances per mm gate
width, for GaN25 and GaN10 technologies.
GaN25
Current density
10 mA µm=1
20 mA µm=1
10 mA µm=1
20 mA µm=1
Wl
Z0
50 µm < Wl < 400 µm 21 Ω < Z0 < 64 Ω
25 µm < Wl < 400 µm 21 Ω < Z0 < 79 Ω
GaN10
100 µm < Wl < 400 µm 17 Ω < Z0 < 42 Ω
50 µm < Wl < 400 µm 17 Ω < Z0 < 58 Ω
maximum current density of 10 mA µm=1 will be used, unless stated otherwise.
The above restrictions induce limitations for the design of distributed amplifiers.
There is a trade-off between maximum output power and obtainable upper band edge,
i.e. the highest frequency in the design frequency band. The trade-off shall be illustrated
by a design example of a DPA with an upper band edge of 20 GHz and a maximum
obtainable power at this frequency. According Fig. 3.4, the maximum TGW for a
six finger transistor is 0.37 mm, i.e. a 6 × 60 µm device. According to the load pull
measurements in Table 3.2, Ropt ≈ 60 Ω mm. For the 6 × 60 µm device, this yields an
Ropt = 167 Ω. According Fig. 5.25(a), this results in a line width below 1 µm which is
not feasible because for one thing the process technology design rules do not allow such
a narrow line and for another thing it violates the current density restrictions of the
metal stack, because according Tab. 5.2, the minimum line width for a 6 × 60 µm device
must be 18 µm. This problem can be evaded by using the NDPA approach, discussed in
Section 5.7.1. By choosing the first device to be 6 × 125 µm in size, Ropt = 80 Ω, yielding
an MSL width of 24 µm according Tab. 5.25(b), which is acceptable by applying the
relaxed current density in Tab. 5.2. In this scenario, the maximum number of devices
is limited to 7 to stay below the 50 mS required by (5.32).
According (5.32), the minimum total resistance at the output of a distributed amplifier Ropt,tot = 1/Gopt,tot is restricted to
Ropt,tot > Z0 ,min .
(5.33)
Z0 ,min is the minimum realizable characteristic impedance on the specific substrate.
According Tab. 5.2, Z0 ,min ≈ 20 Ω for the used GaN technologies in order to stay below
a line width of 400 µm. With (3.19) and (5.33), (3.18) can be recited as follows:
Pout =
(Vmax − Vknee ) Imax
8
where
Vmax − Vknee
> Z0 ,min .
Imax
(5.34)
One obvious way to increase Pout is to increase Imax . This can be achieved by either
improvements in the technology or by increasing the total gate width by concatenating
multiple active devices in parallel, where the maximum TGW is limited by 5.33. The
95
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
other way to increase Pout is to increase Vmax . Here, the superiority of GaN as a widegap
semiconductor becomes evident, because high breakdown voltages can be obtained. By
keeping the current constant, i.e. keeping the TGW constant, Pout ∝ Vmax |Vknee =0 .
However, increasing Vmax leads to a flatter loadline, i.e. Ropt ∝ Vmax |Vknee =0 , as shown in
Fig. 5.26. Aiming for maximum power by keeping Ropt constant at Z0 ,min by increasing
Id (mA)
Imax
Loadline
0
0
Vmax
Vmax
Vds (V)
Figure 5.26: Flattening of the loadline by increasing Vmax .
the periphery, considering (5.34), yields the maximum obtainable output power in a
DPA:
(Vmax − Vknee )2
Pout,max =
.
(5.35)
8Z0 ,min
This means, that the maximum output power increases quadratically with Vmax , i.e.
2 |
Pout,max ∝ Vmax
Vknee =0 . Fig. 5.27 shows the output power as a function of the maximum drain-source voltage Vmax for various Z0 ,min with corresponding line widths for
the GaN25 process as a parameter. The purple curve shows, that designing a distributed amplifier for Ropt,tot = 50 Ω means a severe constraint in obtainable output
power. Therefore, for HPAs, it is reasonable to design an NDPA to drive a load with
a lower impedance with a wideband impedance transforming network that brings the
output impedance back to 50 Ω.
Conclusions on Design Limitations for Distributed Amplifiers
The power class of a distributed amplifier is defined by the used technology. A high
drain-source voltage is clearly beneficial and therefore, GaN is the preferable material
for the design of such amplifiers. GaN allows DC operating voltages of 30 V to 40 V up
to 20 GHz, whereas GaAs does not reach more than 12 V [99]. Therefore, by assuming
an identical maximum current and neglecting the knee voltage, a DPA designed in GaN
delivers 6 to 11 times the power of a comparable DPA designed in GaAs.
Similar considerations apply for reactively-matched amplifiers. By keeping the impedance transformation ratio discussed in Section 5.5.2 constant, the maximum out-
96
5.7 Distributed GaN Power Amplifier MMICs
60
Z0 ,min = 21 Ω
Z0 ,min = 25 Ω
Z0 ,min = 30 Ω
Z0 ,min = 50 Ω
Pout,max (W)
50
40
Wl = 400 µm
Wl = 308 µm
Wl = 234 µm
30
Wl = 92 µm
20
10
0
10
20
30
40
50
60
70
80
90
100
Vmax (V)
Figure 5.27: Quadratic increase of the maximum output power with increasing Vds in
a DPA for multiple minimum characteristic impedances Z0 ,min with corresponding line widths Wl for the GaN25 process (Vknee = 6 V).
put power in a reactively-matched amplifier increases quadratically with Vmax , i.e.
2 |
Pout,max ∝ Vmax
Vknee =0 .
5.7.3 Ku Band Distributed Dual-Gate HEMT Power Amplifier
The NDPA topology as described in Section 5.7.1 was used to design a power amplifier
MMIC in the 250 nm GaN technology. The MMIC is listed in Table 5.1 under ACADIA,
standing for Advanced CAscode DIstributed Amplifier. The used advanced dual-gate
HEMTs are of the type, where the capacitor CRF is partially implemented in the
gate bus of the CG device with source connected capacitor GND electrode via metal
bridges, as discussed in Section 3.7.1 and illustrated in Fig. 3.36(b). These dual-gate
structures have an enhanced stability and power performance as compared to other
cascode topologies discussed in this work. Small and large signal measurements of a
variety of 6 × 75 µm DG devices justifying this statement were shown in Figs. 3.43 and
3.44.
Due to the reduction of the feedback capacitance Cgd , cascode structures are well
suited to design traveling wave amplifiers. The design procedure is simplified, because
the drain and gate lines can be treated separately, i.e. without interaction. Furthermore,
the gain of the amplifier is increased. However, grounding inductance in the commongate HEMT can cause serious problems, and distributed amplifiers have been known to
oscillate at frequencies above the cutoff frequency of the amplifier [85].
The designed NDPA uses five dual-gate HEMTs with gate-widths of Wg = 6 × 125 µm
for Q1 and Wg = 6 × 75 µm for Q2−5 , respectively. The larger size for Q1 compared
to Q2−5 is chosen in order to fulfill (5.30) by maintaining a realizable transmission
97
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
line width for the first transistor, as discussed in Section 5.7.2. Fig. 5.28 shows the
chip photograph of the designed MMIC. By obeying (5.30), the drain line ends up
Figure 5.28: Photograph of the advanced dual-gate HEMT nonuniform distributed
power amplifier MMIC (4.5 × 2.75 mm2 ).
Sij (dB)
in an impedance somewhat lower than 50 Ω. A matching network network is used
to transform the output impedance to the nominal impedance. The measured small
signal parameters are shown in Fig. 5.29. The amplifier was designed to operate in a
15
10
5
0
-5
-10
-15
-20
-25
-30
S11
S21
S22
0
5
10
15
Frequency (GHz)
20
25
Figure 5.29: Measured small signal parameters of the dual-gate NDPA in the 0.1 to
25 GHz range (Vds = 15 V, Vg1 = =1.4 V, Vg2 = 6 V, Id = 100 mA mm=1 ).
frequency range from 5 GHz to 18 GHz, however, due to process variations, the obtained
98
5.8 Millimeter-Wave Distributed Power Amplifiers
frequency range is from 3 GHz to 16 GHz. Due to stability issues at higher drain-source
voltages, the amplifier was measured at Vds = 15 V instead of the usual 30 V. Even
at this voltage, the amplifier obtains a high gain of (10 ± 2) dB, attributed to the use
of dual-gate devices. Comparable designs using common-source HEMTs reach similar
gains by using twice the cell number, e.g. [15].
Dual-gate HEMTs with a large gate width are more prone to oscillations than smaller
devices. For that reason the large first transistor with a size of 6 × 125 µm is the most
critical device. A way to avoid this problem is to use a common-source device for the
the first transistor Q1 in the design. This approach has been successfully implemented
in the mmW dual-stage NDPA described in Section 5.8.4.
Pout (dBm), Gain (dB), PAE (%)
Pout (dBm), Gain (dB), PAE (%)
Fig. 5.30 shows a third-order polynomial curve fit to the measured frequency and
power sweep of the amplifier. Again, the MMIC was measured at a reduced drain
40
35
30
25
Pout
Gain
PAE
20
15
10
5
0
8
10
12
14
16
Frequency (GHz)
18
(a) Frequency sweep at Pin = 32 dBm.
20
40
35
30
25
Pout
Gain
PAE
20
15
10
5
0
26
28
30
32
Pin available (dBm)
34
(b) Power sweep at the upper band edge
(f = 16 GHz).
Figure 5.30: Measured frequency and power sweeps of the dual-gate NDPA
(3rd -order polynomial data fit, Vds = 20 V, Vg1 = =1.6 V, Vg2 = 8 V,
Id,DC = 100 mA mm=1 ).
voltage of 20 V to prevent instability. The obtained output power is 35 dBm up to a
frequency of 16 GHz.
5.8 Millimeter-Wave Distributed Power Amplifiers
The NDPA topology as introduced in Section 5.7.1 was used to design three power
amplifier MMICs in the 100 nm GaN technology. All three MMICs are listed in Table 5.1. The first two designs are common-source HEMT single-stage and dual-stage
configurations, respectively. The third design is a dual-stage topology which uses dualgate HEMTs in the driver stage to boost the gain of the amplifier. The simplified
99
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
schematic of the NDPA topology, which is used as a basis for all the designs is shown
in Fig. 5.22. G0g are the characteristic conductances of the gate line sections. The
optimum characteristic conductances of the drain line sections G0 , . . . , GN are given by
(5.30), the phase condition is given by (5.31). The HEMT model used for all designs is
of state-space type, where the intrinsic and extrinsic circuit parameters were extracted
by multibias small signal S-parameter and large signal measurements at various device
geometries and temperatures [6,91]. The load pull verification of the large signal model
proves to be excellent, e.g. [89].
5.8.1 Single-Stage NDPA MMIC
The designed single-stage NDPA uses five common-source HEMTs with gate-widths of
Wg = 4 × 90 µm for Q1 and Wg = 4 × 45 µm for Q2−5 , respectively. The larger size for
Q1 compared to Q2−5 is chosen in order to fulfill (5.30) by maintaining a realizable
transmission line width for the first transistor. Fig. 5.31 shows a photograph of the
fabricated MMIC. The corresponding small signal simulation and measurement results
Figure 5.31: Photograph of the single-stage NDPA (2.5 × 1.5 mm2 ).
are given in Fig. 5.32. Good agreement between the measured and simulated linear
gain magnitude |S21 | is achieved over the whole operating frequency range from 8 GHz
to 42 GHz. The input and output return losses are better than 10dB for most of the
band. The resonance at 5 GHz is caused by the shunt on-chip MIM capacitors in the
DC bias lines.
5.8.2 Dual-Stage NDPA MMIC
The small signal gain of the single-stage design is given in Fig. 5.32. Under RF-power
drive conditions, the power gain will be inevitably reduced due to the soft gain compression behavior of the GaN HEMTs and due to thermal effects based on the expected low
PAE over bandwidth. The goal for the dual-stage design is to significantly increase the
gain by simultaneously maintaining the saturation power and bandwidth of the single-
100
5.8 Millimeter-Wave Distributed Power Amplifiers
10
S21
5
meas
sim
Sij (dB)
0
S11
-5
-10
S22
-15
-20
-25
0
10
20
30
40
Frequency (GHz)
50
60
Figure 5.32: Simulated and measured small signal parameters of the single-stage NDPA
in the 0.1 to 60 GHz range (Vds = 15 V, Id = 300 mA mm=1 ).
stage design. This was achieved by properly choosing the active device geometries and a
low interstage impedance of 32 Ω. Gate widths of Wg = 4 × 90 µm and Wg = 4 × 45 µm
are used for Q1 and Q2−5 , respectively, in both stages of the NDPA. Fig. 5.33 shows
a photograph of the fabricated MMIC. The corresponding small signal simulation and
Figure 5.33: Photograph of the dual-stage NDPA (5 × 1.5 mm2 ).
measurement results are shown in Fig. 5.34. Again, good agreement between the measured and simulated |S21 | is achieved over the whole operating frequency range with
return losses better than 10 dB for most of the band. The resonance at 5 GHz caused
by the effect described above is observed again. Both amplifiers, the single and the
dual-stage, respectively, are unconditionally stable in the entire frequency range.
101
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
20
S21
meas
sim
Sij (dB)
10
0
S11
-10
S22
-20
-30
0
10
20
30
40
Frequency (GHz)
50
60
Figure 5.34: Simulated and measured small signal parameters of the dual-stage NDPA
in the 0.1 to 60 GHz range (Vds = 15 V, Id = 300 mA mm=1 ).
5.8.3 Measured Large Signal Results
Pout (dBm), Gain (dB), PAE (%)
Pout (dBm), Gain (dB), PAE (%)
Power measurements were made over a wide bandwidth from 6 GHz to 42 GHz using
an on-wafer 50 Ω probe setup. The chuck was kept at room temperature. The amplifier
MMICs were nominally biased at 15 V and 200 mA mm=1 current density. Fig. 5.35(a)
shows the measured frequency sweep of the single-stage NDPA at 23 dBm input power.
The corresponding power sweep at a frequency of 38 GHz is shown in Fig. 5.35(b). As
30
25
20
Pout
Gain
PAE
15
10
5
0
5
10
15
20 25 30 35
Frequency (GHz)
40
(a) Frequency sweep at Pin = 23 dBm.
45
30
Pout
Gain
PAE
25
20
15
10
5
0
5
10
15
20
Pin available (dBm)
25
(b) Power sweep at the upper band edge
(f = 38 GHz).
Figure 5.35: Simulated and measured frequency and power sweeps of the single-stage
NDPA (Vds = 15 V and Id,DC = 200 mA mm=1 ).
102
5.8 Millimeter-Wave Distributed Power Amplifiers
30
Pout (dBm), Gain (dB), PAE (%)
Pout (dBm), Gain (dB), PAE (%)
discussed above, the attained power gain is below 4 dB caused by gain compression of the
GaN HEMTs. The performance of the dual-stage NDPA with significantly increased
power gain is shown in Fig. 5.36 on measured and simulated frequency and power
sweeps. The MMIC delivers a power of more than 25 dBm with a corresponding gain
Pout
25
20
meas
15
sim
Gain
10
5
PAE
0
5
10
15
20 25 30 35
Frequency (GHz)
40
(a) Frequency sweep at Pin = 17 dBm.
45
30
meas
Pout
sim
25
20
15
Gain
10
5
PAE
0
4
6
8
10 12 14 16
Pin available (dBm)
18
20
(b) Power sweep at the upper band edge
(f = 42 GHz).
Figure 5.36: Simulated and measured frequency and power sweep of the dual-stage
NDPA (Vds = 15 V and Id,DC = 200 mA mm=1 ).
of more than 8 dB over the entire designed frequency band from 8 GHz to 42 GHz. The
saturated power at the upper band edge is 27 dBm (0.5 W). Good agreement between
measured and simulated frequency and power sweeps is achieved. This illustrates the
suitability of the used large signal transistor model. It proves the correct description of
the power compression using the large signal loadline based design approach over the
entire bandwidth. It is stated again that the large signal prediction proves to be correct
especially at the critical upper band edge as shown in Fig. 5.36.
5.8.4 Dual-Stage NDPA with Dual-Gate Driver Stage
In Section 3.6 and Chapter 4, the strong compression behavior of dual-gate HEMTs
when driving a power matched load was discussed. The designed NDPA MMIC in
Section 5.7.3 confirmed the problem; strongly compressed power gain data is shown
in Fig. 5.30. Therefore, DG devices are not suitable to be operated in saturation in
power amplifier stages. This section focuses on the application of dual-gate HEMTs
in the driver stage of an NDPA in order to boost the gain of the overall amplifier. As
discussed in previous sections, GaN dual-gate HEMTs are very attractive for wideband
applications due to the reduction of the Miller effect and enhanced gain capability. Beneficial effects of dual-gate devices at frequencies up to 18 GHz have been demonstrated
in Chapter 4.
103
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
Dual-Gate HEMT Layout and Realization
The conventional GaN25 dual-gate layout from Fig. 3.26 was transferred to the GaN10
process. A dual-gate HEMT consists of a HEMT in common-source configuration,
cascode-connected to a HEMT in common-gate configuration, where the former acts as
a current controlling device. The schematic representation of the dual-gate topology is
shown in Fig. 5.37(a). The DC biasing of the CG device is done via a resistor Rbias of
G2
CRF /2
CRF /2
D2
Rbias
D1 /S2
G1
Q2
Q1
S1 G
2
D2
Via
Via
Rbias
Bias G2
CRF
(a) Schematic of a dual-gate HEMT.
S1
(b)
Dual-gate
(Wg = 4 × 45 µm).
D1 /S2
G1
HEMT
structure
Figure 5.37: Schematic and photograph of a 4 × 45 µm dual-gate HEMT structure.
200 Ω. The capacitor CRF has a value of 0.5 pF and provides an RF-short. An adequate
choice of CRF is essential in order to prevent oscillations in the device. A photograph of
a four-finger dual-gate device, as used for the design of the MMIC in Fig. 5.38, is shown
in Fig. 5.37(b). The gate fingers have a length of 100 nm and a width of 45 µm each. In
order to reduce the extrinsic parasitics, an ohmic metal area is placed between the gates
and thereby forms the interconnection between the CS and the CG device (D1 /S2 ). A
reasonable biasing of the dual-gate structure under large signal operation yields higher
drain-gate voltages (Vdg ) at the CG device as compared to the CS device, i.e. the
structure is operated asymmetrically. A typical biasing at Vds = 15 V, Vgs,CS = =1.5 V
and Vgs,CG = 3 V results in Vdg,CG = 12 V and Vdg,CS = 6.4 V. The MSG of a dual-gate
HEMT with the above biasing is 15 dB at the upper target frequency of 37 GHz. This
is a 3.5 dB enhancement in gain as compared to a HEMT with the same dimensions in
common-source configuration.
MMIC Realization
The dual-stage amplifier consists of two concatenated NDPAs whereas each stage is
designed according to the topology in Fig. 5.22. The photograph of the fabricated
MMIC is shown in Fig. 5.38. Since it is cumbersome to reach unconditional stability
for dual-gate HEMTs with device sizes larger than Wg = 4 × 60 µm, Q1 in the driver
stage is chosen to be a CS device with a gate width of Wg = 4 × 90 µm. Because the first
transistor in an NDPA does not contribute much to the overall gain, this is an acceptable
104
5.8 Millimeter-Wave Distributed Power Amplifiers
Figure 5.38: Photograph of the dual-stage dual-gate NDPA (5 × 1.5 mm2 ).
measure. Q2−5 are DG devices with gate widths of Wg = 4 × 45 µm each. In the power
amplifier stage, all transistors are CS devices. Q1 has a gate width of Wg = 4 × 100 µm,
whereas Q2−5 have gate widths of Wg = 4 × 60 µm each. The challenge of designing
the power amplifier stage is to find the optimum G0,i for large signal drive conditions
over bandwidth. Thus the optimum power loads Gopt,1−N of the FETs used in the
design were determined by carefully performing loadline and load pull simulations for
all frequencies over the bandwidth to 40 GHz. The focus in designing the driver stage
is put on gain, i.e. finding the optimum G0,i to allow an operation of the dual-gate
HEMTs at a high gain by delivering an acceptable output power.
Measured Results
The small signal simulation and measurement results of the fabricated dual-stage NDPA
MMIC are given in Fig. 5.39. Good agreement between measured and simulated small
signal parameters up to a frequency of 35 GHz is achieved. The shift of |S21 | towards
lower frequencies arises out of an fT to be lower than expected for the current process
technology. Still, an |S21 | of > 16 dB over a frequency range from 6 GHz to 37 GHz with
return losses better than 10 dB for most of the band is achieved. The resonance at 3 GHz
is caused by the shunt on-chip MIM capacitors in the DC bias lines. Nevertheless, the
amplifier is unconditionally stable in the entire frequency range of operation.
Power measurements were made over a wide bandwidth from 5 GHz–40 GHz using an
on-wafer 50 Ω probe setup. The chuck was kept at room temperature. The MMIC was
nominally biased at 15 V and 300 mA mm=1 current density. All measurements were
performed in continuous wave operation. Fig. 5.40 shows the simulated and measured
frequency sweep of the amplifier at 20 dBm input power. Good agreement between measured and simulated frequency sweeps is achieved. The MMIC delivers a power of more
than 30 dBm with a corresponding gain of more than 11 dB over the entire designed
frequency band from 6 GHz to 37 GHz. The power sweeps at a frequency of 28 GHz
and at the upper band edge at 37 GHz are shown in Fig. 5.41(a) and Fig. 5.41(b), with
105
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
30
S21
Sij (dB)
20
meas
sim
10
0
S11
-10
-20
S22
-30
0
10
20
30
Frequency (GHz)
40
50
Pout (dBm), Gain (dB), PAE (%)
Figure 5.39: Simulated and measured small signal parameters of the dualstage dual-gate NDPA in the 0.1 GHz to 50 GHz range (Vds = 15 V,
Id = 300 mA mm=1 ).
35
30
Pout
25
20
PAE
15
10
Gain
meas
5
sim
0
5
10
15
20
25
Frequency (GHz)
30
35
40
Figure 5.40: Simulated and measured frequency sweep of the dual-stage NDPA at
Pin = 20 dBm (Vds = 15 V and Id,DC = 300 mA mm=1 ).
corresponding saturated powers of 32.1 dBm (1.6 W) and 31 dBm (1.3 W), respectively.
At the time of publication, this was the highest output power achieved by a distributed
amplifier at this frequency range [130]. The saturated PAE is > 10 % over the whole frequency range. With a measured saturated output power of > 1 W and a corresponding
power gain of > 11 dB over the entire frequency range, this is an enhancement of 3 dB
in power gain over the band and an increase in saturated power of 4 dB as compared
to the dual-stage NDPA previously discussed in Section 5.8.2. Thereby, the PAE is
106
Pout (dBm), Gain (dB), PAE (%)
Pout (dBm), Gain (dB), PAE (%)
5.9 Semi-Reactively-Matched Amplifier
35
30
25
20
15
10
Pout
Gain
PAE
5
0
4
6
8
10 12 14 16
Pin available (dBm)
18
(a) Power sweep at f = 28 GHz.
20
35
30
25
Pout
Gain
PAE
20
15
10
5
0
16
17
18
19
20
21
Pin available (dBm)
22
23
(b) Power sweep at the upper band edge at
f = 37 GHz.
Figure 5.41: Measured power sweeps of the dual-stage NDPA with DG driver-stage
(Vds = 15 V and Id,DC = 300 mA mm=1 ).
doubled, whereas the chip size of the initial design is maintained. This illustrates the
suitability of using dual-gate HEMT devices in the driver stage of a multistage NDPA
topology.
5.9 Semi-Reactively-Matched Amplifier
This section discusses a novel power amplifier architecture which eliminates the complex
interstage impedance induced by multistage designs and the thereby involved limitations
discussed in Section 5.6.2. The topology allows the coverage of a wider bandwidth
as compared to the conventional reactively-matched amplifier, while maintaining the
benefits of a reactively-matched power amplifier output stage.
5.9.1 Introduction of a Novel Amplifier Architecture
The idea of the semi-reactively-matched amplifier (SRMA) architecture is to eliminate
the inconvenient complex interstage impedance by introducing an active distributed
power splitter which acts as a driver stage for a reactively-matched power amplifier. The
term semi-reactively-matched“ is given due to the traveling wave amplifier character
”
of the driver stage which implies, that just half of the amplifier is reactively-matched.
The MMIC is listed in Table 5.1 under DREAM, standing for Distributed REactivelyMatched, again referring to the distributed-reactively-matched nature of the topology.
The simplified schematic of the basic semi-reactively-matched power amplifier is shown
in Fig. 5.42. Since the NDPA topology involves the concept of traveling wave amplification, the input and output capacitances of the active devices Q1 –QN are absorbed
107
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
Power amplifier
RFout
OMN
PA
Q11
IMN
PA
Q12
IMN
PA
Rodd
Dist. active power splitter
= {Zint } = 0
G0,N
G0,2
QN
G0g
G0,1
Q2
G0g
Rterm
G0,1
G0,2
Q1
Q2
G0g
G0g
G0,N
QN
G0g
G0g
Rterm
RFin
Figure 5.42: Simplified schematic of the basic semi-reactively-matched power amplifier
topology.
in a distributed structure and thereby a purely resistive interstage impedance Zint is
created, e.g. 30 Ω. The input and output matching networks of the power amplifier
IMN and OMN, respectively, transform the complex impedance of the active devices
Q11 and Q12 into a purely resistive impedance. A patent on the concept of the SRMA
was filed in Germany [128] and a patent request is pending in the U.S. [129].
5.9.2 Distributed Active Power Splitter Driver Stage
The driver stage is designed using the non-uniform distributed power amplifier topology
discussed in Section 5.7.1, where a simplified schematic of the basic NDPA topology was
shown in Fig. 5.22. G0g are the characteristic conductances of the gate line sections.
GLg is the gate dumping load, GL is the output load conductance of the circuit. This
topology increases the maximum output power by presenting an optimized output power
load conductance to each of the transistor sections. As will be discussed below, it is
beneficial to have two outputs at the driver stage. Therefore the driver stage NDPA
is realized as a distributed active power splitter, i.e. a distributed amplifier with one
input and two symmetrical outputs. The optimum characteristic conductances of the
drain line sections G0,1−N are given by (5.30), the phase condition is given by (5.31).
108
5.9 Semi-Reactively-Matched Amplifier
5.9.3 Reactively-Matched Power Amplifier Stage
In order to achieve high output powers, it is necessary to connect multiple active cells
in parallel. By doing so, the total gate width of the power amplifier is increased and
thus higher currents can be obtained. Fig. 5.43(a) shows the conventional arrangement
of two parallel connected eight-finger HEMTs. It is evident, that the distance ddrain
RFout
Drain bus
ddrain
Via
ddrain
Gate bus
RFout
Source
(a) Conventional parallel circuit of two
eight-finger HEMTs.
(b) Parallel circuit with
short drain connection.
Figure 5.43: Conventional parallel circuit of two HEMTs and arrangement with short
drain connection.
between the drains of the connected cells is rather large. However, in terms of broadband behavior, it is essential, to minimize ddrain . This can be achieved by connecting
the two HEMTs in such a way, that the drain buses are facing each other as shown in
Fig. 5.43(b). Each of the active devices Q11 and Q12 in Fig. 5.42 is realized as such a
transistor pair with facing drain buses connected via a short transmission line. This
layout offers the possibility, to place an inductance close to the drains of the active
devices in order to compensate the effective drain-source capacitance Cds,eff . Compensating Cds,eff in close proximity to the drain of an active device is an essential measure
in order to achieve broadband behavior of a matching network. Furthermore, the heat
spreading of such an arrangement is beneficial. Looking at Fig. 5.43 makes clear, that
close together drains means wide apart gates. However, since the driver stage is realized
as an amplifier with two outputs, it is possible to feed the PA stage on the flanks and
thereby dodge this problem. A 30 Ω resistor between the gates of the HEMTs in the
power amplifier stage suppresses odd-mode oscillations. All the mentioned peculiarities
of the architecture are illustrated in Fig. 5.44 on a schematic representation of the layout
of the SRMA. The two capacitors Cbias,G in the middle are realized as one “doubledeck” device. The metal1 layer forms the ground electrode, whereas the galvanic and
gate metals form the other two electrodes. Fig. 5.45 shows the schematic cross section
of a double-deck MIM capacitor. The resistor for the odd-mode suppression Rodd is
connected between port 1 and port 2 of the capacitor.
109
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
Cbias,G
Cbias,G
RFout
Combiner
&
OMN
IMN
IMN
Cbias,D
Cbias,D
OMN
OMN
Rodd
IMN
Cbias,G
Cbias,G
Φ
Φ
Φ
Φ
Φ
Φ
RT
IMN
Φ
Φ
Φ
Φ
Φ
Φ
RT
RFin
Figure 5.44: Schematic of the layout of the semi-reactively-matched amplifier.
Port 1
Rodd
METG
SiN
MET1
SiN
GATE
Port 2
Figure 5.45: Schematic cross section of a double-deck MIM capacitor with indicated
odd-mode suppression resistor Rodd .
5.9.4 Broadband High Power Semi-Reactively-Matched Amplifier MMIC
The semi-reactively-matched amplifier architecture is demonstrated on a dual-stage
high power amplifier MMIC in 250 nm AlGaN/GaN technology. A photograph of the
fabricated MMIC is shown in Fig. 5.46. As discussed above, the semi-reactively-matched
110
5.9 Semi-Reactively-Matched Amplifier
Figure 5.46: Photograph of the semi-reactively-matched dual-stage high power amplifier
MMIC, RFin is at the bottom, RFout at the top (4.5 × 4.25 mm2 ).
amplifier consists of a distributed active power splitter and a reactively-matched power
amplifier. The power splitter uses seven common-source HEMTs with gate-widths of
Wg = 8 × 100 µm for Q1 and Wg = 4 × 50 µm for Q2−3 . The larger size for Q1 compared
to Q2−3 is chosen in order to fulfill (5.30) by maintaining a realizable transmission line
width for the first transistor. The power splitter is dimensioned to yield an interstage
impedance of 30 Ω. For the power amplifier, the transistors are chosen to be two
8 × 90 µm for each Q11 and Q12 , respectively. They are of the ISV type, where each
source finger has its own via. The photograph of a manufactured 8 × 90 µm ISV HEMT
is shown in Fig. 5.47. As can be seen in Fig. 5.46, the power amplifier is fed by the active
power splitter on the flanks. This is a rather unconventional layout. However, it has
some significant advantages. It allows for a connection of the drains of each transistor
pair Q11 and Q12 via a short transmission line. Hereby it offers the possibility, to
place an inductance close to the drains of the active devices in order to compensate the
effective drain-source capacitance Cds,eff , which is beneficial for broadband matching,
as discussed above. The transmission lines of the input matching networks are of equal
111
Via
Via
Gate Via Drain
Via
Via
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
Figure 5.47: Photograph of an 8 × 90 µm ISV HEMT with RF pads.
electrical length in order to maintain the circuit symmetry.
Measured Results of the Semi-Reactively-Matched Amplifier
The small signal simulation and measurement results of the fabricated dual-stage HPA
MMIC are given in Fig. 5.48. The shift of S21 towards higher frequencies and the dis30
Sij (dB)
meas
sim
S21
20
10
0
S22
-10
S11
-20
-30
0
5
10
15
20
Frequency (GHz)
25
30
Figure 5.48: Small signal parameters of the semi-reactively-matched PA in the 0.1 GHz
to 30 GHz range (Vds = 30 V, Id = 100 mA mm=1 ).
crepancy of S22 arise from a slight deviation of the MIM capacitors from the target
value. The increase in gain above 18 GHz is conditioned by advances in the used technology with the aim of shifting the point where the Rollet stability factor reaches unity
(K-point) towards higher frequencies. These latest developments will be addressed in
future model generations. The amplifier is unconditionally stable in the entire frequency range. Power measurements were made over a wide bandwidth from 4 GHz to
22 GHz using an on-wafer 50 Ω probe setup. The chuck was kept at room temperature.
The amplifier MMIC was nominally biased at 30 V and 100 mA mm=1 current density.
Fig. 5.49 shows the measured frequency sweep of the HPA at 24 dBm input power. The
corresponding power sweep at a frequency of 20 GHz is shown in Fig. 5.50. Again,
112
Pout (dBm), Gain (dB), PAE (%)
5.9 Semi-Reactively-Matched Amplifier
40
Pout
35
30
25
meas
sim
20
15
Gain
10
5
PAE
0
4
6
8
10
12
14
16
Frequency (GHz)
18
20
22
Pout (dBm), Gain (dB), PAE (%)
Figure 5.49: Simulated and measured frequency sweep at Pin = 24 dBm (Vds = 30 V and
Id,DC = 100 mA mm=1 ).
40
35
30
25
20
15
10
Pout
Gain
PAE
5
0
10
12
14
16
18
20
Pin available (dBm)
22
24
26
Figure 5.50: Measured power sweep at the upper band edge (f = 20 GHz, Vds = 30 V
and Id,DC = 100 mA mm=1 ).
deviations above 18 GHz can be observed caused by the effect described above. The
MMIC delivers a power of more than 30 dBm with a corresponding gain of more than
8 dB over the entire designed frequency band from 6 GHz to 20 GHz. The saturated
power at the upper band edge is 36.6 dBm (4.5 W). The bandwidth ratio is the largest
ever reported for a reactively matched multistage monolithic GaN power amplifier at
the given frequency and output power, attributed to the novel amplifier architecture.
113
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
5.10 Conclusion
The analytical consideration of the Kramers-Kronig relations and the associated implications made by Bode show that theoretical limitations for the design of broadband
equalizers exist. The bandwidth limitations cannot be eluded, no matter how big the
complexity of the circuitry, i.e. even an impedance transformation network with infinite filter order n = ∞ is subject to these constraints. As a consequence, for a given
bandwidth, the achievable return loss in a broadband amplifier is limited. Bode’s version of the Kramers-Kronig relations state that if gain changes with frequency then so
must phase. Another criterion often stated in the context of broadband amplifiers is
the Bode-Fano criterion, a technology related figure, discussed in detail in Section 3.5.
The Bode-Fano criterion answers the question on how good the reactive part of a
Bode-Fano network according Fig. 3.21 can be possibly compensated over frequency
(in terms of acceptable reflection coefficient) only. It does not give any information on
the required complexity of a matching network in order to realize a certain impedance
transformation ratio over a given frequency range. The dominating limiting effect for
broadband matching network design is the transformation ratio to be achieved. Because Vds ∝ Rout , where Rout is the slope of the loadline, GaN has an advantage over
other technologies such as GaAs. An ideal approach for the design of impedance transforming networks is to use the Chebyshev filter approximation. Chebyshev filters are
broadband and have a defined ripple. Ladder networks according to the Chebyshev
filter structure fulfill the minimum phase requirement and therefore Bode’s rules apply.
A contour plot was generated, that allows to determine the filter order required for a
certain bandwidth-impedance ratio pairing with a defined maximum ripple.
In multistage reactively-matched amplifiers, the trajectories of the input reflection
coefficient of the PA and the output reflection coefficient of the DA travel in opposite directions over frequency in the Smith chart. This is a direct consequence of the KramersKronig relations. Consequently, even if by carefully designing the interstage matching
network the two trajectories happen to be exactly congruent, a phase mismatch would
result for all but one single frequency. For this reason, the interstage matching network
is the bottleneck concerning achievable bandwidth. A novel power amplifier architecture
named semi-reactively-matched amplifier (SRMA) was introduced which eliminates the
inconvenient complex interstage impedance by introducing an active distributed power
splitter which acts as a driver stage for a reactively-matched power amplifier. The designed and fabricated MMIC has a bandwidth from 6 GHz to 20 GHz with a saturated
power at the upper band edge of 36.6 dBm (4.5W). The bandwidth ratio is the largest
ever reported for a reactively matched multistage monolithic GaN power amplifier at
the given frequency and output power, attributed to the novel amplifier architecture.
If bandwidth ratios of B > 4 are targeted, the use of a traveling wave amplifier
topology is inevitable. Traveling wave amplifiers are not reactively matched and are
thus not prone to the Bode-Fano limitations. For power amplifiers, typically the NDPA
topology is applied, because by eliminating the drain line reverse termination resistor
114
5.10 Conclusion
all the current from the FETs is fed in the forward direction only and passes into the
load. This is accomplished by tapering the drain line. However, in order to maintain
realizable transmission line widths, the gate width of the first transistor has to be
chosen larger than the one of the subsequent stages. It was shown, that because the
drain line impedance is decreasing rapidly, there is a limit to the number of stages
that can be employed which is directly proportional to the maximum output power
that can be obtained. Increasing Vds by keeping the loadline impedance constant leads
to a quadratic increase in output power, which makes AlGaN/GaN superior to lower
voltage technologies such as GaAs. A number of designed and fabricated NDPAs using
common-source and dual-gate HEMTs were discussed. Because DG HEMTs suffer from
strong gain compression at high driving power levels, they are preferably applied in the
driver stage well below saturation to boost the gain of the amplifier. A 6 GHz to 37 GHz
dual-stage topology with a driver stage using dual-gate active devices was demonstrated.
By properly choosing the device geometries and a low interstage impedance of 32 Ω, an
output power higher than 1 W with a corresponding power gain of more than 11 dB was
obtained over the whole operating frequency range.
The obtained results on circuit level in the GaN25 and GaN10 technologies impressively illustrate the usability of the structures for broadband power amplifier design,
introduced in Chapter 3.
115
Chapter 5 Verification of Broadband Amplifier Concepts on MMIC Level
116
Chapter 6
Conclusion and Outlook
A recently published article in the IEEE microwave magazine is entitled “GaN takes
the lead” [12]. The fact, that vendors are now producing GaN MMICs in volume and
achieving outstanding performance, certainly prove the authors right. The superior
characteristics of gallium nitride enable PA MMICs with 3 to 5 times the output power
of GaAs alternatives or much smaller die sizes from L band through Ka band. In
addition to power amplifiers, GaN proves to be beneficial in other circuits such as
high power switches with low insertion loss up through 18 GHz [13] and low noise
amplifiers with noise figures equivalent to gallium arsenide but with much higher input
power survivability [63]. The market for GaN RF MMICs comprises commercial and
military applications, including base station, cable television infrastructure, satellite
communications and radar among others.
However, the development of GaN based transistors is ongoing. Efforts are being
undertaken to further increase the power density and to push the transition frequency
farther into the millimeter wave regime. At the IAF, the advance towards higher frequencies is pursued with the 100 nm MMIC process GaN10. An impressive example to
demonstrate the capabilities of the technology is given in this thesis in the form of a
6 GHz to 37 GHz non-uniform distributed power amplifier with an output power well
beyond 1 W over the entire frequency range. At the time of publication, this was the
highest ever reported power for a solid state amplifier at this frequency range [130].
The designed MMIC is a dual-stage topology which employs dual-gate HEMTs in the
driver stage with a measured S21 of (17 ± 1) dB, which is a significant increase of 3 dB
as compared to a driver stage using standard common-source transistors as in previous
work of the author [126]. This demonstrates the usability of dual-gate HEMTs to boost
the gain of an amplifier.
The state of the art at the beginning of this work was presented in the introduction in
Section 1.3. Some of the most important commercially available GaAs broadband PA
MMICs were depicted in Fig. 1.3. In the meantime numerous good results have been
reported in the field of broadband GaN PA MMICs by research institutions and industry
alike. Fig. 6.1 contrasts exemplary GaN broadband power amplifiers published in recent
years with the designed and manufactured MMICs in this work. The x-axis represents
117
Chapter 6 Conclusion and Outlook
8
[15]
7
[88]
[34]
5
SRMA
4
ACADIA
3
[53]
2
[66]
Gain (10 dB/div)
Pout (W)
6
[14]
this work
other work
other on IAF
2-Stage DG
NastyBoy
[87]
BeastieBoy
1
0
0
10
20
30
40
50
Frequency (GHz)
Figure 6.1: State of the art GaN based broadband PA MMICs in contrast to the designed and manufactured MMICs in this work. Center of ellipses = center
frequency and output power on the x-axis and left y-axis, respectively. Horizontal axis of ellipses = bandwidth, vertical axis = gain. Red = this work,
blue = other work, green = other work on IAF GaN25 process.
the frequency from 0 GHz to 50 GHz, whereas the left y-axis represents the output power
at the upper band edge from 0 W to 8 W. The center of the ellipses mark the center
frequency and output power on the x-axis and left y-axis, respectively. The horizontal
and vertical axis of the ellipses represent the bandwidth and gain, respectively. The
gain is scaled to 10 dB per division on the right y-axis. The circuits in this work are
depicted in red, blue are circuits in other work and green are circuits in other work
on the IAF GaN25 process. All the depicted amplifiers can basically be divided into
two groups: reactively-matched and distributed amplifiers, with the exception of the
SRMA, which is a combination of both topologies. This novel broadband amplifier
architecture comprising a distributed active power splitter to function as a driver stage
for a reactively-matched power amplifier eliminates the complex interstage impedance
induced by multistage designs and therefore allows the coverage of a wider bandwidth as
compared to the conventional reactively-matched amplifier. The concept of the semireactively-matched amplifier (SRMA) was filed as a patent in Germany [128] and a
patent request is pending in the U.S. [129]. Nastyboy is the non-uniform distributed
amplifier in GaN10 technology with dual-gate HEMTs in the driver stage mentioned
above. BeastieBoy is its counterpart with common-source HEMTs in the driver stage
and a somewhat smaller gate periphery. [15, 34, 53, 66, 87] are distributed topologies,
whereas [14] is a reactively matched Ka band PA MMIC fabricated with a 150 nm
process. Although it is not broadband in the sense as demanded in this work, it is
mentioned here because it shows a benchmark output power in the Ka band. The rather
118
high output power of [15] results from a large total periphery of 3.2 mm distributed over
10 cells combined with a potent process technology providing a high power density of
6.2 W mm=1 at 40 V drain bias on device level. The MMIC shown in green was designed
by Airbus Defense and Space in Ulm, Germany and manufactured at the IAF on the
GaN25 process [88]. It is a reactively matched three-stage HPA, which delivers an
output power of 10 W from 6.5 GHz to 15 GHz and then starts to degrade to eventually
reach an output power of 5 W at 18 GHz. A detailed overview of all designed MMICs
including their total gate width and number of stages is depicted in Table A.1.
Outlook
The MMIC designed on the GaN25 process by Airbus Defense and Space, discussed in
Fig. 6.1, is part of an ultra-wideband high power amplifier transmit module for multifunctional next-generation active electronically scanned antenna (AESA) applications.
A photograph of the demonstrator is shown in Fig. 6.2. Besides the chip set consisting
Figure 6.2: Ultra-wideband transmit module demonstrator for multi-function defense
AESA applications. Photograph courtesy of Airbus Defence and Space,
Ulm, Germany [88].
of a driver amplifier MMIC driving two HPA MMICs in a balanced configuration, the
module includes a DC part with a pulse and control circuitry.
The work of the Airbus Defense and Space group serves as a motivation to build transmit modules using designed and fabricated broadband monolithic amplifiers demon-
119
Chapter 6 Conclusion and Outlook
strated in this work. A promising candidate to be used in a transmit module is the
SRMA introduced in Section 5.9.1. Since the distributed driver stage in the SRMA
has a purely resistive impedance at the output as well as at the input, this architecture
is predestined to serve as a basis for a three-stage amplifier design. The simplified
schematic of the basic three-stage power amplifier topology with distributed interstage
is shown in Fig. 6.3. The reactively-matched amplifiers in the pre-driver and the power
Pre-driver
Interstage
DA
Power amplifier
RMA
RMA
Combiner
RFin
RFout
RMA
Real, e.g. 50 Ω
Figure 6.3: Simplified schematic of the three-stage semi-reactively-matched power amplifier topology with distributed interstage.
amplifier stages are denoted RMA, whereas the distributed interstage amplifier is denoted DA. The combiner is a passive network which combines the outputs of the two
PA stages. The two purely resistive interstage impedances are indicated in the figure by
the dashed red lines. Using three stages results in an increased gain performance, which
allows to increase the total gate width of the power amplifier and thereby increase the
output power. Such an SRMA MMIC using eight 8 × 150 µm devices in the PA stage
has been designed but not manufactured yet. Small and large signal simulations of the
designed three-stage topology are shown in Fig. 6.4. The simulations show a high small
signal gain of (28 ± 3) dB over a frequency range from 6 GHz to 18 GHz. The rather
low return losses, especially at the input can be accounted for by using a balanced
amplifier topology on module level. For 20 dBm input power, the MMIC delivers a
power of more than 10 W with a corresponding gain of more than 20 dB over the entire
designed frequency band from 6 GHz to 18 GHz. The output power peaks at the center
frequency at an impressive 20 W. This simulated data accentuate the potential of the
SRMA architecture to out-compete today’s state of the art.
120
S11
S21
S22
30
20
Sij (dB)
Pout (dBm), Gain (dB), PAE (%)
40
10
0
-10
-20
-30
0
5
10
15
20
Frequency (GHz)
25
30
(a) Small signal parameters in the 0.1 GHz to
30 GHz frequency range.
45
40
35
30
25
20
15
10
5
0
Pout
Gain
PAE
4
6
8
10 12 14 16
Frequency (GHz)
18
20
(b) Simulated frequency sweep at Pin = 20 dBm.
Figure 6.4: Simulated small and large signal performance of the designed 10 W SRMA
MMIC (Vds = 35 V and Id,DC = 100 mA mm=1 ).
121
Chapter 6 Conclusion and Outlook
122
Appendix A
A.1 Relevant Equations
A.1.1 Effective Dielectric Constant of a Microstrip Line
The effective dielectric constant of a microstrip line is given approximately by [81]
εeff =
1
εr + 1 εr − 1
p
+
.
2
2
1 + 12h/Wl
(A.1)
The effective dielectric constant can be interpreted as the dielectric constant of a homogeneous medium that equivalently replaces the air and dielectric regions of the microstrip line.
A.1.2 Characteristic Impedance of Microstrip Lines
Harold A. Wheeler formulated synthesis and analysis equations based upon a conformal mapping’s approximation of the dielectric boundary with parallel conductor strips
separated by a dielectric sheet [117].
For wide strips (W/h > 3.3):
ZF0
Z0 = √
2 εr
Weff
2h
+
1
π
ln 4 +
εr +1
2πεr
ln
πe
2
1
Weff
2h
+ 0.94 +
εr −1
2πε2r
2
π
ln e16
.
(A.2)
For narrow strips (W/h ≤ 3.3):
ZF0
Z0 = p
π 2 (εr + 1)
 
· ln 
4h
+
Weff
s
4h
Weff
2


1 εr − 1
π
1
4 
+ 2 −
ln + ln
. (A.3)
2 εr + 1
2 εr π
Weff is the effective width, which is the actual width of the strip, plus a correction to
123
Appendix A
account for the non-zero thickness of the metalization [118]:

Weff = W + t
1+
1
εr
2π


ln 
s

t 2
h
4e
+
1
π
W
t
1
+1.1




2  .

(A.4)
ZF0 is the impedance of free space:
r
ZF0 =
µ0
≈ 377 Ω,
ε0
(A.5)
where µ0 = 4π · 10−7 H m=1 and ε0 ≈ 8.854 · 10−12 F m=1 .
For wide microstrip lines, it is possible to excite a transverse resonance along the x
axis of the microstrip line below the strip in the dielectric region because the sides below
the strip conductor appear approximately as magnetic walls. This condition occurs
when the width is about λ/2 in the dielectric, but because of field fringing the effective
width of the strip is somewhat larger than the physical width. A rough approximation
for the effective width is Wl +h/2, so the approximate threshold frequency for transverse
resonance is [81]
c
ftran ≈ √
.
(A.6)
εr (2Wl + h)
However, it is rare that a microstrip line is wide enough to approach this limit in
practice.
A.2 Detailed Overview of the Designed MMICs
A detailed overview of the designed MMICs relevant for the work at hand is given in
Table 5.1. The total gate width (TGW) is expressed as number of devices × gate width,
where the devices of each stage are listed on a separate line for multistage designs. For
the non-uniform distributed power amplifiers, the first device with the larger gate width
is depicted separately. The three-stage semi-reactively-matched amplifier “DREAM
10 W” is the MMIC introduced in the outlook in Section 6, which is not processed yet.
124
NDPA
RMA
NDPA
Beastie
BeastieBoy
NastyBoy
SRMA
DREAM 10 W
GaN10
NDPA
SRMA
ACADIA
DREAM
Top.
–
RMA
RMA
RMA
RMA
RMA
Tech.
–
GaN25
2-Stage DG PA V2
Circuit name
Units
DEC 18 GHz V1
DEC 18 GHz V2
1-Stage DG PA
2-Stage DG PA
DG
CS
CS
CS
CS
DG
CS
DG
Dev.
–
CS
CS
DG
DG
2
1
2
3
1
2
2
Stg.
–
1
1
1
2
TGW
mm
1 × 0.6
1 × 0.6
2 × 0.8
1 × 0.3
2 × 0.8
1 × 0.6
2 × 0.8
0.75 + 4 × 0.45
0.8 + 6 × 0.2
4 × 0.72
1 × 1.2
1.2 + 6 × 0.36
4 × 1.2
0.36 + 4 × 0.18
0.36 + 4 × 0.18
0.36 + 4 × 0.18
0.36 + 4 × 0.18
0.4 + 4 × 0.24
6–37
8–42
8–42
6–18
3–16
6–20
13–18
BW
GHz
16–20
16–20
14–18
15–18
Pout
dBm
34.7
34.7
34
31.9
33.5
35
36.6
40
27
27
32.1
|S21 |
dB
11
11
10 ± 1
22 ± 2
22 ± 3
10 ± 2
18 ± 4
28 ± 3
7±1
14 ± 1
17 ± 1
Pub. [130]
Simulation data,
MMIC not yet
fabricated
Pub. [126]
Pub. [126]
Advanced DG
Pub. [127]
Pub. [131, 132]
Pub. [125]
Remarks
–
Table A.1: Detailed overview of all designed MMICs discussed in this work. Topologies: RMA = reactively-matched amplifier, NDPA = non-uniform distributed power amplifier, SRMA = semi-reactively-matched amplifier. Devices:
CS = common-source, DG = dual-gate.
A.2 Detailed Overview of the Designed MMICs
125
Appendix A
126
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138
Acknowledgments
This thesis is a result of my work as a research associate at the Fraunhofer Institute for
Applied Solid State Physics (IAF) in Freiburg, Germany.
First of all, my genuine gratitude goes to my advisor Professor Oliver Ambacher, for
his continuous support and for giving me the opportunity to do my doctoral thesis at
the Fraunhofer IAF in conjunction with the University of Freiburg. Moreover, I would
like to thank Professor Hermann Schumacher with the University of Ulm who agreed to
act as second reviewer. I would also like to express my deep gratitude to Dr. Michael
Schlechtweg for supporting this work in his function as head of the department RF
Circuits & Devices.
My special thank is dedicated to Dr. Rüdiger Quay for his endless encouragement,
all the valuable discussions and for reviewing my publications and especially this work.
Moreover, I am deeply grateful to Dr. Friedbert “Mastermind” van Raay for putting
tremendous amount of time and effort in mentoring my work. The various discussions
with him contributed a lot to the successful completion of this work.
Without the constant AlGaN/GaN HEMT process development, this work would
not have been possible. Therefore, I am thankful to Dr. Michael Mikulla, head of GaN
RF Power Electronics, and the staff members of the technology group, especially Dr.
Christian Haupt, Dr. Peter Brückner, Dr. Wolfgang Bronner and Dr. Patrick Waltereit
for their contributions to the IAF GaN25 and GaN10 processes.
In addition, I would like to thank my colleagues from the RF department. Stephan
Maroldt for the great time in the office, the many fruitful discussions and his assistance
in writing the thesis. Markus Musser for spending valuable time with me on Freiburg’s
nice singletrails and Fäbu for sharing the affinity for good McChrystal’s. Dr. Matthias
Seelmann-Eggebert and Dirk Schwantuschke for providing transistor models. Sandrine
Wagner for her relentless struggle for properly working software. Thomas Maier, Roger
Lozar and Detlef Peschel for the many measurements performed to support the thesis.
I also would like to acknowledge the financial support of the Federal Ministry of
Defence (BMVg) and the Federal Office of Bundeswehr Equipment, Information Technology and In-Service Support (BAAINBw).
Last but not least, I would like to express my deepest gratitude to my wife Mirjam for
her endless patience and tireless efforts to keep myself free of any obligations, especially
in the last few months.
139