“A Configurable Radiation Tolerant
Dual-Ported Static RAM macro,
designed in a 0.25 µm CMOS technology
for applications in the LHC environment.”
8th Workshop on Electronics for LHC Experiments
9-13 Sept. 2002, Colmar, France
K. Kloukinas, G. Magazzu, A. Marchioro
CERN EP division, 1211 Geneva 23, Switzerland
Overview
Motive of Work
Description of the macro-cell design
Experimental Results
Conclusions
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Motive of Work
Several Front-End ASICs for the LHC detectors
are using the CERN DSM Design Kit in 0.25 µm
commercial CMOS technology.
Many ASICs require the use of rather large
memories in Readout Pipelines, Readout
Buffers and FIFOs.
CERN DSM Design Kit lacks design automation
tools for generating customized SRAM blocks.
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Proposed Design
Built an SRAM macro-cell
that can be configured in terms of
word counts and bit organization
by means of simple floorplanning procedures.
Initially designed for the needs of
the “Kchip” Front-End ASIC used in
the CMS ECAL Preshower detector.
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CERN-SRAM specifications
Data In
Scalable Design
Configurable Bit organization (n x 9-bit).
Configurable Memory Size (128 – 4Kwords).
Write Address
Synchronous Dual-Port Operation
Permits Read/Write operations on
the same clock cycle.
Typical Operating Frequency: 40 MHz.
Full Static Operation.
Divided Wordline Decoding.
Radiation Tolerant Design
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SRAM
SRAM
RD
WR
CLK
Low Power Design
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Read Address
Data Out
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Memory Cell
RBL WBL
WBL RBL
BL
BL
WL
R_WL
W_WL
Dual Port SRAM Cell
Single Port SRAM Cell
To minimize the macro-cell area a Single Port memory cell is used
based on a conventional cross-coupled inverter scheme.
Gain in Memory Cell Layout Area = 18%
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Memory Cell Design
BL GND
BL
VDD
GND BL
M1
BL
M2
M3
8.42 µm
WL
WL
PC
Single Port memory cell
Interconnect: 3 metal layers
• 1st for local interconnects
• 2nd for vertical bitlines and power lines
• 3rd for horizontal wordlines
Memory Cell Area: 47.152 µm2
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5.60 µm
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Write Drivers
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Word-line Buffers
SRAM
Array
• Registered Inputs
• Latched Outputs
n-7
clk
Clk
R
W
Dual-port functionality is
realized with a time sharing
access mechanism.
Timing
Logic
Read Logic
Column-decoder
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Data Latch
RA
<n-1..0>
Addr. Reg.
7
Row decoder
WA
<n-1..0>
m
Addr. Reg.
Din
<m-1..0>
Data Reg.
SRAM Block Diagram
Dout
<m-1..0>
8
SRAM Interface Timing
WRITE
tS 1 tH
READ
tS 2 tH
READ/WRITE
3
4
5
Clk
WA
RA
W
R
Din
tacc
Dout
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SRAM macro-cell Design
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Address Mux Register
Leaf cell is based on the D-F/F and
the 2-input Mux standard cells
found in the CERN DSM Design Kit.
WA
D
SET
CLR
True & Complementary output with
balanced timing.
Easily sizeable by abutting the
necessary number of leaf cells.
RA
D
SET
CLR
Q
Q
Addr
AddrZ
Q
Q
Clk
Leaf Cell
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Row Decoder
WL0
¾Decoder: 7 to 128
¾Hardwire-configured.
¾Pre-routed layout block.
A6
WL1
WL2
¾Dynamic NAND-type.
¾Speed, Area, Power
advantages over the
static NAND-type.
¾Latched output.
WL3
A0
precharge
WL
evaluate
WL128
A0...A6 A0...A6
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Column Decoder
Static NAND-type implementation
Column decoding is one of the last actions to be performed
in the read sequence.
It can be executed in parallel with other functions, and can
be performed as soon as address is available.
Its propagation delay does not add to the overall memory
access time.
Size Configurable
Make use of Design kit standard cells.
Decoding function is via-hole programmable.
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Divided Wordline Decoding
Global Word-line
Local Word-line
Local Word-line
Block
Select
Block
Select
Reduced Power Consumption.
The non accessed portions of the memory remain in the
precharge state.
Improved Wordline Selection Time.
Since the RC delay in each divided wordline is small due to
its short length.
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Divided Wordline Decoding
Data In
Write Drivers
Write Drivers
Write Drivers
Write Drivers
Global Word-line
SRAM
Array
Word-line Buffers
Word-line Buffers
Row Decoder
SRAM
Array
Word-line Buffers
SRAM
Array
Word-line Buffers
Local Word-line
SRAM
Array
Address
Read Logic
Read Logic
Read Logic
Read Logic
Column Dec.
Column Dec.
Column Dec.
Column Dec.
Data Out
Block Pre-Dec.
Block Select signals
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SRAM macro-cell Design
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Data Input Output Ports
Data Input Register
Leaf cell is based on the D-F/F standard cell from
CERN DSM Design Kit.
True & Complementary output with
balanced timing.
Data Output Latch
Leaf cell is based on the Latch standard cell from
CERN DSM Design Kit.
Easily sizeable by abutting the necessary number of
leaf cells.
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SRAM Data Path
Data in
Clk
Write Drivers
Write enable
Bit Line
Bit Line
BLPC
precharge
evaluate
Word Line
precharge
evaluate
Read Logic
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Latch
Data out
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Read Logic
Substitution of the conventional sense
amplifier with an asymmetric inverter.
Reduced Power Consumption
Stable operation al low power supply voltages.
Acceptable performance for target applications.
Easy to design.
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Replica Techniques
Dummy Bit Lines
Wordline select time depends
on the size of the memory.
Dummy Wordline with replica
memory cells to track the
wordline charge-discharge
time.
Bitline Timing
128 rows
Scalability
Dummy Bitlines to mimic the
delay of the bitline path over
all conditions.
SRAM
Array
WLdummy
BL0
Dummy Word Line
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Replica Techniques
Data in
Dummy Bit Lines
WEN
Row
Decoder
BLPC
Bit Line
Bit Line
A6
Global
Word Line
A0
Local
Word Line
WLPC
Block Select
WLPC
WLdummy
LWLdummy
Dummy Word Line
BL
Latch
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BL
BL0
Data out
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Timing Logic
Data Input
Register
Address Mux
Register
Clk
SRAM
Interface
Clk
Clk
R
W
WLpc
BLpc
Timing Logic
Memory Cell WLdummy
BL0
Array
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Memory Cell
REN
Array
WEN
Latch
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Data Ouput
Latch
22
Timing Logic
Asynchronous internal timing of control signals.
Static operation.
Hand-shaking and transition detection to realize
internal timing loops.
Timing loops are initiated by the system clock and
terminated upon completion of the operation.
All control signals are forced back to their initial state
to prepare for subsequent tasks.
During standby periods, bitlines and wordlines
precharge-evaluate cycles are not initiated, thus
keeping the Power Consumption to a minimum.
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Operation and Timing
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Cell Library
Fixed Layout
Size Configurable
Data Input Register
WordLine Buffers
SRAM column, 128 x 9bits
(50.4 µm x 1086.2 µm)
Column Decoder
Block Pre-Decoder
Output Data Latche
Row Decoder
Address Mux Register
Timing logic
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Floorplanning
Column
Timing PreDecoder Address Reg
Block
Read logic Read logic Read logic Read logic
Column Decoder
DOut Latch
Read logic Read logic Read logic Read logic
DIn Reg
Write drv. Write drv. Write drv. Write drv.
Row Decoder (128 rows)
Write drv. Write drv. Write drv. Write drv.
vdd
gnd
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DIn
WA
RA
CLK
W
R
DOut
CAD Tools Support
Digital Simulation
Digital
Simulator
SRAM
verilog module
(parameterized)
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VERILOG
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CAD Tools Support
Logic Synthesis
Template
SRAM
timing
Design Kit
.lib file
compilation
Combined
.lib file
Combined
.db file
Logic Synthesis
Tool
SYNOPSYS
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CAD Tools Support
Place & Route
Template
SRAM
timing
Design Kit
TLF file
Layout
view
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compilation
Combined
TLF file
Abstract
view
Combined
CTLF file
LEF file
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Place & Route
Tool
Silicon Ensemble
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Experimental Results
To prove the concept
of the SRAM macro-cell scalability and
to evaluate the performance of the proposed
design we have fabricated two test chips:
a 1Kwords X 9bits and
a 4Kwords X 9bits.
Both chips were tested and found functional.
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Submitted SRAM Chips
1st Prototype
Design: CERN_SRAM_1K
Configuration: 1K x 9 bit
Size: ~560µm x 1,300µm
Area: ~0.73mm2
Density: ~12.6Kbit/mm2
The Memory consists of
2 Blocks of 512 x 9bits.
Each Block is composed by
4 Columns of 128 X 9bits.
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Submitted SRAM Chips
2nd Prototype
Design: CERN_SRAM_4K
Configuration: 4K x 9 bit
Size: ~1,850µm x 1,300µm
Area: ~2.4mm2
Density: ~15.4Kbit/mm2
The Memory consists of
8 Blocks of 512 x 9bits.
Each Block is composed by
4 Columns of 128 X 9bits.
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CERN SRAM test results
Test chip: 4Kx9bit
Functional tests
Max operating frequency:
Simultaneous Read/Write operations: 70MHz @ 2.5V
Read access time: 7.5ns @ 2.5V
Power dissipation:
15µW / MHz @ 2.5V for simultaneous Read/Write operations on
the same clock cycle (0.60mW @ 40MHz).
Tests for process variations:
Differences in the access time < 1ns for: -3σ, –1.5σ, typ, +1.5σ, +3σ
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Performance Tests
Test Chip: 4Kword X 9bits
Operation Frequency: 50MHz
Power Supply: 2.5Volts
Read Access Time: 7.5nsec
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Performance Tests
Schmoo Plot
All 1’s and all 0’s
Checkerboard
Marching 1’s
Marching 0’s
2.7
2.6
Power Supply Voltage (V)
Test Chip: 4Kword X 9bits
Power Supply: 2.0 - 2.7Volts
Operation Frequency: 50MHz
Test Patterns:
2.5
Pass
2.4
2.3
2.2
2.1
2
1.9
6.00
8.00
10.00
12.00
14.00
16.00
Access Time (nsec)
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Power dissipation
Power dissipation of macro-cell.
CERN SRAM 4K
1200.0
Test chip: 4Kwords x 9bits
Power Dissipation (uW)
1000.0
800.0
Standby
Idle
600.0
Read
Write
400.0
Read/Write
Power
Operation (µW/MHz)
Standby
0.10
Idle
1.90
Read
7.40
Write
10.60
Read/Write
14.05
200.0
0.0
20
30
40
50
60
70
Clock frequency (MHz)
Test Conditions
Operation
Standby
Idle
Read
Write
Read/Write
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Description
No operation, addr. & data static.
No operation, addr. & data changing in every clk cycle
checkerboard data pattern
checkerboard data pattern
checkerboard data pattern
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Irradiation Tests
Ionizing Total Dose
Test chip: 4Kwords x 9bit
Conditions
Source: X-rays.
Step Irradiation: 1Mrad, 5Mrad, 10Mrad.
Constant dose rate: 21.2 Krad/min.
Annealing: 24h @ ~25 oC.
Under bias, in Standby mode during irradiation & annealing.
Results
No increase in power dissipation.
No measurable degradation in performance.
Single Event Upset:
Under preparation
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CERN SRAM popularity !
z
ATLAS MCC chip
z
z
z
z
z
z
z
z
z
z
z
Sept 12, 2002
z
z
KLOUKINAS Kostas
Memory configuration: 128 x 153 bits
Detector: ATLAS TRT
Lab: CERN
CMS Kchip
z
z
z
Memory configuration: 256 X 9 bits
Detector: LHCb muon system
Lab: INFN Cagliary
Memory configuration: 128 x 18bit
Detector: ATLAS tracker
Lab: NEVIS Labs
ATLAS DTMROC chip
z
z
LHCb SYNC chip
z
z
Memory configuration: 16K X 9 bits
Detector: ALICE Silicon Drift Det.
Lab: INFN Torino
Memory configuration: 256 X 9 bits
Detector: ALICE Silicon Drift Det.
Lab: INFN Bologna
ATLAS SCAC chip
z
z
ALICE CARLOS chip
z
z
Memory configuration: 128 x 27bit
Detector: ATLAS PIXEL
Lab: INFN Genova
ALICE AMBRA chip
z
z
z
Memory configuration: 2K x 18 bits
128 x 18 bits
Detector: CMS Preshower
Lab: CERN
Chips submitted and tested
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Design Support
Delivery
Delivery of
of SRAM
SRAM design
design library
library
Half
Half aa day
day “design
“design course”
course” @
@ CERN
CERN
Designer
Designer configures
configures his
his macrocell
macrocell
Review
Review the
the macrocell
macrocell design
design
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Conclusions
Design Status
Design meets target specifications.
Macrocell has been successfully used in a number of ASIC designs.
Future Plans
No further development is foreseen.
Design Support
Contact Person: Kostas.Kloukinas@CERN.ch
Information on the Web
http://home.cern.ch/kkloukin
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vdd
gnd
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CLK
W
R
DOut
Read logic
WorldLine Buffers
& Block Decoders
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Read logic
Column Decoder.
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Timing PreDecoder Address Reg
RA
Block
Column
WA
DIn Reg
Write drv.
DOut Latch
Read logic
DOut Latch
Timing
Column
Address Reg
Block
Write drv.
DIn
Row Decoder (128 rows)
Row Decoder (128 rows)
Write drv.
DIn Reg
Floorplanning
DIn
WA
RA
CLK
W
R
DOut
vdd
gnd
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