International journal of advanced scientific and technical research
Available online on http://www.rspublication.com/ijst/index.html
Issue 5 volume 1, January-February 2015
ISSN 2249-9954
PERFORMANCE EVALUATION OF NEW BREED
MULTILEVEL INVERTER
Venkataramanan K#1, Shanthi B#2, Prathapkumar K#3
#1 Arunai Engineering College, Tiruvannamalai, Tamilnadu, India.
#2 CISL, Annamalai University, Annamalai Nagar, Tamilnadu, India.
#3 Arunai Engineering College, Tiruvannamalai, Tamilnadu, India.
ABSTRACT
Multilevel inverters are popularly used for high power inverters due to their high-voltage
operation, high efficiency, low switching losses, lower output harmonics and low
electromagnetic interference. In this paper symmetrical seven level inverter fed with resistive
load was investigated through various PWM strategies. The PWM strategies developed using
modified sine as carrier signal and trapezoidal as reference. For comparison purposes, same set
of PWM strategies were also developed using sine reference. The results were presented and
evalutated.Simulations were performed using MATLAB-SIMULINK.
Key words: SPWM,MSCPWM, THD, DF,VRMS
Corresponding Author: Venkataramanan K
1.INTRODUCTION
A multilevel inverter is a power electronics system and very rapidly growing area of power
electronics. The application of MLI technology is in the medium-to-high-voltage range, industrial
drives, power distribution, and power conditioning. When the number of level increases,we can
achieve good power quality, low harmonic distortion, better electromagnetic capability and lower
switching losses.The multilevel inverter not only achieves high power ratings, it can be easily
interfaced with renewable energy sources such as fuel cells and photovoltaic etc described by
Leon Tolbert and Thomas Habetler [1], [2]. Jose Rodriguez et al [3] analyzed on various
multilevel inverter topologies. Jeevananthan et al [4] proposed Inverted Sine Carrier PWM
(ISCPWM) method. Paul Chan et al [5] introduced boundary control method to control the singlephase multilevel inverters.Seyezhai and Mathur [6] analyzed the variable frequency inverted sine
PWM technique by implementing in asymmetric cascaded multilevel inverter. Sajith Ali and
Kamaraj [7] suggested three phase Z-source inverter using a novel natural sampled pulse width
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Issue 5 volume 1, January-February 2015
ISSN 2249-9954
modulation strategy. Saad Mekhilef and Mohamad Abdul Kadir [8] developed three-stage18-level
inverter design with novel vector transformation control method. Rokan Ali Ahmed et al [9]
developed the symmetrical multilevel inverter with reduced number of Switches. Youssef
Ounejjar et al [10] proposed a novel multilevel inverter which emphasis on eliminating
transformer by employing packed U cells. Jwu-Sheng Hu et al [11] examined and detected that
control of n phase VSI can be solved using Eigen space decomposition. Zixin Li et al [12]
implemented improved pulse width modulation for chopper cell oriented multi level inverter. Hui
Peng et al [13] analyzed switching-ripple voltage on the DC Link Between a modular multilevel
cascade inverter and diode rectifer. Obrad Dordevic et al [14]compared various PWM methods.
Chaithanya Deepak and Nagaraja Rao [15] analyzed about the three phase seven level cascaded
multilevel inverter using inverted sine wave pulse width modulation strategies. Danya Bersis et al
[16] presents a novel fifteen-level cascaded H-bridge inverter with various multi carrier pulse
width modulation strategies. Krishna Kumar Gupta and Shailendra Jain [17] analyzed the singlephase five-level inverter based on switched DC sources. The harmonics in the inverter output can
be reduced by using pulse width modulation. The lower order harmonics are reduced by
sinusoidal pulse width modulation while varying the modulation index. The sine carrier control
scheme was used in multilevel inverter to get maximum output voltage. The difference in pulse
width, resulting from sine wave and triangle wave with the low frequency reference sine wave in
different sections can be easily understood. For gating pulse generation, modified sine wave used
as carrier waveform.
2. NEW BREED MULTILEVEL INVERTER
The switches were the most important part of symmetrical multilevel inverter. The
conventional H bridge multilevel inverters need 2(m-1) switches to generate „m‟ levels at the
output of the inverter. To achieve most prominent output with less number of switches by
introducing a new breed multilevel inverter topology.
This new seven level inverter has five bidirectional switches S1 to S5 and four same
magnitude of DC source, and therefore it is called as a symmetrical multilevel inverter. Fig.1
shows the configuration of the new symmetrical seven level inverter.
VDC
S2
S1
VDC
S3
R Load
VDC
S4
S5
VDC
Fig 1: New Seven Level Inverter Topology
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International journal of advanced scientific and technical research
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Issue 5 volume 1, January-February 2015
ISSN 2249-9954
The seven level inverter topology produces various levels of output voltage. They are: 3VDC,
2VDC, VDC, 0,- VDC, -2VDC, -3VDC.Table 1 shows the output voltage with the corresponding
switching states of the chosen inverter.
Table 1: Switching states for seven level inverter
Output
Voltage
S1
S2
S3
S4
S5
3VDC
0
1
0
0
1
2VDC
0
0
1
0
1
VDC
0
0
0
1
1
0VDC
0
0
0
0
0
- VDC
1
1
0
0
0
-2VDC
1
0
1
0
0
-3VDC
1
0
0
1
0
3. MODULATION STRATEGIES FOR MULTILEVEL INVERTER
Various modulation strategies are available for multilevel inverters. They are generally
classified as pulse width modulation, fundamental switching and space vector strategies. Space
vector and fundamental switching strategies are very complicated for higher number of levels.
So, pulse width modulation switching strategy is preferred. This paper focuses the analysis of
modified sine carrier based PWM strategies having sinusoidal and trapezoidal references. The
amplitude and frequency modulation index is defined as,
Amplitude modulation index ma = 2 Am / (m-1)Ac
Where,
m - Number of levels at the output voltage
Am - Amplitude of reference signal
Ac - Amplitude of carrier signal
Frequency ratio mf = fc /fm
Where,
fc - Frequency of carrier signal
fm - Frequency of reference signal
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Issue 5 volume 1, January-February 2015
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3.1 Phase Disposition PWM (PDPWM) Strategy
This strategy uses (m-1) carriers with the same frequency fc and same peak-to-peak
amplitude and Ac which are disposed so that the bands they occupy are contiguous. The carrier set
is placed above and below the zero reference. Six modulation waveform having amplitude Am and
frequency fm and it is centred in the middle of the carrier set are used to sample the modified sine
carriers to generate the gating pulses. The carrier arrangement for seven level inverter using
MSCPDPWM with sine and trapezoidal references are shown in Fig 2 and 3 respectively.
Fig 2: Carrier arrangement for PDPWM strategy with sine reference (ma=0.8 and mf=20)
Fig 3: Carrier arrangement for PDPWM strategy with Trapezoidal reference
(ma=0.8 and mf=20)
3.2 Phase Opposition Disposition PWM (PODPWM) Strategy
In this strategy, the set of (m-1) carriers were placed above the zero reference and the other
set of carriers placed below the zero reference. The two groups are opposite in phase with each
other while keeping in phase within the group. The carrier arrangement for seven level inverter
using PODPWM with sine and trapezoidal references are shown in Fig 4 and 5 respectively.
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Issue 5 volume 1, January-February 2015
ISSN 2249-9954
Fig 4: Carrier arrangement for PODPWM strategy with sine reference (ma=0.8 and mf=20)
Fig 5: Carrier arrangement for PODPWM strategy with Trapezoidal reference
(ma=0.8 and mf=20)
3.3 Alternate Phase Opposition Disposition PWM (APODPWM) Strategy
In the APODPWM, each modified sine carriers are phase shifted by 180 degrees with the
previous one. The carrier arrangement for seven level inverter using APODPWM with sine and
trapezoidal references are shown in Fig 6 and 7 respectively.
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International journal of advanced scientific and technical research
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Issue 5 volume 1, January-February 2015
ISSN 2249-9954
Fig 6: Carrier arrangement for APODPWM strategy with sine reference (ma=0.8 and mf=20)
Fig 7: Carrier arrangement for APODPWM strategy with Trapezoidal reference
(ma=0.8 and mf=20)
4. SIMULATION RESULTS
The new symmetrical single phase seven level inverter is modeled using MATLAB /
SIMULINK. The switching signals for seven level inverter using PWM Strategies having sine
and trapezoidal references were simulated. Fig 8-19 shows the simulated output voltage and
their corresponding FFT plot with strategies PDPWM, PODPWM and APODPWM having
sine and trapezoidal references for modulation index 0.8. Simlations were executed for
different values of modulation indices and the corresponding %THD, VRMS were measured and
tabulated in table 2 and 3 respectively. % DF for the chosen strategies were calculated and
tabulated in Table 4. Fig 20 & 21 shows graphical comparison of % THD in all strategies for
both references. Fig 22 & 23 shows graphical comparison of VRMS for sine and trapezoidal
respectively. It is observed from FFT plot that 20th order harmonic energy is dominant in
PDPWM strategies. 3rd order harmonic is dominant in all the strategies except PDPWM
strategy having sine reference. The following parameter values are used for MATLAB
simulation: Resistive load = 100ohms, VDC = 100V.
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Issue 5 volume 1, January-February 2015
ISSN 2249-9954
Fig 8: Output voltage generated by PDPWM strategy for Sine reference
Fig 9: FFT plot for output voltage of PDPWM strategy with Sine reference
Fig 10: Output voltage generated by PODPWM strategy for Sine reference
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Issue 5 volume 1, January-February 2015
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Fig 11: FFT plot for output voltage of PODPWM strategy with Sine reference
Fig 12: Output voltage generated by APODPWM strategy for Sine reference
Fig 13: FFT plot for output voltage of APODPWM Strategy with Sine reference
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Issue 5 volume 1, January-February 2015
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Fig 14: Output voltage generated by PDPWM Strategy for Trapezoidal reference
Fig 15: FFT plot for output voltage of PDPWM strategy with Trapezoidal reference
Fig 16: Output voltage generated by PODPWM Strategy for Trapezoidal reference
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Fig 17: FFT plot for output voltage of PODPWM strategy with Trapezoidal reference
Fig 18: Output voltage generated by APODPWM Strategy for Trapezoidal reference
Fig 19: FFT plot for output voltage of APODPWM strategy with Trapezoidal reference
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TABLE 2: % THD comparison for different Modulation Strategy
PDPWM
Sine
Trapezoidal
18.4
12.9
PODPWM
Sine
Trapezoidal
18.8
13.1
APODPWM
Sine
Trapezoidal
21.1
13.4
0.95
20.8
18.9
21.5
20.7
23.4
22.2
0.9
22.6
21.5
24
22.4
24.1
24.5
0.85
23.6
23.6
23.9
23
23.8
25.6
0.8
24.3
24.6
23.3
24.3
23.5
25.75
0.75
24.6
24.8
22.8
24.5
23
25
0.7
27
24.3
29.7
22
24.4
22.7
ma
1
TABLE 3: VRMS comparison for different modulation Strategy
PDPWM
Sine
Trapezoidal
212
232
PODPWM
Sine
Trapezoidal
200
223
APODPWM
Sine
Trapezoidal
204
229
0.95
201
217
189
203
193
209
0.9
190
208
177
194
185
198
0.85
181
199
171
186
177
189
0.8
173
188
160
176
169
181
0.75
162
177
153
165
161
173
0.7
148
166
137
156
149
165
ma
1
TABLE 4: % Distortion Factor for different modulation Strategy
PDPWM
Sine
Trapezoidal
0.58
1.21
PODPWM
Sine
Trapezoidal
0.18
0.36
APODPWM
Sine
Trapezoidal
0.42
0.45
0.95
0.39
0.84
0.16
0.40
0.60
0.86
0.9
0.21
0.79
0.12
0.53
0.67
0.97
0.85
0.15
0.77
0.13
0.65
0.69
1.03
0.8
0.14
0.62
0.18
0.55
0.65
1.05
0.75
0.23
0.46
0.16
0.37
0.55
1.02
0.7
0.29
0.47
0.54
0.28
0.35
0.96
ma
1
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30
25
20
PD
15
POD
10
APOD
5
0
1
0.95
0.9
0.85
0.8
0.75
0.7
Fig 20: %THD Vs ma for PWM Strategy with Sine Reference
30
25
20
PD
15
POD
10
APOD
5
0
1
0.95
0.9
0.85
0.8
0.75
0.7
Fig 21: %THD Vs ma for PWM Strategy with Trapezoidal Reference
250
200
150
PD
100
POD
APOD
50
0
1
0.95
0.9
0.85
0.8
0.75
0.7
Fig 22: VRMS Vs ma for PWM Strategy with Sine reference
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ISSN 2249-9954
250
200
150
PD
100
POD
APOD
50
0
1
0.95
0.9
0.85
0.8
0.75
0.7
Fig 23: VRMS Vs ma for PWM Strategy with Trapezoidal reference
6. CONCLUSION
In this paper, various PWM strategies with sinusoidal and trapezoidal referances
for new seven level inverter have been presented. The various performance parameters like
%THD, VRMS and %DF have been measured and analyzed. It is found that the PDPWM
strategy with trapezoidal reference provides lower total harmonic distortion and higher
RMS output voltage.%DF low for PODPWM strategy having sine reference.
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Issue 5 volume 1, January-February 2015
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