NewDesigns
Products
Editor: J. Daniel Nash, Raytheon Co., Missile Systems Div., Hartwell Rd., Bedford, MA 01730.
GE Calma's Apollo Domain CAE/CAD/CAM systems
General Electric's Calma subsidiary has added the recently introduced Apollo Domain series
3000 and DC570A workstations to its line of
CAE/CAD/CAM systems for electronic, mechanical, and AEC (architecture/engineering/
construction) markets.
The Domain series 3000 will support GE Calma's CAE software for semicustom and PCB
design, schematic capture, simulation, and test-
ability analysis. Moreover, GE is evaluating series 3000 (first available in the second quarter of
1986 for US electronics applications) as a plat-
for the AEC market, and the logic series CAE/
CAT/CAD software for electronic design applications, including semicustom and PCB
form for its 3D mechanical and AEC systems.
design.
The new DN570A workstation will support
For pricing and further information, contact
three new systems from GE Calma configured GE Calma, 510 Sycamore Dr., Milpitas, CA
with DDM (design, drafting, and manufacturing) software and SDRC I-DEAS for the mechanical market, DIMENSION III software
95035; (408) 434-4000.
Reader Service Number 12
ECAD unveils DRACULA on VAX 8800
ECAD tested its Parallel DRACULA IC layout verification programs on the VAX 8800 at
the end of 1985 and early in 1986. Actual
benchmarks were run in cooperation with
DEC's CAD Systems Group, part of the team
that designed and verified the Microvax ii chip
using DRACULA's design rule checker. In recent months, ECAD's Parallel DRACULA layout verification programs have been running on
DEC's VAX 8800 dual parallel processor.
Parallel DRACULA has verified a 16K static
RAM design on the VAX 8800 and on a dual
VAX 11/780 in a cluster configuration-a design containing about 130,000 devices. As measured by total elapsed time, the dual 780's
throughput was 1.78 times that of a single 780;
the 8800's throughput in dual-processor mode
was 1.76 times greater compared to single-processor mode. These figures imply overheads of
11 and 12 percent, a performance increase
Custom IC layout
software
Celerity Computing's supermini
design systems
Silvar-Lisco recently added Princess,
Reader Service Number 19
a cus-
tom IC layout software system, to its SL-2000
series of CAE tools. The system includes a
graphics editor, a project management system,
and a user interface to Silvar-Lisco logic design,
standard cell, and gate array layout tools, to
industry-standard design verification software,
and to external CAD systems.
Princess also supports hierarchical VLSI design and access to external CAD systems, allows
schematic viewing during layout editing, and
provides an edit command set, menu-driven tool
integration, multiwindow display, and system
configuration. Pricing starts at $25,000 per
workstation, and options (including interfaces
to other databases and plotters) start at $3000.
For more information, contact Bob Greene,
Silvar-Lisco, 1080 Marsh Rd., Menlo Park, CA
94025; (415) 853-6314.
Reader Service Number 11
June 1986
ECAD claims can be maintained in systems
with up to five processors.
Available immediately, Parallel DRACULA
is priced from $141,750. For more information,
contact Sue Taishoff, ECAD, Inc., 2455 Augustine Dr., Santa Clara, CA 95054; (408) 7270264.
Celerity Computing's C1230 and C1 260 distributed computer systems for CAE and scientific research, announced earlier this year and
available immediately, fill the gap between
mainframes and limited-performance officebased engineering workstations. Priced starting
at $75,000 for fully functional, multiuser installations, they provide purchasers all the tools
necessary to complete compute-intensive design
and research projects in office or laboratory
without offloading data to remote, time-sharing
computers.
System features include Celerity's proprietary 32-bit ACCEL processor and floating
point coprocessor, a reduce instruction set
(RISC)-based architecture, the Berkeley 4.2
Unix standard operating system, advanced applications software support, and open communications and graphics. A dual-processor option
on
the C 1260 increases program execution
speed, and both systems offer mainframe-class
disk storage, I/O capacity, and multiuser support for up to 128 users. Both systems are based
on industry-standard hardware and software
platforms allowing flexible system expansion.
Celerity systems measure 29 inches high, 30
inches deep, and 21 inches wide-roughly the
size of a two-drawer filing cabinet. Both are air
cooled, requiring no special cooling, and both
plug directly into standard electrical wall outlets. Functional C1230 configurations cost
$75,000. The dual-processing C1260 costs
$110,000.
For more information, contact Bob Ollerton,
Celerity Computing, 9692 Via Excelencia, San
Diego, CA 92126; (619) 271-9940.
Reader Service Number 18
65
DASH-PCB -Data I/O's new PCB router
Displayed at the recent NEPCON and
ADEE shows, Data I/O FutureNet Division's
DASH-PCB fits on the engineer's desk along
with other DASH tools for schematic entry and
simulation. DASH-PCB uses up to five different routing algorithms to assure maximum finished-board density, and users can alter algorithm execution sequences.
Once a target circuit has been designed and
simulated on a FutureNet DASH workstation,
its net list is extracted and used as input for
DASH-PCB. Parts placement is interactive and
trace routing is automatic, although users have
the option to work interactively. Additional software facilities support six postprocessing tasks
including back annotation, automatic parts-insertion files, a bill of materials, a parts list, NC
drill files, and fabrication and assembly drawings. Standard features include gate and pin
swapping, step-and-repeat macros for building
buses, and upload/download ability letting
DASH-PCN interface with VAX or IBM
mainframes.
Priced from $13,000 depending on configuration, DASH-PCB deliveries (four weeks ARO)
began in March. For more information, contact
FutureNet Corporation, 9310 Topanga Canyon
Blvd, Chatsworth, CA 91311; (818) 700-0691.
Reader Service Number 20
PC workbench software for analog design
Analog Design Tools, Inc. recently announced the first CAE software providing a
complete set of analog circuit design tools on a
PC. This PC-based version of ADT's Analog
Workbench (that runs on Sun, Apollo, and HP
workstations) offers most of the original product features at half the cost.
Like the original, the PC Workbench lets designers construct circuits, attach simulated test
instruments, and see test results on a screen
without using conventional workbench tools.
Software functions include a circuit editor,
three test setups (time domain, frequency domain, and DC multimeter), spectral analysis,
parameter entry, parametric plotting, subcircuits, and statistical analysis. The PC Workbench runs SPICE PLUS, ADT's version of the
new SPICE 3 software, and includes ADT's device model library.
PC Workbench is available as a $12,500 PC
upgrade kit including the Opus 32032 board,
mouse, documentation, and seven software
modules: the circuit editor, SPICE PLUS, DC
multimeter, time- and frequency-domain test
setups, the spectrum analyzer, and parameter
entry with subcircuit capability. Options include the parametric plotting module, the statistical analysis module, a basic 50-member device
library, ADT's 500-member general device library, and range in price from $2500 to
$12,000.
For more information, contact Michael Carroll, Analog Design Tools, Inc., 66 Willow Pi.,
Menlo Park, CA 94025; (415) 328-0780.
Reader Service Number 15
AIDA's high-speed
CAE workstation
AIDA Corporation's recently introduced
CAE workstation, first available in April, was
targeted at systems designers doing complex
digital design. It features testability and analysis tools, simulation capability, and a knowledge-based rules checker.
The initial platform for AIDA's design system is the Apollo 32-bit workstation. AIDA's
tools include a logic design rules checker, automatic test pattern generator, system simulator
accelerator, schematic design editor, symbol
editor, cell libraries, timing libraries, librarian,
and automatic logic documenter.
A typical configuration-Apollo workstation, schematic capture, logic and fault simulation, and the cosimulator accelerator-costs
$140,000. Current Apollo users can upgrade to
an AIDA design system for $85,000. For more
information, contact Georgia Marszalek,
AIDA Corporation, 3375 Scott Blvd., Ste. 340,
Santa Clara, CA 95054; (408) 748-8571.
Reader Service Number 13
66
The AIDA design system for complex digital design.
IEEE DESIGN & TEST
IMS adds dc parametric testing to Logic Master
The new parametric measurement unit from
Integrated Measurement Systems allows design
engineers to verify and measure prototypical IC
dc parametric characteristics in the design envi-
Integrated parametric testing in IMS
Logic Master's design verification system gives
designers the ability to perform functional verification as well as full device characterization of
ronment.
state-of-the-art ICs such
as
ECL and CMOS
gate arrays, standard cells, and full custom
devices.
Including a complete switching matrix verification station for device fixturing, the PMU
matrix allows users to disconnect drivers and
receivers from the DUT and route the dc PMU
to the desired IC pin for measurement, all under
automated program control. Parametric measurement ability is further enhanced through a
software automeasure feature that automatically develops a parametric test sequence covering
every DUT pin.
The PMU comes in two versions: The PMU-
1001 (at $19,200) provides a PMU and switching matrix to support up to 192 channels, while
the PMU-2001 (at $31,200) supports up to 384
channels. Both systems permit users either to
force voltage and measure current, or to force
current and measure voltage on any IC-undertest pin. Available 16 weeks from receipt of or-
der, standard Logic Master configurations with
PMU begin at $48,700.
For more information, contact Integrated
Measurement Systems, Inc., 9525 SW Gemini
Dr., Beaverton, OR 97005; (503) 626-7117.
The new parametric measurement unit from IMS.
Reader Service Number 17
ADEPT -SDL's integrated mixed-mode simulator
Silicon Design Labs' L-Simulator combines a
behavioral timing simulator, a switch level simulator, and ADEPT-a new circuit simulator.
According to SDL, ADEPT improves performance two to three times over that of SPICE
with less than a five percent error factor: Since
matrices are not required during simulation,
CPU requirements only increase linearly with
the number of nodes, rather than by the square
of the number of nodes as SPICE does.
The L-Simulator is positioned in an interactive environment allowing users to simulate and
edit circuits simultaneously, while viewing resulting states and waveforms on a graphics display. The entire design process can be tracked
with a single simulation tool, from initial behavioral specification to performance verification.
The interactive environment enables users to
verify operation and performance of CMOS,
NMOS, or bipolar circuits.
For pricing and further information, contact
David R. Reiser, Silicon Design Labs, Inc., 645
Martinsville Rd., PO Box 16, Liberty Corner,
NJ 07853; (201) 580-0102.
Reader Service Number 14
Mentor Graphics design kit for CMOS 3
Mentor Graphics Corporation recently introduced its design kit for CMOS 3, a three-micrometer CMOS standard cell library distributed by the USC/ISI MOSIS project. The kit was
jointly developed by Mentor Graphics, the
Aerospace Corporation, and BMAC (Boeing)
with MOSIS project cooperation.
The kit is currently in beta test at several
sites. Mentor Graphics and BMAC have al-
June 1986
ready completed VLSI circuitry using the new
kit. BMAC engineers designed an IC to incorporate over 1200 CMOS 3 macros (about 4000
gates) and completed the concept-to-manufacturing data cycle in four weeks. Within eight
weeks, BMAC engineers had functioning
prototypes.
Kits are available from Mentor Graphics for
$400. For more information, contact Brian
Kiernan, Mentor Graphics Corporation, 8500
SW Creekside P1., Portland, OR 97005; (503)
626-1301.
Reader Service Number 16
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