The Devices
Read sections 2.1,2.2
EE415 VLSI Design
Goal of this chapter
•Present intuitive understanding of device operation
•Introduction of basic device equations
•Introduction of models for manual analysis
•Introduction of models for SPICE simulation
•Analysis of secondary deep-sub-micron effects
•Future trends
EE415 VLSI Design
The Diode
B
A
Al
SiO
2
p
n
Cross section of pn-junction in an IC process
N-type region
EE415 VLSI Design
doped with donor
impurities
(phosphorus,
arsenic)
P-type region
doped with
acceptor
impurities (boron)
The Diode
Simplified structure
A
p
Al
A
n
The pn
region is
assumed to
be thin (step
or abrupt
junction)
EE415 VLSI Design
B
One-dimensional
representation
B
diode symbol
Different concentrations of
electrons (and holes) of the p and ntype regions causes a concentration
gradient at the boundary
Depletion Region
•Concentration Gradient causes electrons to diffuse from n to p,
and holes to diffuse from p to n
•This produces immobile ions in the vicinity of the boundary
•Region at the junction with the charged ions is called the
depletion region or space-charge region
•Charges create electric field that attracts the carriers, causing
them to drift
•Drift counteracts diffusion causing equilibrium ( Idrift = -Idiffusion )
hole diffusion
electron diffusion
p
n
hole drift
electron drift
EE415 VLSI Design
Depletion Region
hole diffusion
electron diffusion
•Zero bias conditions
p
•p more heavily doped
than n (NA > NB)
•Electric field gives rise
to potential difference in
the junction, known as
the built-in potential
(a) Current flow.
n
hole drift
electron drift
Charge
Density
ρ
+
x
Distance
-
Electrical
Field
ξ
x
(b) Charge density.
(c) Electric field.
V
Potential
ψ0
-W 1
EE415 VLSI Design
W2
x
(d) Electrostatic
potential.
Built-in Potential
 N AND 
Φ 0 = Φ T ln 

2
n
 i 
Where φT is the thermal voltage
kT
ΦT =
= 26mV (at 300 K )
q
ni is the intrinsic carrier concentration for pure Si
(1.5 X 1010 cm-3 at 300K)
EE415 VLSI Design
Diode Current
Ideal diode equation:
EE415 VLSI Design
Forward Bias
hole diffusion
electron diffusion
p
n
hole drift
electron drift
+
-
•Applied potential lowers the potential barrier
•Idiffusion > I drift
•Mobile carriers drift through the dep. region into neutral regions
•become excess minority carriers and diffuse towards terminals
EE415 VLSI Design
Forward Bias
Minority carrier concentration
•Minority carrier
concentration gradient gives
rise to diffusion current
(proportional to bias
voltage)
pn (W2)
•Law of the junction:
concentration at the edge of
the dep. region is an
exponential function of the
of the applied bias voltage
pn0
Lp
np0
p-region
-W1 0
W2
n-region
diffusion
EE415 VLSI Design
x
Reverse Bias
hole diffusion
electron diffusion
p
n
hole drift
electron drift
-
+
•Applied potential increases the potential barrier
EE415 VLSI Design
Reverse Bias
Minority carrier concentration
•Law of the junction is
equally valid for the reverse
bias case
•Minority carrier
concentration decreases
(actually approaches zero
with sufficient reverse bias)
•Resulting gradient causes
diffusion towards junction,
where their swept across by
E field to majority zone
•Reverse current limited by
availability of minority
carriers and low gradient
EE415 VLSI Design
pn0
np0
p-region
-W1 0
W2
x
n-region
diffusion
Diode Types
pn(x)
Short-base Diode
(standard in semiconductor
devices)
x
pn 0
Wn
pn(x)
pn 0
EE415 VLSI Design
Long-base Diode
x
Wn
Models for Manual Analysis
+
ID = IS(eV D/φT – 1)
VD
ID
+
+
VD
–
(a) Ideal diode model
•Accurate
•Strongly non-linear
•Prevents fast DC bias
calculations
EE415 VLSI Design
–
VDon
–
(b) First-order diode model
•Conducting diode replaced
by voltage source
•Good for first order
approximation