covnetics
Providing quality IC design solutions
Company Overview
Covnetics Limited
Eliot Park Innovation Centre
4 Barling Way
Nuneaton
England, CV10 7RH
Covnetics Limited
Company Confidential
PHONE : +44 2476 796570
E-mail us : info@covnetics.com
Copyright Covnetics Limited 2016
1
Background
•
Company Background
•
Highly skilled team of 10 personnel who have worked together for 20 years with over
250 man-years of experience
• >30 production ASIC developments (Toshiba, NEC, IBM)
• >50 FPGA designs deployed
• FPGA cost reduction early adopters
• Altera – designs implemented in Stratix II, Hardcopy II, Stratix IV GX,
Cyclone III, Cyclone IV GX, Cyclone V
• Xilinx – designs implemented in Virtex II, Easypath, Spartan 3/6, Artix 7,
Kintex 7
• Telecoms/engineering background – optical wireline platforms from the edge of a
network through to the core transmission
• Carrier grade ethernet traffic managers
• TDM SDH line framers
• TDM switches
• POS (packet over SDH) mappers
•
Quality procedures have been developed in line with ISO 9001:2008.
E-mail us : info@covnetics.com
Issue 16
Company Confidential
2
Copyright Covnetics Limited 2016
Capabilities (1)
•
Design Services
•
•
•
•
•
•
•
•
Systems and device level solutions
FPGA/ASIC RTL development and review, simulation, emulation including ‘real time’ packet testing
Electronic Design services - hardware design, schematic capture and review
Software – API drivers, embedded
App (Android) development
Test automation solutions – emulation software (Tcl, C, VB) with test scripts and regression capability
Hardware diagnostic and fault finding
Design Consultancy
•
•
•
•
•
•
•
•
•
Design process from requirements definition and review to design, implementation, verification and
review
Systems architecture – specialists in Ethernet, Packet Processing (Ethernet traffic management), TDM
FPGA vendor and device selection
Telecom standards and protocols, including node synchronisation
Systems specification – systems and device level solutions
Systems synchronisation – IEEE 1588v2, NTP and PTP, SyncE
Design migration and integration, obsolescence management
Design for cost, area and power optimisations
Ability to analyse and solve complex system level problems
E-mail us : info@covnetics.com
Issue 16
Company Confidential
3
Copyright Covnetics Limited 2016
Capabilities (2)
•
Specialisation in Design services
•
•
•
•
•
•
Contract or sub-contract design services for FPGA & ASIC developments
Added value in telecom and packet based solutions and design
End to end design services competence
• End customer requirements definition and capture
• Technology selection and evaluation
• Added value verification and review methodology
• Complete solution capability with API development
Selected as a Hardware Resource Supplier to GE Aviation, Cheltenham
Partner on the Ismosys Design Partner Program
Associate Member : Xilinx Alliance Program, engaged with Altera for access to Design Services Network
E-mail us : info@covnetics.com
Issue 16
Company Confidential
4
Copyright Covnetics Limited 2016
Design Competencies
•
Design Competencies
•
•
•
•
•
•
•
•
•
•
•
Packet and TDM Switching
Traffic Management
• MAC
• Classification
• Policing
• Header Modification
• Queuing
• Shaping
OAM
• Ethernet Operations Administration Management, IEEE 802.3ah
• Service Operations Administration Management, IEEE 802.1ag and Y.1731
System Synchronisation – SDH, IEEE 1588v2 (NTP and PTP)
Embedded NIOS cores in Altera technology
Embedded ARM cores in Xilinx Zynq technology
Embedded MCU software - C
Android APP development
SDH (Synchronous Digital Hierarchy) multiplexing and transmission systems (STM1 to STM256)
Ethernet/ATM transport over SDH
PDH (Plesiochronous Digital Hierarchy) multiplexing and transmission systems (E1/E3/E4/T1/T3)
E-mail us : info@covnetics.com
Issue 16
Company Confidential
5
Copyright Covnetics Limited 2016
Interfaces
•
Industry standards (implementation thereof)
•
Some of the industry standards in which we have expertise:
•
•
•
•
•
•
•
•
•
•
•
DDR2, 3 memory interface with various FPGA vendors
AXI System-on-Chip (SoC) interconnect
SPI-3 (System Packet Interface Level 3) – chip-to-chip, channelised, packet interface
XAUI - MAC to/from PHY for 10G interface
Interlaken - high bandwidth channelised, packet interface
SGMII, GMII, MII – Media Independent Interfaces for MAC to PHY
High speed Serial IO to 10Gbps – multi lane Gbps sync backplane interface design
MDIO and I2C interfaces to external PHY device and SFP
SDHC memory card controller
STM1, 4, 16, 64, 256 – SDH transmission rates (also SONET equivalents)
UTOPIA – ATM data path interface
E-mail us : info@covnetics.com
Issue 16
Company Confidential
6
Copyright Covnetics Limited 2016
Recent Contracts
•
•
•
•
•
•
•
Concept definition, requirement definition, FPGA architecture definition and power analysis
for the Pulsar System Sub-element functions within the SKA program, working with the
University of Manchester
Multiple design service wins with Tier1 telecommunications supplier
• Four custom IP developments (Cyclone III, Spartan 6, Kintex 7 325T & 480T)
• Ethernet traffic management and OAM
• Custom RTL developed for ASIC (TSMC 28nm)
• Ethernet traffic management and OAM
• Feature enhancement to an ‘Ethernet over SDH mapper’ FPGA (Stratix II)
FPGA design services provided for Genesis Technical Systems – broadband data
communications network (Spartan 6)
FPGA design services provided for Apical Imaging – image transfer using SD card technology
(Stratix IV GX)
FPGA design services provided for obsolescence management – designing STM16
mux/demux functions in FPGA (Artix 7)
Multiple ASIC/FPGA design and RTL verification services provided for GE Aviation Systems
Limited, design process methodology inline with DO-254
Worked with Guidance Marine on their next generation hardware (Cyclone V)
E-mail us : info@covnetics.com
Issue 16
Company Confidential
7
Copyright Covnetics Limited 2016
Organisation Structure
E-mail us : info@covnetics.com
Issue 16
Company Confidential
8
Copyright Covnetics Limited 2016
Design Process
E-mail us : info@covnetics.com
Issue 16
Company Confidential
9
Copyright Covnetics Limited 2016
Verification Process
•
•
•
•
•
Verification covers a high percentage of the development life cycle
No one method can be solely used to ensure a design is fully verified
Covnetics employs several methods to ensure a design is verified to a high level
Verification methods overlap to maximise the probability of detecting issues
Rigorous three phase verification methodology integral to our formal design process
standard
• Simulation – RTL simulation, co-simulation,
self-checking testbenches
Simulation
• RTL Review – line by line code inspection to verify
functionality, asynchronous boundaries, state machine
lock-ups, conformance to design rules
RTL Review
Hardware
Emulation
• Hardware Emulation – auto generated database of
design register map, auto generated GUI forms for
modules, TCL based scripts, script regression ability
E-mail us : info@covnetics.com
Issue 16
Company Confidential
10
Copyright Covnetics Limited 2016
CAE Tools
E-mail us : info@covnetics.com
Issue 16
Company Confidential
11
Copyright Covnetics Limited 2016
Business Summary
• Business model
•
•
•
•
•
Complete start to finish custom IP development service
Licence free (client retain IPR), IP licence (Covnetics retains IPR), or shared licence
Flexible model : fixed pricing or time and materials based
• On programs where assistance is required for up front definition this can be time
and materials based followed by a fixed priced model once the program is agreed
and defined
Support/maintenance based agreements
Negotiable payment terms
• Ways of Working
•
•
•
•
Covnetics site working - high bandwidth internet site access suitable for remote access
Regular visits to customer’s site to support the development and post-development
program
Regular weekly meeting via conference call to ensure program is progressing to
schedule. Can be more often if required
In house tools support – Mentor Graphics, Altera, Xilinx, Microsemi
E-mail us : info@covnetics.com
Issue 16
Company Confidential
12
Copyright Covnetics Limited 2016
Case Study – Ethernet Traffic Manager (1)
•
Customer Case Study
•
Design Contract : Undertake full design and verification responsibility for new Ethernet traffic processing
implementation for use in Xilinx Kintex 7 technology, and for RTL implementation into customer ASIC
•
The customer’s design process and rules were followed for this development
•
•
•
•
•
•
Period : 18 months
Resource : 10 personnel
Customer : Tier 1 Telecommunications Supplier
Technology : Xilinx Kintex 7 and vendor ASIC
Device Resource : approx. 53k registers, approx. 200 RAMs (~2Mbits), core speeds 125MHz and 200MHz
Business Model : Time and materials (hourly charge), expenses for European visits covered by customer
E-mail us : info@covnetics.com
Issue 16
Company Confidential
13
Copyright Covnetics Limited 2016
Case Study (2)
•
General description : the FPGA was used in a product which transports packets from an ethernet LAN
interface over a microwave WAN radio interface. Conversely takes the packets from the WAN interface
and transports them over the LAN ethernet interface. The design encompassed the following functions :
•
•
•
•
•
•
•
•
•
•
•
MAC interfaces at 100M, 1GE and 2.5GE, full duplex. Includes full set of standard based
performance counters
MAC address learning for both the LAN and WAN ports, access control lists for the LAN port
Flexible classification incorporating a custom hardware processor. Software (microcode) for
classification algorithms written by Covnetics and executed within processor
Policing algorithms at frame or bit rate
Packet header modifications to support VLAN tagging and de-tagging
Link and Service OAM support, also encompassing customer hardware processors for software
updates (Covnetics microcode)
Management port MAC (10M/100M) for insertion and extraction of control packets (DCN packets)
IEEE1588v2 transparent and boundary clock support (Precision Timing Protocol – PTP), addition of
timestamps
Traffic scheduling and priority queuing, DDR3 interface
MDIO and I2C interfaces to external PHY device and SFP
In-built diagnostic packet generators, analysers and packet capture
E-mail us : info@covnetics.com
Issue 16
Company Confidential
14
Copyright Covnetics Limited 2016