LECTRO
TATIC
ISCHARGE
SSOCIATION
URIN
OAD
LDG
OME

Preface.......................................................................................................................................... ii
Glossary of Terms.........................................................................................................................iii
PART I: Technology Scaling and ESD Roadmap
1.
Silicon Technology Trends......................................................................................................1
Charvaka Duvvury
2.
New Package Trends.............................................................................................................. 5
Charvaka Duvvury
3.
ESD Technology Roadmap..................................................................................................... 9
Steve Voldman, Tim Maloney and Charvaka Duvvury
PART II: ESD Testing and New Test Methods
4.
ESD Testing and Qualification Trends .................................................................................. 11
Steve Voldman
5.
ESD Testers and the Need for Improvements — HBM, MM and CDM Issues ..................... 13
Mike Chaine and Leo G. Henry
6.
Wafer Level HBM and MM Testing — Pros and Cons.......................................................... 21
Mike Chaine and Evan Grund
7.
Transmission Line Pulse (TLP) Testing ................................................................................ 26
Steve Voldman and Leo G. Henry
8.
Electrostatic Discharge at the System Level......................................................................... 31
Michael Hopkins and Jon Barth
9.
Charged Board Model (CBM) ESD ....................................................................................... 39
Andrew Olney and Leo G. Henry
10.
Cable Discharge Event (CDE) .............................................................................................. 44
Michael Hopkins
11.
Transient Latchup (TLU) ....................................................................................................... 47
Steve Voldman and Chris O’Connor
PART III: Future Issues
12.
New Electronic Trends: Nanoparticle Technologies — Coming of Age ................................ 54
David Swenson and Timothy Maloney
13.
Research Opportunities ........................................................................................................ 57
Charvaka Duvvury and Steven H. Voldman
- i -

Since the early part of the new millennium there has been a thrust in the semiconductor electronics industry to introduce new technologies and newer applications at a much faster rate than ever before. This has led to an unusual impact on ESD as both the IC suppliers and customers have been scurrying to meet the anticipated higher ESD sensitivities. This comes not only from the delicate technologies that are necessary for high speed circuit operations but also from the increased consumer applications of the electronics making them even more susceptible to ESD events in the field. A good example is the now common use of cell phones with high speed Digital Signal Processor chips. Compounded with this, the complexity of the IC packages increased their vulnerability to a variety of ESD transients at both the component level and at the system board level. Therefore the testing for ESD reliability under different scenarios has also become a crucial part of the evaluation.
The pyramid on the cover of this document is intended to represent this push from the technology challenges along with new ESD test requirements that are squeezing out the available ESD reliability window. This document is essentially divided into three sections. Part
I examines the impact of technology scaling and the advanced circuit requirements that are driving the ESD roadmap. Part II introduces the developments in ESD testing and qualification followed by descriptions of the new test methods that would require more comprehensive ESD test methods. Finally, Part III outlines the upcoming new applications and points out the critical areas of ESD research needed to keep up with the future developments. Our hope is that the reader would find this information valuable in preparing for the future of ESD as we move toward the next decade. With the introduction of newer test methods described here, the need for standards development will no doubt become even more important.
I would like to thank the ESD experts who volunteered their time in preparation of this document and for their valuable contributions. These thanks are offered to Dr. Steve Voldman of IBM, Mr.
Chris O’Connor of UTI, Dr. Tim Maloney of Intel, Dr. Leo G Henry of ESD-TLP Consultants, Mr.
Mike Hopkins of Thermo Keytek Corporation, Mr. Andrew Olney of Analog, Mr. Mike Chaine of
Micron, Mr. Jon Barth of Barth Electronics, and Mr. Dave Swenson of Affinity Static Control
Consulting, LLC. The encouragement of ESD Association Board of Directors and the help of the
ESDA Staff with Ms. Lisa Pimpinella are very much appreciated.
Charvaka Duvvury
Texas Instruments
ESD Association Board
September 2006
- ii -

ATE: Automatic Test Equipment
BGA: Ball Grid Array
CBM: Charged Board Model
CDE: Cable Discharge Event
CDM: Charged Device Model
CIM: Capacitor Inductor Module
CLTLP: Capacitor Coupled Transmission
Line Pulse
CMOS: Complementary Metal Oxide
Semiconductor
COM: Capacitor only Module
CP: Charge Plate
CVM: Capacitor Verification Module
DIP: Dual-in-line Package
DSP: Digital Signal Processor
DUT: Device under Test
EMI: Electro Magnetic Interference
EOS: Electrical Overstress
ESD: Electrostatic Discharge
ESF: Electrostatic Field
EUT: Event under Test
FICDM: Field-induced Charged Device
Model
FOD: Field Oxide Device
GP: Ground Plate
HBM: Human Body Model
HPC: High Pin-Count devices
IEC: International Electro-technical
Commission
IT2: Second Breakdown Current
LDD: Lightly Doped Drain
MCM: Multi-Chip Module
MM: Machine Model
MUGFET: Multi-gate Field Effect Transistor
PBGA: Plastic Ball Grid Array
PCB: Printed Circuit Board
PGA: Plastic Grid Array
PLCC: Plastic Leaded Chip Carrier
QFP: Quad Flat Package
RF: Radio Frequency
RFI: Radio Frequency Interference
RLC: Resistance, Inductance, Capacitance
SCR: Silicon Controlled Rectifier
SOIC: Small-Outline Integrated Circuit
SP: Standard Practice
STM: Standard Test Method
TCAD: Technology Computer Aided Design
TDR: Time Domain Reflection
TLP: Transmission Line PulseTLU:
Transient Latchup
TQFP: Thin Quad Flat Package
Tr: Transient Rise time
VF-TLP: Very Fast Transient Line Pulse
WG: Working Group
WSP: Wafer Scale Package
- iii -

Charvaka Duvvury
Since the mid 1980s the advances in Integrated Circuit (IC) technologies have had a major impact on the intrinsic ESD reliability which in turn adversely affected the on-chip protection design capability. Because the majority of the advanced semiconductor electronics are built with silicon technologies, this chapter will review the scaling features of this technology and the specific impact they pose on ESD. This is summarized in Table 1, where we show the transistor feature lengths in microns versus the evolutionary advances on the process and the respective specific impact on ESD. Note that in all cases the effect on ESD has become progressively worse [1].
Table 1. Silicon Technology Scaling and Subsequent Impact on ESD
Feature Size
3 to 5 um
2 um
1 um
Process Advance Impact on ESD
Junction Scaling
NMOS Intrinsic
Robustness
Lightly Doped Drain
Junctions
Silicided
Drain/Source
Junctions
NMOS Intrinsic
Robustness
Severe degradation of NMOS intrinsic robustness
Affecting Factor
Increased current density
Increased power dissipation
Poor ballasting effects
1 um
0.5 um
0.35 to 0.18 um
0.065 to 0.090 um
<0.045 um
Epitaxial Substrate
Shallow Trench
Isolation
Very short channel transistor designs
Ultra thin gate oxides below 20A
Multi-gate transistors combined with insulator substrates
NMOS Intrinsic robustness
Lower performance of NMOS or SCR protection devices
Unexpected reduction in Intrinsic
NMOS ESD robustness
Much more susceptible gate oxide damage
Very low performance for
NMOS or even diodes
Difficulty for triggering NMOS
ESD protection
Reduction in parasitic bipolar performance
Complicated merging of implant species in the drain and source
Ineffective clamp designs combined with voltage buildup
Increased power dissipation in transistors and metal interconnects
During the 3–5 um technology applications, the transistor scaling involved reducing the junction depth which allowed the transistor channel lengths to be made smaller. This has had a rapid reduction in the ESD performance, since at these junction depths the current density J resulted in being relatively higher and hence the associated heating given by J.E, where E is the electric field, increased, causing degraded ESD performance. The next major issue for the transistors was their operational field reliability that was being influenced by the high electric field E at the
- 1 -

junctions. Reducing this E by the necessary changes (such as Lightly Doped Drain) in the transistors led to unexpected reduction in ESD. In this case, although the electric field E decreased, the parasitic bipolar transistor which provides the intrinsic ESD robustness increased in its power dissipation during ESD, causing a substantial decrease in the ESD capability. Subsequent process technology optimization, however, alleviated some of the effects. But the most major impact came from the introduction of silicides on top of transistor junctions. This silicide, formed by incorporating refractory materials such as Tungsten or Cobalt, increased current density due to crowding effects and had the severe degradation on ESD.
Simultaneously, lowering substrate resistance became important to combat internal latchup of the transistors that threatened to form a severe reliability of the transistor for IC applications.
This lowering of the substrate resistance with Epitaxial material combined with silicides and the
Lightly Doped Drain at the 1um technology node had formed the most significant turning point in the ability of transistors to withstand reasonable amount of ESD current level. That is, the design of protection devices became very challenging. Subsequently, these effects on ESD continued with added features such as Shallow Trench Isolation (STI, to separate the diffused areas to avoid interactions) that reduced the bipolar efficiency, along with the much reduced channel lengths that have now been observed leading to increased heat dissipation in local areas and reducing ESD even further. As the technologies now move deeper into the nanometer range, severe effects are seen from the almost atomic in count thinness of the gate oxides. At oxide thicknesses reduced to 10-20 A range their breakdown voltage is severely lowered causing them to be extremely susceptible to ESD stress, especially for the CDM. The emerging silicon technology advance with its 3-dimensional transistors poses even more of a challenge for ESD reliability. Called the MUGFET for multi-gate field effect transistor, its process is as complex as probably could be its ESD reliability issues. A cross-section of this device is illustrated in Figure 1. In this transistor composed of hundreds of fins, the current paths are localized and can lead to damage to the fins during ESD stress [2]. Moreover, the transistor is built on an insulator (SOI) making it more susceptible to relatively higher heating during ESD.
S
G
D
Fi n
X
-S ec tio n
BOX
Si
3
N
4
SiO
2
Si
Figure 1. Cross-Section of an Advanced 3-dimensional Transistor
The gradual advances in the technology nodes have in the past led to implementation of appropriate compatible protection designs. That is, the design of ESD protection devices followed through a roller coaster dictated by the trends in the IC technologies. These trends were most simply determined by the need for new advanced features that had been going through other considerations such as long-term reliability of the transistors, improved
- 2 -

performance of the circuits, or the manufacturability of the transistors. These changes are illustrated in Figure 2, showing that during the time period of every new process technology node there was the need for development of a new protection design strategy. While the Field
Oxide Devices (FOD) or NMOS transistors were popular before the year 2000, their use and effectiveness have rapidly diminished with adverse effects from the technology. It is also clear that the SCR devices while coming in later may continue to be potentially more useful in future.
The diodes have been the most perennial form of protection and will continue to be so. Note that all these protection devices are not expected to give the expected 2kV protection beyond the year 2010 and in fact can be potentially limited to only 100V protection capability for many of the essential high speed applications. What is dictating their limitation for future application? It is simply the constraints that will be placed both by the technology and the circuit applications.
8000
6000
4000
2000
0
19
80
19
85
19
90
19
95
20
00
20
05
20
10
20
15
FOD
NMOS
MOS-SCR
Diodes
Figure 2. Trends of Typical Minimum Performance of Various Protection Devices
Consider the following future limitations that would make it difficult to achieve even 1kV HBM protection:
• Heating of the interconnect
• Low breakdown of the gate oxides
• Reduced failure currents in the new application transistors
• Lower operating voltages for the circuits
• Very low tolerance of the circuits for any ESD device capacitance
• Limited area available for ESD device implementation
Therefore it is not surprising that technology and circuit advances will continue to play the dominant role in future ESD reliability for the IC chips. To picture this better, consider Figure 3, where the ESD current from a protection device is plotted versus the application voltages. It is clear to see that the safe region of ESD protection design window is being constricted while keeping up with the IC reliability factor [2]. These can come from lowering of the gate oxide breakdown voltage combined with thermal effects from the technology scaling, especially heating from the metal interconnects.
- 3 -

I I
Figure 3. ESD Protection Design Window
From the discussions presented in this chapter, it is evident that the silicon technology has already had a major impact on the ESD protection capability. Going into the future this will continue to limit the practical achievable ESD protection.
References
1. C. Duvvury and G. Boselli, “ESD and Latchup Reliability for Nanometer CMOS
Technologies,” International Electron Devices Meeting Digest, pp. 933–937, 2004.
2. G. Boselli, R. Rodriguez, C. Duvvury and J. Smith, “Analysis of ESD Protection Components in 65nm CMOS Technology: Scaling Perspective and Impact on ESD Design Window,”
EOS/ESD Symposium Proceedings, pp. 43–52, 2005.
3. C. Russ, H. Gossner, K. Schruefer, T. Schultz, N. Chaudhary, W. Xiong, A. Marshall, C.
Duvvury, and C.R. Cleavelin, “ESD Evaluation of the Emerging MuGFET Technology,”
EOS/ESD Symposium Proceedings, pp. 280–289, 2005.
- 4 -

Charvaka Duvvury
During the 2003 EOS/ESD Symposium, Mr. Darvin Edwards of Texas Instruments presented an overview of IC package designs [1]. As he outlined, package advances are based on requirements of the different market segments. For computer applications it could only mean performance while for the consumers it is price and robustness, or for automotive and military applications it could be temperature sensitivity and reliability. Each type of package is then designed and selected according to the application. This proliferation has gone from the standard Dual-in-Line (DIP) packages to Multi-chip Modules (MCM) and to Flip-chips and
Stacked Die or even Stacked Packages. Eventually we could come to Wafer Scale Packages or (WSP). Figure 1 indicates this progress.
DCA WSP
Figure 1. Evolution of IC Packages [1]
Although not particularly considered in the past or even at present, during the package development some attention should also be given to the ESD effects as well. The aggressive technological advances into newer types of packages might very well determine the achievable
ESD performance for overall adequate reliability. For example, is the susceptibility for damage of package interconnect in substrate increasing while moving from ceramic to organic types of the future, or even for substrates without a die? These issues will be briefly examined in this chapter to give a perspective on package development and its influence on ESD.
Package ESD Effects
As the IC technologies advance there have been serious consequences to ESD protection design methods, as were noted in Chapter 1. IC packages, however, until recently have remained mostly innocuous to the ESD design efforts. In some cases the package advances like from DIP to Ball-Grid-Array (BGA) have actually made them relatively safer for HBM ESD.
For example, while DIP device pins are more readily exposed to handling the BGA or other similar type of packages, their embedded pins make them more unlikely for direct HBM stress encounters. But the next phase of package development may have surprises for ESD vulnerability due to their complex architectures. At the same time larger packages with more
- 5 -

and more pins are already showing severe impact on CDM performance. These issues will be outlined in this chapter.
Table 1. Silicon Technology Scaling and Subsequent Package Impact on ESD
Technology Node Common Packages New Developments Comments on ESD
3-5 um DIP TQFP QFP - DIP devices relatively more sensitive to HBM
1 um DIP TQFP QFP PBGA Flip-Chip-BGA TQFP more sensitive to
CDM than the BGA’s
1 um to 100nm
0.5 um to 100nm
TQFP QFP
TQFP QFP BGA
2000 pin Flip-Chip
Packages
Stacked Die/Stacked
Packages
Large pin count devices very harsh for CDM protection
Complexity in ESD testing and reduction in CDM performance
<50nm BGA Silicon Major challenges ahead for
ESD evaluation
The package evolution versus the silicon technology scaling is shown in Table 1. It should be noted that this table is just a selected snapshot and in no way accounts for the multitude of packages used in the IC industry. From Table 1, it is clear to see that these package advances given at a glance do have different influences on ESD performance and ESD evaluation. For example, as we moved away from DIP packages to BGA packages, the direct stress impact on
HBM somewhat reduced but the complexity of HBM stress rapidly went up for large pin devices.
The HBM ESD testers, which were originally built to handle small pin count devices, have begun to show confusing results because of the numerous relays and the large number of floating pins.
There is much work that is ongoing to understand these effects [2, 3]. But the focus here is on real world ESD and not the assessment obtained from the ESD testers. Other than the complexity and cumbersome issues involved with nearly thousands of pin combinations for a given large pin count device, the real world impact of package on the intrinsic HBM performance is almost undetectable. What is more severe and compelling is the impact on CDM with direct relation to package parasitics.
Impact of Package Development on CDM
The most serious impact that packages have is on CDM where its performance strongly depends on the package type and package lead design. As shown in Figure 2, if the qualitatively assessed CDM risk is now imposed in the package types of Figure 1, the TQFP packages might pose lower CDM performance while the micro-star BGA (u*BGA) can show relatively better CDM performance. This is simply related to the peak current that is discharged during the stress and directly depends on the effective package capacitance. Figure 3 presents the quantitative data on peak CDM current under different stress voltage conditions.
- 6 -

DIP
PLCC
LOW
QFP
TQFP
HIGH
PBGA u*BGA™
C-BGA
C-PGA
MED
DCA WSP
FC-CSP
FC-BGA
LOW
Figure 2. Relative CDM Risk of Different Packages
1681-LGA
144-TQFP
100-BGA
Figure 3. Measured CDM Peak Current versus Stress Voltage for Different Packages
Some of the most significant impact of packages on CDM would come from a variety of packaging factors. Consider a BGA device as shown in Figure 4. What would influence the
CDM peak current and hence the CDM performance?
These factors for the BGA could be:
•
•
•
The die size (larger die would mean more capacitance)
The mold compound (type of material and its thickness)
The lead frame metal routing (including the number of pins)
- 7 -

Figure 4. Cross-Section of a BGA Package [1]
In this manner we can see that as chip sizes are made larger and built in complex packages with many more pins (>2000), the CDM stress current will continue to increase in magnitude.
Combined with the package effects presented here, RF designs that can tolerate very little capacitance from the protection device will have difficulty meeting the ever larger CDM currents.
So, in the future CDM package issues can become worse for stacked packages and multi-chip modules. Moreover, conversion to new organic materials for environmental safety could potentially exacerbate the situation. Therefore, package engineers and ESD engineers need to work in close collaboration to maintain package performance and ESD reliability.
References
1. D. Edwards, “High Performance IC Package Design and Electrical Reliability,” EOS/ESD
Symposium Proceedings, 2003 (Invited Paper).
2. H. Kunz, R. Steinhoff, C. Duvvury, G. Boselli and L. Ting, “The Effect of High Pin-Count ESD
Tester Parasitics on Transient Triggered ESD Clamps,” EOS/ESD Symposium Proceedings,
2004.
3. M. Chaine, T. Meuse, R. Ashton, N-M Iyer, J. Barth, L. Ting, H. Gieser, S. Voldman, M.
Farris, E. Grund, S. Ward, M. Kelly, V. Gross, R. Narayan, L. Johnson, R. Gaertner and N.
Peachey, “HBM Tester Parasitic Effects on High Pin Count Devices with Multiple Power and
Ground Groups,” to be presented at the EOS/ESD Symposium, 2006.
- 8 -

Steve Voldman, Tim Maloney and Charvaka Duvvury
As discussed in Chapter 1, the trends in advanced silicon technologies toward the nanometer range are having a severe impact on the ESD capability. It is also noted that that during the
1990s, although the technology has had a negative impact, some progress was made to maintain a reasonable level of ESD protection. At least the minimum required 2 kV HBM could be met with protection design innovation. However, the major impact is expected within the next five years when the technologies shrink further into the nanometer range. There are other strong factors: constraints from the circuit design at the IO pins with the combined effect resulting in conceivably low HBM levels that would become the reality. For example, for high speed RF circuits, the capacitance from the ESD protection device size would become even more intolerable which would lead to maximum possible HBM level to be less than 100V for these sensitive designs. Consider the HBM level ESD roadmap as given in Figure 1 [1]. Note that although reasonable 2kV HBM performance might still be obtained for numerous special products with sensitive or high speed IO pins, this level will dramatically degrade to sub-100V level. This could only mean that much better control at the production areas will be very necessary. Fortunately, the trend towards packages with very close pin spacings and the much reduced incidence of human handling will certainly alleviate this threat to a large extent.
Therefore consideration should be given to lowering the HBM specs to 1kV or even 500V as a practical and realistic requirement. There should be push across the industry to modify the
HBM specs.
On the other hand for CDM, a similar trend could also be envisioned as shown in Figure 2 [1]. It was discussed in Chapter 2 that the package design and the packaging trends for the future will have a strong influence on achievable CDM. Actually, for CDM the limitation particularly comes from scaling towards the ultra-thin gate oxides. By the same token as for HBM, CDM protection levels may not be possibly designed to withstand even 50V for the sensitive pins. All of this again points to the need for much tighter controls at the factory and fab environments.
10000
8000
6000
4000
2000
0
1980 1985 1990 1995 2000 2005 2010
Year
Figure 1. SD Protection Design Window
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2000
1500
1000
500
0
1980 1985 1990 1995 2000 2005
Year
Figure 2. ESD CDM Protection Design Window
References
1. ESD Technology Roadmap, ESD Association website (www.esda.org).
2010
- 10 -

Steve Voldman
Electrostatic discharge (ESD) testing of semiconductor components is in the most revolutionary transition point in the history of ESD testing today, due to the rapid changes in the semiconductor types, circuits, applications and systems. ESD testing is important in the evaluation of the reliability of semiconductor components; hence, these new testing transitions will influence our perspective on the ESD robustness of semiconductor products. In the last five years, there has been an increase in the interest and/or resurgence of the following methods:
• Human body model (HBM) alternative test methods
• Human body model (HBM) wafer level testing
• Transmission Line Pulse (TLP) testing technique
• Very fast Transmission Line Pulse (VF-TLP) testing technique
• Cassette
• Charged Cable Model
• Charged Board Model
• IEC System level test methods
Alternative HBM test methods started being pursued in the late 1990s to address the problem that the ESD commercial test equipment cannot keep pace with the pin-count of advanced high pin-count semiconductors. A second issue is the long test time for high pin-count semiconductor chips, where it is a requirement to test all pins. To address this dilemma, alternative test methods such as sample testing, split-fixture testing and other methods are being considered.
To clearly define these new methods has been difficult. Also, it has been hard to establish a common definition to address all types of semiconductor products.
In recent years, the focus of ESD testing has also shifted to being part of the semiconductor technology development process of characterizing and qualification of the ESD robustness of the devices in the technology, as well as the qualification of products. As a result, HBM testing on a wafer-level has gained greater interest. Where this is practiced by some semiconductor corporations, it is of greater interest with the growth of foundries, and globalization of the semiconductor industry.
With the focus on understanding the ESD robustness of semiconductor technologies, a greater interest has occurred in TLP testing. With TLP testing, and establishment of an ESD technology benchmarking, it is possible to establish an understanding of the technology trend for the ESD
Technology Roadmap. In 1998, SEMATECH initiated an effort for standardization of the TLP testing methodology for the semiconductor industry. This effort was transferred to the ESD
Association in 2000, where the ESDA WG5.5 TLP committee released a TLP standard practice
(SP) document defining the testing methodology for the semiconductor industry [1]. While in
1998 there were no commercial TLP machines in the industry, there are now over six suppliers of TLP commercial systems in the United States, Taiwan and Japan, for both component and wafer level testing. An additional trend is that the growth of TLP machines is consistent with the number of development/research publications utilizing this methodology, where this methodology has become the research tool of choice for evaluation of ESD phenomenon. A key question in the future is whether the TLP methodology will replace HBM ESD testing as a qualification and release process for semiconductors chips and products in the semiconductor
- 11 -

industry, as well as other microelectronic and nano-structure disciplines (e.g. magnetic recording industry, micromachine electromechanical systems, carbon nano-tubes).
Additional to the TLP method, a new second method known as very fast transmission line pulse
(VF-TLP) testing is increasing in interest as a test method to quantify short pulse width phenomenon. Today, the ESD Association Working Group on Transmission Line Pulse testing has defined a VF-TLP standard practice soon to be released (i.e., presently in draft status).
Whereas the development of a VF-TLP standard practice is ongoing, already today there are commercial VF-TLP systems in the semiconductor industry to evaluate ESD phenomenon. This method will have continued growth as the semiconductor components achieve radio frequency
(RF) application speeds of 1 to 5 GHz.
With the ever-changing application environments, new ESD models will be necessary to address chip, board and system level interactions. A growing trend is also the need for new models that address the interactions between the system, the board and the chip. In the past, these disciplines were compartmentalized into chip-level and system-level ESD phenomenon.
Today, it is clear that new ESD testing models, techniques and practices are needed to address the chip-board interactions, to chip-board-system interactions. As a result, there is growing interest in the charged cable model and the charged board model, as well as other IEC system level test methods. As the number of circuits increase on a chip, the number of I/Os increase; this leads to an increase in the number of ports, which in turn lead to a higher number of cable connections. As a result, charged cables are playing a larger role in laptops, to systems.
Additionally, the role of the board, in a charged or uncharged state, is also an issue in systemto-chip interactions. Hence, a resurgence of interest in the charged board model is evident today. With the growth of specific industries, such as the game industry, many other models exist such as the Cassette Model to emulate computer cassettes and games used in today’s game industry.
With the changes in the technology, system-on-chip integration, decreasing design cycle times of time-to-market, there is a higher need for reduced test time placing pressure on the elimination of 100% testing of products. Additionally, in contrast, there is an increase in the utilization of ESD test methods for early learning of the semiconductor technology robustness, and what the technology robustness of a given semiconductor technology is during its qualification cycle. As a result, new methods such as wafer-level HBM, TLP and VF-TLP are being utilized in the semiconductor technology qualification cycle. And, in addition, the everchanging system environments of digital, analog and radio frequency (RF) applications, from wired to wireless is changing the landscape of test methods, to test models. It is clear that a revolution is underway in the ESD testing processes of semiconductors, and it is not clear when the traditional methods will transition or maintain ground in the future. These testing methodologies may influence the understanding of reliability mechanisms and insure reliable products in the future. Additionally, future testing methodologies that incorporate semiconductor technology evaluation, will establish the ability to establish an ESD Technology Roadmap based on the semiconductor technology generations.
Reference
1. ESDA Work Group Document on TLP Standard.
- 12 -

Mike Chaine and Leo G. Henry
SECTION A: HBM ESD Testers
Introduction
As the complexity of integrated circuits continues to increase, ESD HBM and MM stressing of IC components, of advanced deep submicron, high speed, low power, high pin count and complex multi-chip packages, becomes more and more challenging. The HBM/MM standards [1, 2] written in the late 1980s were originally developed for a two-pin tester and were adapted to relay-matrix automated test simulators in the early 1990s. HBM and MM tester – tester miscorrelation problems have existed since the first ESD testers were built [3]. These problems occur because of the complex interaction between the device under test and the ESD testers [4].
Recently, this complex interaction between the IC component and HBM simulator has resulted in false ESD failures unique to this interaction [5–8]. The failures occur only in the relay-matrix type simulators and cannot be reproduced using the simpler two-pin manual HBM simulators.
The “real” ESD sensitivity of the IC component is now uncertain.
HBM Tester — IC Component Interactions
As the number of IC pins in a component has increased, the complexity of the HBM simulators has also increased, which has resulted in a stronger interaction between the tester and the IC component. HBM tester parasitic capacitive, inductive and resistive elements are distributed throughout the test system. Some of these elements are fixed in the internal wiring of the testers, while others are variable as they are built into the design of test fixture boards [9]. When high voltages are applied to the device under test, the parasitic tester elements are also charged and can interact with the HBM discharge waveforms. This complex interaction can affect how the
ESD internal protection circuits operate and can cause unexpected ESD test results [5, 6].
In all cases, the two-pin short circuit and 500 Ω load waveform verification tests confirmed that the HBM simulators were in compliance with the HBM STM5.1 waveform requirements. When the IC components unexpectedly fail on one simulator, but passed on another system, the reason for this miscorrelation problem was always a mystery. Somehow the IC components’
ESD circuits were responding differently to the RLC parasitic elements from one HBM simulator compared to another system. This tester – IC Component interaction has always been present, but as the technology has scaled and power supply voltages have been decreased, the interaction effects have been amplified. As the technologies continue to scale and the power supplies decrease to below 1.8 V, the expectation is that these problems will increase.
New HBM tester research has uncovered a major weakness in the two-pin waveform verification test procedure [10]. Although this test procedure verifies that the stress pin at terminal A and the ground pin at terminal B meet the STM5.1 short circuit and 500 Ω load waveform requirement, the test procedure does not show how an IC package component in the socket will respond to the discharge waveforms. The basic belief was that the 2-pin verification measurement accurately evaluated all of the HBM simulator RLC parasitic elements.
Recently, the ESD Association WG 5.1 committee performed a series of short circuit and 500 Ω load waveform experiments that replaced the two-pin test with a multiple parallel pin test. The
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original purpose of these experiments was to understand what happened to the HBM discharge waveform when a single power or ground pin or ball, which were connected to power and ground planes, was stressed. The use of power and ground planes frequently occurs in the packaging of high pin count (HPC) IC components. Special short circuit pin grid array packages were used to model how an actual HPC component would react to the HBM discharge to one of its pins while the other pins were left “floating” in the socket. The waveform measurements were made either to the pin under test at terminal A or to the ground pin at terminal B.
This work accidentally discovered that some of the basic and fundamental assumptions that presumed that floating unstressed pins or balls were inactive during the 2-pin HBM stress were false. One of the primary reasons for the strong interaction between the IC component and the
HBM simulator was due to the diversion of the ground discharge currents away from the assigned ground pin(s) to parasitic capacitive elements inside the HBM relay-matrix simulators.
The HBM stressing of parallel power and ground pins in a relay-matrix type simulator is quite different from stressing just two pins in a simple manual test HBM simulator. In a parallel test, an HBM discharge pulse is applied to one of the power pins, while the other power pins, shorted together by the power plane in the package, connect to the socket of the HBM test simulator.
Each floating pin that is placed in a socket adds open-relay capacitance, and this capacitance interacts with the test board capacitance and ground termination resistance.
Each unstressed or “floating” pin can act like a capacitive load connecting to ground of approximately 4.5 pF to 9.0 pF per pin. When the open-relays were left in a floating state, one terminal of the relay was connected to ground while the other terminal was connected to an IC pin, thereby creating a small parasitic capacitor. As the number of pins increased, the number of parallel HBM tester channel lines also increased, thereby adding extra capacitance. This variable floating pin capacitance was in addition to the test board capacitance and was a strong function of the number of pins placed in the socket.
A HBM relay-matrix SPICE simulation circuit model, illustrated in Figure 1, was developed that reproduced the affects the extra pin capacitance had on the discharge current waveforms [10].
Simulation and measured HBM current discharge waveforms showed that the primary influence of the open-relay capacitance were to reduce the peak currents and to significantly slow down the rise time of the HBM waveforms through the primary ground path.
Open-Relay
Capacitanc e current path
Test Board
Capacitanc current path e
Primary ground path
Figure 1. A SPICE equivalent circuit has been proposed that shows the interaction of the IC device and HBM simulator parasitic equivalent RLC circuit elements.
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For those ESD simulators with 50 to 100 Ω ground termination resistors (R s1
), more current is shunted through the open-relay capacitance as the number of pins in an IC component increases. This shunting of the ground current away from the primary ground path is a major worry as this is a unique property of the relay-matrix type HBM simulator and does not occur in the real world.
The fundamental concern is that the HBM simulators have become part of the HBM test. The
HBM sensitivity level of the IC component does not reflect the actual sensitivity of the component, but instead, it reproduces the HBM sensitivity level of the two combined as a unique pair. The major issue today is that the very strong interactions are becoming worse as the package pin count increases.
In the most recent paper [10], the authors suggested that adding a 2 M Ω resistor to each openrelay’s capacitance ground path could theoretically shut down the parasitic current path and potentially eliminate the unwanted interaction between the parasitic capacitance of the simulator and the IC component. Retrofitting existing ESD simulators is still an unknown and its associated cost may be prohibitive. Although adding a large resistor is theoretically possible, actually building HBM simulators that can eliminate these unwanted parasitic affects is a different issue. More HBM test correlation data is still required before any real action can take place.
Conclusion
The most important progress made to date is the discovery of how the HBM simulator parasitic
RLC elements interact and modify the discharge waveforms inside a HPC short module and presumably an IC component. Understanding these affects hopefully can provide new insight into finding new HBM simulator design solutions that potentially could eliminate these unwanted interactions.
References
1. EOS/ESD STM5.1-2001. ESDA Human Body Model [HBM] standard Test Method for ESD sensitivity testing. ESDA, Rome, NY.
2. EOS/ESD STM5.2-2000. ESDA Machine Model [MM] standard Test Method for ESD sensitivity testing. ESDA, Rome, NY.
3. K. Verhaege, P. Roussel, G. Groeseneken, H. Maes, H. Gieser, C. Russ, P. Egger, X.
Guggenmos, and F. Kuper, “Analysis of HBM ESD Testers and Specifications Using A 4th
Order Lumped Element Model,” EOS/ESD Symposium Proceedings, pp.129–137, 1993.
4. C. Russ, H. Gieser, K. Verhaege, “ESD Protection Elements During HBM Stress Tests –
Further Numerical and Experimental Results,” EOS/ESD Symposium Proceedings, pp. 96–105, 1994 .
5. C. Duvvury, R. Steinhoff, G. Boselli, v. Reddy, H, Kunz, S. Marum, R. Cline, “Gate oxide
Failures Due to Anomalous Stress from HBM ESD Tester,” EOS/ESD Symposium
Proceedings, pp. 132–140, 2004.
6. W. R. Anderson, James J. Montanaro and Nicholas J. Howorth, “Cross-Referenced ESD
Protection for Power Supplies,” EOS/ESD Symposium Proceedings, pp. 86–95, 1998.
7. M. Chaine, J. Davis, A. Kearney, “TLP analysis of 0.125 um CMOS ESD Input Protection
Circuit,” EOS/ESD Symposium Proceedings, pp. 70–79, 2003.
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8. Guilhaume, J.P. Chante, P. Galy, B. Foucher, S. Bardy, F. Blanc, “Human Body Model Test of a Low Voltage Threshold SCR Device: Simulation and Comparison with the Transmission
9.
Line Pulse Test,” EOS/ESD Symposium Proceedings, pp. 110–119, 2001.
M. Chaine, K. Verhaege, L. Avery, M. Kelly, H. Gieser, K. Bock, L.G. Henry, T. Meuse,
T. Brodbeck, J. Barth, “Investigation into Socketed CDM (SDM) Tester Parasitics,”
EOS/ESD Symposium Proceedings, pp. 301–310, 1998.
10. M. Chaine, T. Meuse, R. Ashton, L.G. Henry, M.I. Natarajan, J. Barth, L. Ting, H. Gieser,
S. Voldman, M. Farris, E. Grund, S. Ward, M. Kelly, V. Gross, R. Narayan, L. Johnson,
R. Gaertner, N. Peachey, “HBM Tester Parasitic Effects on High Pin Count Devices with
Multiple Power and Ground Pins,” EOS/ESD Symposium Proceedings, 2006.
SECTION B: CDM ESD Testers
Introduction
For the Electro-Static Discharge (ESD) Stress Testing of semiconductor devices using the
Charged Device Model (CDM), the challenges are related not only to both device package type and package size, but also to the design of the CDM equipment Test Head, the design of the waveform verification module and to the diagnostic measurement chain. The originally designed CDM ESD Testers [1, 2] were most suitable for small devices, as is evidenced by the small size of the non-specified Ground Plane, and the specified size of the Charge Plate [3] in the standard as they relate to the devices being measured. Several CDM publications [4–6] have shown that CDM ESD testers’ lack of repeatability leads to tester miscorrelation and therefore to incorrect CDM ESD failure thresholds for the devices.
CDM METROLOGY Measurement Chain
The peak currents, rise times and waveforms for the same voltage differ from tester to tester independent of the other components in the measurement chain. The capturing of the true
CDM ESD waveforms have always been questioned because the higher the BW and/or sampling rate of the scope used to capture the waveform, the more detail is revealed [7]. It has been shown that beyond the 3.5 to 4.5 GHz BW, the waveforms exhibit large distortions that include double peaks. These double peaks and distortions are never observed at the 1.0GHz measurement level. Using the standards’ specified 3.5 GHz BW scope, the measurement of
100 pS is the actual rise time of the scope, so the resulting waveform of the ESD transient event must have been faster.
In an earlier publication [4] it was reported that the inadequacies of any diagnostic measurement chain are some of the root causes of the deviation from the waveform parameters in the standard. The measurement chain is made up of the components required to get the CDM event signal from the CDM Test Head to the scope. This includes all cables, attenuators, power splitters, delay lines, current monitors and connectors. The signal at the scope combines all losses from each of the distinct components superimposed on the real CDM waveform. Ideally, the measurement chain should transport the signal to the scope with minimum loss and/or distortions but Test Head to Test Head response times (rise times, Tr) can vary by a factor of 2 to 3 and observed Ips (peal currents) can differ by a factor of 2. The variations are due to both the BW limited equipment [8] including the sampling rate and the discharge Test Heads because the CDM waveforms depend on the total measurement system . The BW capability of measurement system must be at least 2x the event being measured for a 12% margin of error [9] . It was concluded then that the 3.5GHz BW scope did not provide the precise answer
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of CDM event amplitude and rise time of the test head, and the test heads were deemed not to be fast enough to deliver the real event.
Capacitance Verification Modules — Issues
Major discrepancies exist among different CDM ESD simulators when collecting the waveforms using the present capacitive verification modules (CVM) and using the parameters as specified in the CDM ESD standard. Supposedly identical CVMs have shown significantly different peak currents when measured under the same testing conditions and this is because of capacitance differences. The measured capacitance of different CVMs from different users can vary as much as 32% from the standard [3] requirement of 4pF (+/-5%).
The waveform data from actual devices (1–26 pF measured) and empty (no die) packages (2–
10pF measured) show broader peaks, lower peak values and slower rise times than that from the CVMs [10]. The devices in various packages (32–292 pins) produced measured rise times of 270–340 pS, and empty packages (20–48 pins) had measured rise times of 250 to 370 pS.
Since the devices and empty packages have lead frames and different lead lengths or traces, then an inductance parameter must be added to the existing capacitance parameter.
The existing CVMs design does not include the inductance in devices, so they are called
Capacitance Only Modules (COMs). Since capacitance and inductance are the central parameters associated with devices, then the COMs can be converted to CIMs (Capacitance
Inductance Modules) with the inductance designed into the 4.0pF COM. Using TDR, the measured inductance of the CIM was 9.89 nH, the measured capacitance was 5.62 pF, and the calculated impedance was approximately 90 ohms. The resulting waveforms from the CIMs are now more reliable because now we have an ESD event which is more than 2X as slow as the
1GHz scope and therefore has less than 12% error.
Using the alumina-96, the FR-4 and the RF35 dielectric materials to make the CIMs, the discharge waveforms closely replicate the discharges from both the packaged devices and the empty (no die) packages [10]. There is less waveform variability. When the extracted Ip parameter is plotted against the voltage (250 -2000), direct linearity is established. The CIMs waveforms had the same shape as the devices, hence the waveform parameters can be correctly associated with the inductance in the bond wires, lead frames, etc.
The introduction of inductance into the CIMs is significant because the 2005 Packaging
Roadmap [11] shows the design of very fast I/Os coupled and the continued move to bumps will require less built-in inductance in the packages. Even though this runs counter to what we are now introducing, some inductance is needed because the present Module has none. At the same time, as the packaging technology improves, it is easy to modify the Modules to keep up with the packaging technology requirements.
Although all three materials are suitable to manufacture the CIMs, the following properties must be taken into account when making the final decision of which one to use. Humidity affects the materials as follows: FR-4- 22% absorbed; RF-35 -2%, and Alumina-96 is 0% absorbed. The dielectric constant, K changes with frequency: FR-4 is flat to 1MHz, RF-35 is flat to 2 GHz, and
Alumina is flat to 8GHz. In addition, most materials have several dielectric constants, and even if there isn’t a constraint on what K to use, the capacitance must be measured to ensure that the specified capacitance value is obtained/used.
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CDM Tester Parameters
Data collected over the last several years [12, 13] conclusively show that a set of fundamental parameters exist, which, if not taken into account, can have undesired effects on the CDM discharge waveform. These parameters include the pogo pin diameter, the pogo pin length, the distance between the Ground Plane (GP) and the Charge Plate (CP), the capacitance of the verification module, and the areas/sizes of the GP and the CP. Existing CDM standards provide limited equipment schematics; and in some cases, the CDM simulator is simply defined as
“must meet the waveform parameters” in the standard.
The pogo pin length and pogo pin diameter behave in a competing manner and have opposite effects on the peak current, Ip. Increases in the diameter (radius of curvature at the tip ) increases the Ip, but increases in the length of the pogo pin, decreases the Ip. This is because the length of the pogo pin introduces enough inductance to change the peak current. The shorter the pogo pin length, the lesser the inductance as is seen in the following equation:
Ip = V sqrt(C/L). There is no inductance number specified in the standards. The competing affects of the diameter and the length results in the following: a long and thin pogo pin will drive the Ip to the lower limits of the standard specification, and a short and wide pogo pin will drive the parameters to the higher limits of the specifications. As much as a 53% variation between pogo pin configurations have been observed, so this can result in significant calibration and correlation issues.
The additional challenging situations for CDM ESD stressing of semiconductor devices are also related to both device package type and package size. In this setup, regardless of which pin is being stressed, the device should be fully covered by the Ground Plane and always in the same central location of the Charge Plate. If the device is not fully covered by the GP then the capacitive coupling between the GP-Device-CP combination is greatly modified and mostly reduced. This in turn reduces the overall circuit capacitance and hence a reduction in the peak current [ 12 ].
The same effects are observed for increasing the GP size, with a corresponding increase in the peak current, but the relationship is non-linear. GP size/area are not specified in the standard and are good for small devices because measurements show the rectangular size to be 2.85 in x 2.5 in (or 72.4mm x 63.5 mm). For large devices, rotations (for pin selections) of module/device caused signal variations because the total device is not covered completely by the GP, so Ip decreases with inadequate coverage.
Present CDM standards refer to the use of a GP and CP, but do not specify a distance between them. This distance is dependent on the combined effect of pogo pin length and the orientation of the leads on the device package. The vertical lead configuration produces a lower Ip value when compared to a horizontal lead configuration for the same device, and this is due to the reduced distance between GP and CP for the horizontal setup. This GP to CP distance varies because of the various package configurations (PDIP, PLCC, SOIC, PGA etc) and associated lead lengths, so the capacitance and the inductance varies in a manner that causes significant changes in Ip (if not monitored), as much as 16-19%, and this can result in out of spec waveform parameters.
The dielectric area that is in intimate contact with the conductive disc only has a minimum specification [3], but data collected [12] shows that there is no significant difference in Ip when
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this the dielectric area is increased to the size of the CP: from the minimum (30x30 mm 2 ) to the maximum 50x50 mm 2 . The CP size/area is specified (7X the package size/area) so that the
ElectroStatic Field (ESF) fringing effects are reduced to a minimum, resulting in the device under test (DUT) seeing a uniform field all around. The 2005 Packaging Roadmap [11] points to the increase in the pin count of HPC components, so an increase in package size/area may require an increase in GP and CP, and possibly an increased footprint on the CDM testers.
CDM Test Head Effects
The CDM ESD event can be modeled and simulated in an ESD Tester using an RLC circuit. Up to about 2004, it was generally accepted that a 3.5GHz (10GS/sec) scope was adequate to capture the waveform from a CDM ESD event. However, a series of unexplained failure differences occurred in the failure thresholds from similar device types. The differences occurred using three different ESD Testers from three different manufacturers. All the testers were within their one year calibration window and met the requirements of the existing standard at 1GHz (user verification). However, there were enough differences at 3.5GHz to warrant collecting the calibration waveform at a higher BW(6GHz, 20GS/sec). The observed double peak (a second peak superimposed on the first peak) at 6GHz and an overlapping peak on the
3.0GHz measurement led to the decision to perform a Fast Fourier Transform (FFT) on all three waveforms from all three testers. This led to a resonance (second) peak at the 3GHz position for the 6GHz data (see Figure 2), an overlapping peak at the 3GHz position for the 3GHz measurement and no second peak for the 1GHz data [14].
Resonance peak at 3GHz
Figure 2. : Showing the Fast Fourier Transform of the original CDM waveform collected using a
6GHz (10GS/s) BW scope.
When the parameters in the CDM standard were used to run a spice analysis, double peaks also occurred. The double peaks were removed when the impedance between the pogo pinresistor-SMA connector-cable to scope remains 50 ohms (50 ohm impedance Test Head).
Previous to this, all Test Heads had different impedances, but none were 50 ohms end-to-end.
So it is important to calibrate the Tester and obtain the waveform using higher than 3.5GHz BW scopes [14, 15] to be able to monitor any distortions in the equipment test head and measurement calibration chain.
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Summary
The CDM diagnostic measurement chain is part of the CDM tester, therefore the CDM testers need modification to get improvement because the waveforms produced are distorted. Scopes capture the CDM event and have 50 ohm input impedances. Matching cable impedances to the scope impedance and to the current monitors becomes mandatory if we are to avoid reflections.
Improperly matched CDM Test Heads cause waveform distortions due to internal reflections in the Test Heads. Losses in the Diagnostic chain are due to high frequency information losses when the low bandwidth diagnostics chain is used [16]. Using a signal faster than the response of the measurement chain will measure the exact response of the diagnostric chain. The full diagnostic chain however combines the CIM, the CDM Test Head (with the current resistive sensor), the measurement chain and the scope.
References
1. Bossard, Chemilli and Unger. “ESD Damage from Triboelectrically charged IC pins”. EOS-2,
EOS/ESD Symposium, p17-22, 1980.
2. R.N. Shaw. “A Programmable Equipment for ESD Testing the Charged Device Model”.
EOS-8, EOS/ESD Symposium, p232, 1986.
3. ESD/ANSI STM5.3.1-1999 “ESDA STM for ESD Sensitivity Testing – CDM Component
Level”.. ESDA, Rome, NY. www.esda.org
.
4. Henry, L.G. et al. “CDM Metrology: Limitations and Problems”. EOS-18 page 167, 1996; and in Microelectronics Reliability, #42, 2002, p 919.
5. Gieser, H et al. “Influence of Tester Parasitics on CDM –Failure Threshold”. EOS 16.
EOS/ESD Symposium, p69. 1994
6. Verhaege, K et al. “Influence of Tester, Test Method and Device Type on CDM ESD Testing.
EOS 16, Eos/ESD Symposium, 1994, page 49.
7. Hyatt, H et al. “Measurements of Fast Transients and Applications to human ESD” EOS-2,
EOS/ESD Symposium, p179, 1980.
8. Agilent Technical application Note “BW and Sampling Rate In Digitizing Scopes”, 1992. www.agilent.com
.
9. Tektronix-Technical Note. “High BW Transient Capture”. 1991. www.tektronix.com
.
10. Henry,L.G et al. “Issues Concerning CDM ESD Verificatio Modules- The need to move to
Alumina, EOS-21, p203, 1999; and the Microelectronics Reliability Jour. #41, (2001) p407.
11. 2005 Packaging Roadmap Overview. The International Electronics Manufacturing Initiative.
www.inemi.org
.
12. Henry, L.G. et al. “ The Importance of Standardizing CDM ESD Test Head Parameters to
Obtain Data Correlation”. Eos-22. EOS/ESD Symposium, 2000. page 72. and the
Microelectronics Reliability Jour. #41 (2001) p1789.
13. Renninger, R.G et al. “a Field Induced CDM Simulator” EOS-11. EOS/ESD Symposium, p59, 1989.
14. Henry, L.G., Narayan, R. et al. “Different CDM ESD Simulators provide different Failure
Thresholds from the same device even though all the Simulators meet the Standard specification”. A paper accepted to be published at the 2006 EOS/ESD Symposium, Eos-28.
15. Gieser, H et al. “A Traceable Method for the ARC-free Characterization of Modeling of CDM
Testers and Pulse Metrology Chains”. EOS-25, EOS/ESD Symposium, p328, 2003.
16. Hyatt, H. “ESD Diagnostic chain”. EMC/ESD 1993.
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Mike Chaine and Evan Grund
Introduction
Electrostatic discharge (ESD) testing and package qualification play an important role in determining the total reliability of semiconductor IC components. The desire to evaluate ESD sensitivity as early as possible in the new product design cycle is driving the development of techniques for ESD testing of IC components earlier in the semiconductor manufacturing flow.
Wafer level HBM and MM testing is currently used as an engineering characterization tool, similar to the role that transmission line pulse (TLP) test equipment is used today. Currently small I/O modules can be HBM or MM wafer level tested. These type of tests use 2-pin micropositioners or 25 pin probe cards extensively, and 120 pin probe cards are currently under evaluation. These ESD measurements provide important engineering data on how effective the full-size I/O ESD protection circuits and networks work as a fully integrated design solution. In addition, some companies are using HBM and MM wafer level tests as a debug tool to diagnose and fix real HBM failures. In this case, package level HBM failures have occurred and design mask fixes have been made to fix the identified fail circuits. To verify that the revised masks fix the ESD failure mechanism, wafer level HBM tests are now performed on selected pins to specific pin combinations to confirm that the ESD design solution works. This use of wafer level
HBM tests have been found to be an effective tool for shorting the time required fix a known
ESD failure mechanism.
The commonly used Standard Test Methods for Human Body Model (HBM), Machine Model
(MM) and Charged Device Model (CDM) all specify package level ESD testing. Wafer level
HBM, MM or CDM standards test methods have not yet been developed. This limitation is now becoming a major industry problem as more companies start shipping more wafers and die as their finish product. The challenges and issues with extending the package level ESD test methods to wafers level ESD tests is the subject of this chapter.
Today’s Wafer Level HBM and MM Test Capabilities
ESD equipment manufactures have demonstrated the capability of applying both HBM and MM pulses to bond pads on the die in wafer form that fully meet the HBM (STM5.1) and MM (5.2) package level discharge current waveforms. Two different test techniques have been developed.
They include very basic two-pin test, which use micropositioners and individual needles, and multi-pin test, which include small 25-pin and 120-pin probe cards. The individual needles are usually used with manual or semiautomatic probe stations, while the probe cards are made for semiautomatic and fully automatic probers. The simplest HBM or MM test uses two contacts to conduct the pulse through the device under test (DUT).
The two most important parameters that must be controlled are ringing and pulse rise times. As the wiring of an HBM/MM simulator is extended to micropositioners placed on a wafer probe station good frequency performance of the cables is required to meet the HBM short circuit rise time of less than 10 ns. To avoid reflections that increase ringing, the impedance of the wiring is typically kept at greater than 75 Ω. This impedance level sets the maximum cable length required to pass 500 Ω test load rise time requirements. The ringing frequency of MM short circuit current waveform must also be controlled. The inductance of the cabling must meet the total inductance of 0.7 µ H in order to meet the ringing frequency waveform requirements. In fact, extra inductance must be added to reach this “magical” value of 0.7 µ H. While it is difficult to
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meet all these waveform specifications defined in STM 5.1 and 5.2, wafer level HBM and MM simulators can be built that can meet these specifications.
One approach is to build an ESD pulse generation circuit onto a probe card as this minimizes the pulse conduction path and controls test system RLC parasitics. An alternate method is to supply a high current square wave pulse using a 50-ohm cable to an HBM or MM RLC filters, which are placed close to the wafer probes [1]. This technique can apply the stress pulses to the DUT through individual needles or through a small switch matrix to the needles of a probe card.
The existing wafer level HBM and MM test equipment has been developed primarily as an engineering characterization tool. Although this is type of engineering measurement is valuable, the exiting hardware is limited in its ability to replace the package level HBM and MM qualification tests. In the package level tests, when an individual pin is stressed to power or ground supply with multiple pins, all of those pins are connected to ground through a relaymatrix system. The same situation occurs when the I/O-to-I/O pin combination stress is applied.
In this situation, a single I/O pin is stressed while all other I/O pins are held at ground.
A two-pin wafer level test can apply the correct waveform pulse to the bond-pad under test, but only one bond-pad can be grounded at a time. Consequently, the simple wafer level test with individual pins requires multiple ground needles each with its own holder and micropositioners.
This adds significant expense to testing of parts with many I/O pins or high pin count power planes.
Probe Card Option
The limitation of the two-pin wafer level test system potentially can be improved if a probe card is used. In this case additional pins built onto the probe card can be used with a relay matrix type system and grounded. In this specific case, a single pin can be defined as the high voltage pin, the HBM or MM pulse terminal, and all of the other pins on the needle assembly built on the probe card can be defined as the ground terminal. The probe card systems can ground any combination of pins but are also limited to the needle count.
The introduction of complex probe cards increases the cost of performing the ESD wafer level tests. Although a common probe cards can be used, each die will require its own needle assembly and that has to be custom made. Unlike the purchase of a package socket and test fixture board where more that one device type may be used with the socket, the needle assembly design typically is unique for each specific design. Since it is custom made, the needle assemblies can be quite expensive, especially as the number of bond pads on the die increases.
Two-Pin Wafer Level Tests
The simplest and most cost effective ESD wafer level test method available would be the twopin test method. In this case, the additional cost of constantly purchasing new larger needle assemblies would be eliminated. Since only two pins would be stressed at a time, increasing the pin count or bond pads would not impact the design of the ESD wafer level simulator since the design is independent of the number of pins or bond pads in the design. In addition, this very simple design solution keeps the unwanted tester parasitic RLC components at a minimum and
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eliminates the interaction between IC component or die and the ESD simulator that is present in package testers.
This type of a wafer level test method uses either two micropositioner or one micropositioner and the probe station. When a full die is to be tested, the micropositioners probe needles move independently from one another. This allows two degrees of freedom of motion, so the high voltage (HV) terminal A micropositioner and terminal B micropositioners would be independently controlled. After the HV micropositioner was placed on the terminal A bond pad, the terminal B micropositioner could be moved systematically to different ground bond pads, which connect to different power and ground supplies and to different I/O bond pads. After the different pin combination tests have been performed, the HV micropositioner would move to the next bond pad in the test plan and the terminal B micropositioner would repeat its previous movements to ground the other individual bond pads.
This type of a probe station is still in a research and development phase and has not yet been fully developed. The primary advantage of this type of simulator is that it could easily adjust to a die with 500 bond pads or 5000 bond pads. Although it would be a more complex mechanical system, this type of two pin robotic simulator would have minimum HBM and MM simulator RLC parasitics due to its relatively simple electrical design.
The basic issue with this two-pin wafer level ESD simulator test method is the fact that it would not meet the existing STM5.1 or STM5.2 package level test procedure. As previously discussed, this system would not be able to ground more than one pin at a time. The grounding of multiple pins to reduce the total number of theoretical pin combinations would not be achieved with this type of an ESD simulator. As a result, new HBM and MM test standard methods would have to be developed that would permit ESD sample testing for both the multiple power and ground bond pads as well as multiple I/O and input bond pads.
The overall cost of this type of wafer level ESD HBM test method would be limited to the number of probe stations and the number of HBM wafer level test simulators. Additional cost for special needle assemblies would be reduced and the system would automatically expand to increasing die size or increasing pin or bond pad count. Since this type of test system is dependent solely on the physical size of the wafer, the only increase in cost over time would be the cost of new larger probe stations to account for larger wafer size.
Wafer Level CDM Test
The capability of generating either a HBM or MM discharge pulse to bond pad on a die on a wafer has been demonstrated and commercial equipment can be purchased to perform this type of test on simple test structures or relatively small modules or small number of I/O pins.
Performing a similar type wafer level test that uses the Charge Device Model (CDM) test method has not yet been demonstrated. CDM testing is a unique test in that the IC die and package are raised to a high voltage potential, this charges the parasitic capacitance stored inside the package and the silicon of the component under test and is abruptly discharges when a ground probe is brought closed to the lead or ball of the package.
The discharge currents have been shown to be a strong function of the capacitance stored in the package, and to a certain degree a property of the CDM test equipment. A wafer level CDM
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test would not be able reproduce the charge stored in a specific package because this is a parasitic property of the IC package.
Unlike the HBM or MM test where an external pulse is applied to the bond pad, the CDM discharge current pulse is strongly dependent on how the charge is distributed inside the package, the network impedance of both the package and the power bus network inside the die and the atmospheric conditions like humidity and altitude. Although an external fast transient pulse can be applied to the bond pad under test with equipment such as a vf-TLP system, a
CDM pulse is not replicated. A vf-TLP pulse, even with a pulse duration approximating a CDM pulse, is fundamentally different from a CDM discharge from a ball on a package IC component.
The vf-TLP technique requires a stress of one pad and a grounding of another pad on the die to complete the circuit path. This is completely different from a single pin CDM pulse that uses the device capacitance to discharge from a single ground pin. The high current flows from the die under test could be very different between these two test methods and could potentially produce totally different failure mechanisms.
A different approach for transferring charge to the IC package has been proposed by Maloney.
This new method applies a charge-packet generation technique that is based on transmission line directional couplers [2]. Another technique that is under investigation is called the Capacitor
Coupled TLP (ccTLP) [3], [4]. This technique uses a square waveform with short pulse widths as an approximation of a CDM pulse. An important aspect of ccTLP is that the charge injection is into single pad and not a pair of pads. The capacitance of the die on the wafer to the holding wafer chuck is used to complete the current path. The amount of charge actually transferred to device depends on this capacitance.
Wafer level CDM testing is still in a research and development phase of its development. More basic work still needs to be done to prove that the test result achieved by these alternative test methods actually can reproduce the same electrical failures caused by a package level CDM test simulators.
Conclusions
Wafer level HBM and MM test equipment exists today that can perform engineering characterization analysis. This test equipment can generate discharge current waveforms that can meet the existing package level STM5.1 and STM5.2 requirements. The existing hardware is limited to either small probe cards 25-pin or 120-pins or 2-pin micropositioners. Increasing the number of pins in the probe cards to much higher pin counts is theoretically possible, but the added cost for building custom made needle assemblies potentially may be a limiting factor.
Developing the full capabilities of a two pin wafer level tests is one option, but this alternative
HBM test method would require the introduction of a new wafer level HBM and MM test standard methods that would require the simplification of the complex pin combination requirements that exist in today’s package level HBM and MM standard test methods. Although
HBM and MM wafer level tests are possible to do today, performing CDM tests in wafer form is still in the research and development phase of development. New promising research is in progress, but more work is required before a standard practice test method can be developed.
References
[1] Grund, “A wafer level HBM tester delivering pulses with variable rise time through transmission lines” Journal of Electrostatics 62 (2004), pp. 99-112
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[2] T.J. Maloney and S.S. Poon, “Using Coupled Transmission Lines to Generate Impedance-
Matched Pulses Resembling Charged Device Model ESD”, 2004 EOS/ESD Symposium
Proceedings, pp. 308-315
[3] H. Wolf, H. Gieser, W. Stadler, W. Wilkening, “Capacitively Coupled Transmission Line
Pulsing CC-TLP - A Traceable and Reproducible Stress Method in the CDM-Domain” ”,
2003 EOS/ESD Symposium Proceedings, pp. ??
[4] H. A. Gieser, H. Wolf, F. Iberl, “Comparing Arc-free Capacitive Coupled Transmission Line
Pulsing CC-TLP with Standard CDM Testing and CDM Field Failures” Proceedings of the 3 rd
EOS/ESD/EMI Workshop, Toulouse, France, 2006, pp 11-17.
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Steve Voldman and Leo G. Henry
In recent years, the focus of ESD testing has shifted from a qualification and release process to utilization of ESD testing for semiconductor technology quantification, release, and qualification on the single components (wafer level) instead of the product chip level. This perspective has lead to the growth of interest in the transmission line pulse (TLP) methodology. In the 1970’s, the technique of pulse testing of semiconductor was commonplace with a focus on the powerto-failure of semiconductor devices. At that time, the interest was the survival to the semiconductor components to a wide spectrum of frequencies from nano-seconds to microseconds. Today, this method has had a resurgence with an interest in the current and voltage
(I-V) characteristics of semiconductor components where the device is step-stressed and the current and voltage conditions are recorded through the step-stress. Simultaneously, at each voltage level, a dc voltage is applied to the chip and leakage current measurements (ranging from picoamps to nanoamps) are obtained. The combined I-V and Leakage curve provides additional information which is critical to early failure tendencies.
Interest in transmission line pulse (TLP) testing is growing rapidly in the testing of electronic components in the semiconductor industry [1,2]. TLP testing techniques are being used for semiconductor process development, device and circuit design. This technique or practice is being utilized on products in both wafer level and packaged environments. TLP testing is used as an ESD characterization tool to obtain voltage-current pulse characterization parameters, leakage current anomalies, failure levels, and ESD metrics. The TLP technique is being used today as a standard measurement for ESD devices. The TLP system to the ESD engineer is becoming a tool as critical as the “parameter analyzer” is to the semiconductor engineer.
With a step-stress approach, a pulsed I-V characteristic provides a set of current, voltage, leakage current and impedance values that can be used to quantify the device response to the
TLP stress testing method. With this information, ESD technology benchmarking can be established as well as development of high current device models which may be critical for the
ESD Technology Roadmap [4].
A transmission line pulse (TLP) standard practice (SP) document was released in June 2003 for the semiconductor industry, by the ESD Association Work Group 5.5 Device Testing. The document is ESD Association Standard Practice for the Protection of Electrostatic
Discharge Susceptible Items – Electrostatic Discharge Sensitivity Testing: Transmission
Line Pulse (TLP) Component Level [1].
In Table 1, the TLP pulse waveform parameters of current and voltage is shown.
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Table 1: TLP Current and Voltage Pulse Parameters
TLP Pulse
Parameters
(Voltage & Current
Conditions)
Pulse Width
Rise Time
Fall Time
Fall Time
Typical Values for r-TLP
100ns
0.2 to 10ns
0.2 to 10ns equal to rise time
Load Condition for r-TLP
50 ohm
50 ohm
50 ohm
Typical Values for vf-TLP
Load Condition
For vf-TLP
< 10nS
0.1 to 0.5nS
50 ohm
50 ohm
0.1 to 0.5nS 50 ohm
Greater or equal to rise 50 ohm time
20% of plateau 50 ohm
Max.Peak Voltage
Overshoot
Max.Voltage
Ringing Duration
20% of plateau 50 ohm
25% of pulse width 50 ohm
25% of pulse width
50 ohm
Current Overshoot
50 ohm 20% of plateau 50 ohm
Ringing Duration
Measurement
Time Window
10% to 95% of pulse width
N/A
25% of pulse width
50 ohm
10% to 95% of pulse width
N/A
In this method, there are four possible system configurations that can be utilized, depending on the system topology, and whether the system is observing the reflected, transmitted, or absorbed pulse response [(Constant Current, TDR, TDT and TDRT ) ]. The TLP methodology defines test equipment requirements, pulse waveform, a calibration, and verification methodology. The method [1] is based on a 100 ns pulse width and equivalent peak current at the same voltage, to approximate the HBM standard [ESDA/ANSI HBM standard 5.1]. Today, there are commercially available TLP systems that support the TLP SP document methodology.
Figure 2 shows an example of a time domain reflection (TDR) TLP system as seen in the TLP standard..
Transmission Line
Pulse
Attenuator
Delay Line
Switch
HV Power
Supply
10-100M
Current and
Voltage Probes
DUT
Figure 2. Time Domain Reflectometer (TDR) TLP
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For the testing procedure, Figure 3 shows an example of the TLP testing methodology for the step-stress.
Procedure
Calibration and
Verification
Initial leakage/ parametric test
Apply stress pulse to the DUT
Measure and
Record pulse voltage and current
Perform poststress leakage measurement
Fail
Stop testing
Increase stress pulse amplitude
No
Pass
Max Pulse
Amplitude
Reached?
Yes
Stop
Figure 3. Flow Diagram for the TLP Component Test Procedure
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Figure 4 shows an example of a TLP I-V characteristic and leakage current evolution from the
TLP test methodology. In Figure 4, the I-V characteristic highlights the transition points of avalanche breakdown, snapback, and thermal failure.
1x10E--6 2x10E-07 3x10E-08 4x10E-09
Leakage Current
Figure 4. TLP I-V Characteristic Highlighting the Semiconductor Device Transitions
The growth of the TLP testing processes are well established globally as a ESD testing practice in semiconductor foundries globally (e.g. IBM, Chartered Semiconductor, Texas Instruments,
AMD, Intel, National Semi, TSMC, and UMC). In some foundries, the TLP data is released to the customers as part of today’s business practice, whereas in others it is used for qualification evaluation of the technology only.
In the future, TLP testing has great opportunities due to the natural compatibility with radio frequency applications. First, RF testing methods are consistent with this methodology due to the two-port testing of RF circuits and two-pin nature of TLP testing. Secondly, the TLP systems are being designed as 50 impedance systems, similar to RF networks. Third, the language and the methods are consistent (e.g. time domain reflectometry is used in RF circuit evaluation and in ESD TLP testing).
A new method known as very fast transmission line pulse (vf-TLP) testing is increasing in interest as a test method to quantify short pulse width phenomenon. In the 1970’s such methods were utilized to characterize the power-to-failure of RF and microwave components. In present day, the objective was to mimic the CDM method; this unfortunately has not yet been achieved due to the nature of the charge source. But, the method as originally developed for
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microwave and RF components, has value in quantifying short pulse phenomenon in the adiabatic regime.
This vf-TLP method will have continued growth as the semiconductor components achieve radio frequency (RF) application speeds of 1 to 5 GHz. Today, the ESDA Standards Working Group
5.5 Device Testing Transmission Line Pulse (TLP) testing has initiated a standard practice draft for the vf-TLP method, the ESD Association Draft Standard Practice for the Protection of
Electrostatic Discharge Susceptible Items – Electrostatic Discharge Sensitivity Testing:
Very Fast Transmission Line Pulse (vf-TLP) Component Level [3].
References
[1] ESDA/ANSI Association DSP5.5.1-2003 Standard Practice for the Protection of
Electrostatic Discharge Susceptible Items – Electrostatic Discharge Sensitivity Testing:
Transmission Line Pulse (TLP) Component Level, June 2003.
[2] S. Voldman, R. Ashton, B. McAffrey, J. Barth, D. Bennett, M. Hopkins, J. Bernier, M. Chaine,
J. Daughton, E. Grund, M. Farris, H. Gieser, L.G. Henry, H. Hyatt, N.M. Iyer, P. Juliano, T. J.
Maloney, L. Ting, and E. Worley, “Standardization of the Transmission Line Pulse (TLP)
Methodology for Electrostatic Discharge (ESD),” Proceedings of the Electrical Overstress/
Electrostatic Discharge (EOS/ESD) Symposium, 2003, pp. 372-381.
[3] ESD Association DSP5.5.2 Draft C: Draft of Standard Practice for the Protection of
Electrostatic Discharge Susceptible Items – Electrostatic Discharge Sensitivity Testing: Very
Fast Transmission Line Pulse (VF-TLP) Component Level, 2005.
[4] ESDA Roadmap, 2005. Editors: Voldman, Duvvury and Maloney
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Michael Hopkins and Jon Barth
Introduction
At the system level, ESD is a threat to the proper operation of virtually all electronic items, from your desk top computer to drug infusion pumps, televisions, mobile phones, security systems, controls at large process plants, and more. As manufacturers are driven to provide more complexity in less space, the devices that handle the data, communications and control— semiconductors—become smaller and more dense, and as a result, more sensitive to environmental effects such as Electrostatic Discharges (ESD). At the system level, ESD could cause damage to semiconductors but more likely the effect will be upset or loss of data. While standards do exist for hardening products against ESD, they are lacking in a number of ways and completely ignore the radiated effects of ESD. Fortunately, some changes are coming, but historically standards changes are slow and hampered by industry’s unwillingness to replace existing ESD simulators and change the way tests have been done historically.
The System Level Threat
ESD exists, and at the system level it’s actually a problem with people. As we move around, we get charged to hundreds and even thousands of volts from the triboelectric effects of two materials rubbing against each other, such as shoes against carpets or clothing against a leather or vinyl seat. Most readers can relate to walking across the carpet and getting “zapped” by the doorknob.
When you do get “zapped” by the doorknob, you’re probably getting charged to 10,000 volts or so, although there isn’t enough energy in the discharge to harm you (unless as a result, you pull your arm back too quickly and into the corner of a file cabinet!). Making a discharge to the doorknob doesn’t really hurt anything, but if instead of the doorknob the discharge point is your laptop computer, you could be in for a surprise.
To put the threat into perspective, most people can’t even feel a 2,000 volt discharge; most everyone can feel a 5,000 volt discharge. 15,000 volts is something you really will feel and at that voltage you can expect to see an arc that’s as much as a few millimeters in length. How many times have you seen that kind of discharge into your keyboard or telephone, or anything else? Probably not often, which says that the 15,000 volt test level in many international standards is probably a good upper limit number as a threat to products from people, but like everything else, there will always be exceptions.
Effects
Only a few volts at the wrong time and in the wrong place can cause a data error in a system.
With the threat being thousands, or even tens of thousands of volts, industry really must be doing a pretty good job of keeping ESD from effecting semiconductor devices or you’d be seeing frequent product failures both at home and at work. However, as the semiconductor devices become more and more dense, the amount of energy necessary to cause a problem also becomes less. Notice the term is “energy,” not voltage, because it is not really the static voltage, it is how fast the resulting currents are changing that makes it easier to get more energy into sensitive circuits.
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The voltage threat outside the product has little or no effect until a discharge occurs, either to the victim equipment or device directly or to some close-by object that’s at a different potential 1 .
Because there is usually very little opposition to resulting current flow between two metal objects, the current tries to go up very, very fast and that means energy exists at extremely high frequencies and is more easily coupled into internal circuits where it may appear as just another data pulse: Something turns on or off unexpectedly, some data appears to be corrupt or worse yet, some machine starts or stops when it shouldn’t resulting in a safety issue.
Product failure and upset due to ESD is well known in virtually every industry, from aerospace to zoology, but not always well documented in the public domain. After all, no manufacturer wants to advertise product problems, past or present, and are they really not interested in giving hints to their competitors about how to fix the problems. As a result, most documented cases that do make it into the public domain are quite old or “sanitized” so that particular manufacturers and products can’t be easily identified.
Standards
Today there are numerous standards for testing products for the effects of electrostatic discharges, but they are all slowly becoming harmonized. For electronic products in general, there are two primary standards: IEC 61000-4-2 and ANSI C63.16. In the automotive industry,
SAE and ISO standards dominate at the international level but automotive manufacturers still lean heavily on their own internal standards. Even though the harmonization process really is taking place, there will still be areas in some industries where higher test voltages, different energies or test methods will remain important. In addition to the test standards, ESDA has published a Standard Practice which specifies the metrology necessary for accurately measuring the ESD currents from the simulators used to test to these standards.
IEC 61000-4-2
IEC is the International Electrotechnical Commission and their Basic EMC Standard, IEC
61000-4-2, is probably the most dominant ESD standard for testing electronic products today, primarily because of its status in the European Union (EU) hierarchy for testing products. The process to revise this standard is underway at this writing.
In 1989 the EU published an EMC Directive requiring all products shipped into EU countries or across borders within the EU must meet certain basic immunity and emissions requirements.
This includes a test for ESD immunity based on IEC 61000-4-2 2 . Since the publication of the
EMC Directive in Europe, it has been used as a model for similar directives in other parts of the world, including China, Australia, New Zealand and others. Because of this expansion, and because meeting these directives is a legal requirement to ship products and not just a recommendation, the IEC standards have become quite dominant.
1
Any object, including a person, that becomes charged is charged with respect to the surrounding environment and all other objects in the area. A discharge to equalize charge can occur between any two objects with un-equal charges and doesn’t have to be to a “ground” point. For example, a person charged to 10kV will cause a discharge to occur by touching a object charged to any voltage other than 10kV. It’s a question of charges between two objects equalizing without any absolute reference to ground or anything else.
2
For purposes of compliance to the EMC Directive, tests are done to IEC 61000-4-2, which is essentially identical to
EN 61000-4-2. The EU decided that it makes more sense to base European Norms (ENs) on international standards, such as those published by the IEC. In literature, IEC 61000-4-2 and EN 61000-4-2 are often used interchangeably.
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It should be stated here that it really takes more than a legal requirement for a standard to dominate—it needs to be a good standard. When the ESD standard first surfaced in the IEC as
IEC 801-2, it was the first document of its type to surface in the international area. Prior to that
(mid 1980s) every industry and sometimes different companies within those industries, had their own ideas about ESD testing. The 801-2 drafts got people going in the same direction partly because it was based on broader research and not specific to individual industries 3 . This meant that standardized tests could be developed across industries, making it easier for product manufacturers as well as for the manufacturers of simulators.
ANSI C63.16
ANSI is the American National Standards Institute. Not only do they publish standards they develop themselves, they also publish standards developed by the IEEE (Institute of Electrical and Electronics Engineers), ESDA (Electrostatic Discharge Association), and others. ANSI
C63.16 is American National Standard for Electrostatic Discharge Test Methodologies and
Criteria for Electronic Equipment. ANSI C63.16-1993 was revised; however publication seems unlikely at this point. That said, there are some differences between ANSI and IEC that warrant some discussion:
IEC 61000-4-2 contains information about the simulator, how to perform the tests and provides some recommended test levels. It does not provide specific test levels for compliance or failure criteria. This is left to other documents, such as Product, Product Family and Generic standards
ANSI C63.16 does provide specific test levels and failure criteria for Information Technology
(IT) products, Consumer Products and Telecommunications equipment.
There are technical differences as well, including a faster rise-time of the injected current pulse and many more discharges per point when testing a product, but because it was recognized that during ESD testing, occasionally
failures occur that are difficult to reproduce, and escalation strategy has been included as follows:
If a failure occurs at a particular test level at a particular test point and the operator expects this to be a random event (note: the operator may declare any failure as a “random” event), the operator may repeat the test at this point (at all test levels) according to the following procedure.
• If more than one failure occurs in the first 50 discharges, the EUT fails the test at that test point and voltage level. The error cannot be declared a random event.
• If one error occurs in the first 50 discharges and the operator suspects this to be a random event, a second test is run at that test point applying 100 new discharges to the original EUT or another identical EUT. If no errors occur in this set of 100 discharges, the
EUT passes the test at that test point. If more than one error occurs in this set of 100 discharges, the EUT fails the test. If exactly one error occurs in this set of 100 discharges, a third test is performed.
• The third test is to apply 200 new discharges at that test point. If no errors occur in this set of 200 discharges, the EUT passes the test at that test point. If one or more errors occur in this set of 200 discharges, the EUT fails the test.
3
The IEC 801 series of standards was being prepared by the process control industry to deal with EMC effects in control rooms, which were quickly being converted from electro-mechanical and pneumatic controls, to new computer control systems. At some point it was realized that these new control rooms were representative of general office areas – carpets, air-conditioning, computers, etc… -- and the work transferred to a group with the responsibility for developing a series of Basic EMC Standards, including one for ESD.
- 33 -

This is quite a departure from the ESD testing at the IEC level and from the way most manufacturers test for ESD susceptibility, but it makes perfect sense and needs to be considered for future test standards.
Figure 1. Discharge currents from various ESD Simulators, all of which meet the requirements of IEC 61000-4-2 .
ESDA and Simulator Issues
As testing to IEC 61000-4-2 became widespread (at the time, IEC 1000-4-2), manufactures began to realize that tests done using a simulator from manufacturer “A” didn’t correlate with testing done using a simulator from manufacturer “B”. Products could pass or fail depending on the simulator being used. In fact, manufacturers have been know to select the simulator based on getting passing results for compliance tests, and a different simulator if they wanted to stress the product more severely to look for failure levels. Both simulators meet the requirements of
IEC 61000-4-2.
Because passing tests based on IEC 61000-4-2 are a legal requirement for placing the CE mark on products, it seems essential that work be done to first figure out why different simulators that all meet the standards requirements then produce different test results, and second, what can be done about it.
Working Group 14 was formed in the ESDA to try and get a handle on this problem, and what they found was that the current discharge from some ESD simulators included considerable ringing at very higher frequencies – to several GHz – and other simulators had very little high frequency ringing. It was shown that simulators with this higher frequency energy caused failures and upset where simulators with “clean” waveforms, i.e. no high frequency ringing, did not produce failures.
- 34 -

The primary problem the working group came up against was the lack of an acceptance metrology for comparing the ESD currents from simulators. IEC 61000-4-2 states: “The values of the characteristics of the discharge current shall be verified with 1000MHz bandwidth measuring instrumentation.” Further, it says that the “…bandwidth of the target has to be more than 1GHz.” Details of a recommended target are provided. The 1993 ANSI document requirements were essentially the same. Unfortunately, limiting the bandwidth of the measurement equipment to 1GHz also limits the ability to see any higher frequency ringing.
Figure 2. Test Setup for Monitoring ESD Currents according to IEC 61000-4-2
Working Group 14 of the ESDA worked out a metrology for making measurements of ESD currents that included the real bandwidth of the measurement system. As a result, both users and manufacturers of simulators now have a clear, defined way to make comparisons. It doesn’t prohibit using lower bandwidth measurements – at 1GHz for example to comply with IEC requirements, but does make it clear that the peak currents and higher frequency ringing won’t be observed. Even before the ESDA document was published, ANSI included the basic metrology and future IEC drafts will likely do the same.
As a result of work done in ESDA, measurement methods for ESD currents from system level simulators today are quite well defined and will likely cross over into making measurements of
ESD currents from device level testers and for looking at currents resulting from cable discharges.
How Tests are Performed
A typical test setup for the IEC evaluation is shown in Figure 2. ESD testing of products at the system level is conceptually simple: make a discharge to anyplace where an operator of the equipment could touch, and see what happens. In reality it’s a bit more complicated. Issues that always come up are: What points do I test, what if the product is all plastic, and do I really have to test all the pins of a connector?
First, both ANSI and IEC leave it to the manufacturer to determine what points need to be tested, and both suggest that these should be points deemed to be most susceptible to the ESD events.
As a general rule, you want to test points where people are likely to come in contact with the products – keyboards, touch screens, controls, displays, etc… Points you don’t need to test
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include cable ports on an installed product that the operator isn’t likely to touch. Think about it this way: “I never touch the cables connected to the back of my desk-top computer. The computer is installed by someone trained to do so and I just operate the keyboard and use CDs”.
In this case, a manufacturer could easily justify not testing the cable ports on the back of the computer, but would certainly be testing the keyboard and areas around the CD drawer. On the other hand, a laptop computer that you travel with may have something constantly plugging in the back of it. The manufacturer needs to recognize that these ports should definitely be tested for ESD susceptibility.
Testing an essentially all plastic product is no different – if you can’t make a discharge to a product and no failures occur by trying to do so, you’re product is in pretty good shape, but wait a minute: what happens as the ESD simulator is moved around the product trying to make a discharge at, say, 4kV? It’s likely that the unit itself is becoming charged by the voltage from the
ESD simulator, and if the polarity is changed on the simulator, now moving a simulator charged to -4kV around a product that is sitting there at +4kV, a differential of 8kV. This is a real problem with small double insulated (no ground) plastic products such as cell phones, and there are really only two possible ways out: use ionizers in the area to carry the charge away from the unit under test, or if there is any exposed metal on the product, connect a drain wire via 470k ohm resistors between ground and that exposed metal.
Whether plastic or not, most products have connection points for power, communications, or both. These connectors for power are sometimes just recessed two pin connectors incased in the plastic molding of the product, RJ45 Ethernet connectors, D connectors used for RS 232 or video, or a multitude of other configurations. ESD into these connector pins could cause problems, so the question becomes, “Do I need to test each pin for susceptibility?” Generally, the answer is “No”.
Amendment 2.2 to IEC 61000-4-2 adds the following statements regarding points where tests do not need to be done:
“Unless stated otherwise in the Generic, Product related or Product Family standard, the following exclusions apply:
• those points and surfaces, which are only accessible under maintenance. In this case special
ESD mitigation procedures shall be given in the accompanying documentation.
• those points and surfaces, which are only accessible under service by the (end-)user.
Examples of these rarely accessed points are: battery contacts while changing batteries, a cassette in a telephone answering machine, etc.
• those points and surfaces of equipment, which are no longer accessible after fixed installation or after following the instructions for use e.g. the bottom and-/-or wall-side of an equipment or areas behind fitted connectors.
• the contacts of coaxial and multi-pin connectors, which are provided with a metallic connector shell. In this case, contact discharge shall only be applied to the metallic shell of that connector.
NOTE: Contacts within a non-conductive e.g. plastic connector and which are accessible shall be tested by the air-discharge test only. This test has to be carried out by using the rounded tip finger on the ESD generator.
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• those contacts of connectors or other accessible parts which are ESD sensitive because of functional reasons and are provided with an ESD warning label e.g. RF inputs from measurement, receiving or other communication functions.
Determination of Susceptibility Levels (Pass / Fail)
Under the European Union system, Product, Product Family and Generic Standards determine what tests are to be done and at what ports, the levels at which the tests are to be done, and the failure criteria. IEC 61000-4-2 specifies the test set-up, simulator, and test procedure and requires 5 shots of each polarity per point. There are three basic levels of performance criteria as defined in Generic Standards, and they are used throughout the Product and Product Family
Standards as well:
Performance criterion A: Essentially no loss of function, degradation of performance, loss of data or safety issues below a level specified by the manufacturer, both during and after the test.
Performance criterion B: Same as A, except that during the test itself, degradation of performance is allowed.
Performance criterion C: Temporary loss of function is allowed, provided the function is selfrecoverable or can be restored by the operator.
The current version of ANSI C63.16 defines undesirable responses as:
Automatically recoverable
Recoverable
Non-recoverable
Destructive
Tests are then done based on a calculation of Mean Time Between Undesirable Response, estimations of expected numbers of ESD events in the products lifetime and expected voltages.
A very complex exercise.
The new draft instead uses the following criteria listed in Figure 3 based on 25 shots in each polarity and an escalation clause:
1
2
3
Temporary Degradation or loss of function that is self-recoverable after the discharge.
Temporary degradation or loss of function that requires operator intervention or system reset after the discharge.
Degradation or loss of function that is not recoverable due to damage from the discharge.
Figure 3. ANSI EUT Response Criteria
The escalation clause described earlier then applies.
Future Work at the System Level
The biggest gap in system level testing and test standards is the lack of information regarding the radiated effects of ESD. We’ve known for some time that different simulators have different
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radiation characteristics, and there still isn’t any information regarding how well any of the simulators replicate the radiation characteristics of a discharge from a person.
In order to begin the process of quantifying these effects, Working Group 14 of ESDA has begun a document to specify the metrology for looking at the ESD radiation. Experiments have been done using a large circular ground plane with Electric Field (E-Field) and Magnetic Field
(H-Field) sensors mounted at certain distances from a discharge point in the center of the ground plane. Both monopole and TEM E-Field sensors, and large and small loop antennas were used for picking up the H-Fields. Although it has been a slow process putting the document together, it is hoped this will become the basis for future specifications of the radiated characteristics of ESD Simulators.
Some data does exist in an informative Annex to the ANSI C63.16 draft and it’s certain that these radiated effects will become an issue to be dealt with in future standards.
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Andrew Olney and Leo G. Henry
Introduction
Anecdotal evidence of ESD failures of Integrated Circuits (ICs) that are mounted on Printed
Circuit Boards (PCBs) have been published since 1981 [ 1, 2, 3 ]. These PCB failures occurred after personnel handled the PCBs during all stages of manufacturing, inspection, assembly or replacement in electronic equipment. The magnitude of the transient discharges from the PCBs into the ICs have been shown to depend on three factors: (i) the potential on the PCB, (ii) the capacitance to ground of the PCB and (iii) any other circuit elements in the discharge path. The measured board capacitance was as high as 120pF when using PTFE or PMMA as dielectric.
This PCB capacitance is compared to the less than 25 pF for IC devices being built at that time.
The charged board failure thresholds were much less than the thresholds of the recognized charged device model (CDM) failures, and as the PCB to ground capacitance increased, the failure threshold of the board failures decreased. On the other hand, any resistance in the discharge path raises the susceptibility level, but not significantly.
In the early years, up to 1984 [ 4 ], most components which failed for the ESD transients on the board passed the electrical parametric testing, but failed functional testing, so internal node failures were assumed. This is in contrast to the single component (IC) level ESD failures which failed parametric electrical testing at the stressed pin. Here the physical failure was usually junction damage at the stressed pin. Failure Analysis of the ICs from the Board confirmed the internal location and the physical damage type to be dielectric/silicon punch-through. The boards were replaced and tighter ESD controls (handling and protective packaging) were employed.
After 1984 [ 5 ], this PCB ESD discharging event was referred to as a Charged Board Model
(CBM) ESD event and CBM ESD Testing was initiated. ESD sensitivities of components mounted on PCBs were lower than that from CDM and the failure levels were not related to
HBM nor to CDM. In all cases, the ICs passed component level ESD testing, but failed board testing. There are three distinct mechanisms for discharge transients associated with the PCB.
If a charged person touches a PCB that is already grounded, the discharge transient will result in an HBM failure. If an ungrounded PCB is held by a charged person, and the PCB is then grounded, a CBM failure will occur. In the latter case, the off-board edge connector on the charged PCB usually makes contact with the card-frame connector into which the PCB is being pushed. The PCB rapidly discharges via whichever connector makes contact first, and the susceptible ICs in its path will fail.
For the third mechanism, the Board mounted ICs can be damaged by the discharge current which flows when an inductively-charged PCB is grounded via an input connector. Here the
PCB is in the field of a charged object or surface, so the conducting materials on the PCB get charged by induction, and the PCB develops an induced voltage. This is also a CBM failure and the physical location and type is the same as the previously explained CBM failure [ 6 ].
The ESD Models
Three electrostatic discharge (ESD) models are commonly used in the electronics industry: the
Human Body Model (HBM), the Machine Model (MM), and the Charged Device Model (CDM).
For integrated circuits (ICs), ESD testing to these models is conducted on an individual
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component basis, i.e., ICs are not mounted to a Printed Circuit Board (PCB) when stress tested for qualification . This component-level ESD testing is effective at simulating real-world ESD events that occur on ICs prior to PCB mounting. However, component-level ESD testing is not a good predictor of how susceptible ICs are to ESD after they are mounted on a PCB. In fact, an IC mounted to a PCB may be much more or much less susceptible to ESD than when this same IC is handled individually.
Charged Board Model (CBM) Overview
Conceptually, the Charged Board Model (CBM) is similar to the Charged Device Model (CDM).
During a CDM event, the charge stored by a packaged IC discharges just (nanoseconds to picoseconds) before contact is made with a conductive object at or near ground potential.
During a CBM event, the charge stored by an entire PCB discharges just (picoseconds to nanoseconds) before contact is made with a conductive object at or near ground potential.
Thus, the Charged Board Model can be thought of as an extension of the Charged Device
Model where the PCB is the “device” which stores the charge. However, since a PCB can store far more charge (higher capacitance) than a single IC, the peak discharge current for a CBM event is typically much higher than for a CDM event. Consequently, the damage from a CBM discharge can be quite severe and can be easily mistaken for electrical overstress (EOS) damage.
Charged Board Model (CBM) Testing
A PCB can be tested to the CBM in essentially the same manner as a packaged IC is tested to the CDM. Theoretical and empirical CBM studies have been conducted since the late 1980s [1-
10]. Recent work [10] has shown that Field-Induced Charged Board Model (FICBM) testing can be used to simulate real-world CBM failures using a commercially-available robotic CDM test system as follows:
1. Center the PCB on the charging plate as shown in Figure 1. Note: The PCB is separated from the metal charging plate by a thin dielectric layer (for example, 13 µ m thick Mylar) because the bottom of the PCB has solder joints and other metal that would otherwise short to the charging plate. This addition changes the capacitance of the whole system, and has to be controlled.
2. Set the charging plate to +125 V and then discharge the desired PCB node (for example, the GND plane). Repeat this step two more times.
3. Electrically test the PCB.
4. Set the charging plate to -125 V and then discharge the desired PCB node. Repeat this step two more times.
5. Electrically test the PCB.
6. Repeat steps 2-5 after incrementing the charging plate voltage in 125 V steps until the PCB electrically fails or the maximum charging plate voltage of the system is reached.
7. As appropriate, repeat steps 2-6 using other likely real-world PCB node discharge points such as additional power planes, edge connector pins, metal components that are physically highest on the PCB, etc.
- 40 -

DSP
127 mm (5”) diameter charging plate
Figure 1. FICBM Test Method Setup for a DSP Board
NOTE: No industry standard currently exists for CBM testing, but a Standard Practice
Document is being considered by the Device Testing Working Group members. Standardizing
CBM testing is challenging for a number of reasons. Existing test systems are designed for small components and therefore do not accommodate relatively large PCBs. In addition, since
PCB designs and layouts vary significantly and each PCB may have hundreds or even thousands of potential discharge points, specifying specific discharge points in a standardized test method is not easy, but a Standard Practice Document can be developed.
Charged Board Model (CBM) Test Results
Figure 2 compares the FICDM discharge waveform for a single Digital Signal Processor (DSP)
IC to the FICBM waveform for the same DSP device mounted to the PCB shown in Figure 1.
Not surprisingly, for a given charge voltage (250 V in this case), the FICBM discharge has much higher peak current than the FICDM discharge. This is because PCB capacitance is much higher than IC package capacitance. Also, the FICBM event has a faster rise time than the corresponding FICDM event. This is because the inductance of the discharge path is lower on the PCB than on the stand-alone DSP device. This is primarily because the traces on the
Board are much wider and thicker than bond wires on an IC. The net result of the much higher peak current and faster rise time for the PCB is that a given IC that is effectively immune to ESD damage at the device-level may be quite susceptible to ESD damage at the board level. If the mounted IC is in the primary discharge path on the PCB, the CBM ESD damage on the IC will be much more severe. Consequently, such ESD damage can look like EOS damage.
- 41 -

10
8
6
0
-2
4
2
FICBM vs. FICDM Discharge Waveforms for DSP with a 250V Charge Voltage
GND test pad FICBM
GND pin FICDM
Time (nanoseconds)
Figure 2. Comparison of FICBM vs. FICDM discharge waveforms
Identifying and Minimizing Charged Board Model (CBM) Failures
ICs are most susceptible to CBM ESD damage if one or more of the following conditions apply:
1. The IC is adjacent to large insulators such as plastic sockets or plastic connectors.
2. The IC is close to PCB edges, especially PCB edge connectors, mounting holes, or test points.
3.
4.
5.
The IC has numerous supply pins that are soldered to supply planes, especially if the supply planes are large.
The IC has a large die that results in a very low impedance discharge path, especially if the IC is the primary discharge path for the PCB.
The PCB does not include explicit EOS/ESD protection such as Transient Voltage
Suppressors across the supply planes.
ICs and other components on PCBs are most susceptible to CBM ESD damage during the processing steps from when they are first populated with components until they are inserted into a case or other enclosure that provides adequate ESD protection. Ionizers should be used throughout PCB manufacturing lines to minimize PCB charging, particularly during steps when insulating components (sockets, connectors, etc.) are mounted, and just prior to convection/IR reflowing or wave soldering.
Summary
The Charged Board Model (CBM) is not as well known as other ESD models but it represents a major real-world ESD threat. Even if all the individual components used for a given PCB have high device-level ESD robustness, one or more of these components may be very susceptible to ESD damage after mounting to a PCB. Since a PCB has much higher capacitance than an individual device, CBM damage can be much more severe than CDM damage. Therefore, before attributing an IC failure on a PCB to EOS, the possibility of CBM ESD damage should be explored.
- 42 -

Bibliography / References
[1]. D.E. Frank,. EOS/ESD Symposium. “The Perfect ‘10’. Can you really have one?” EOS-3, p
21, 1981
[2]. W.Y. McFarland,. EOS/ESD Symposium. “The Economic Benefits of an Effective ESD
Awareness and Control Program- An Empirical Analysis”. EOS-3, p 28, 1981
[3].W.H. Thompson,. EOS/ESD Symposium. “EOS Damage. Does it happen on PCBs?” EOS-6, p 22, 1984
[4]. R.N. Shaw & R.D. Enoch,. EOS/ESD Symposium. “An Experimental Investigation of ESD
Induced Damage to ICs on PCBs.” EOS-7. p 132, 1985
[5]. R.D. Enoch and R.N. Shaw,. EOS/ESD Symposium. “An Experimental Validation of the
Field Induced ESD Model.” EOS-8, p 224, 1986
[6]. J.M. Koyler et al., EOS/ESD Symposium. “ESD Control in an Automated Process”. EOS-9, p 41, 1987.
[7] D. Pierce, “Can Charged Boards Cause IC Failure?” EOS/ESD Technology, February/March
1988.
[8] G. Weil, “Characterization and Test Methods for Printed Circuit Board ESD,” IEEE
International Symposium on Electromagnetic Compatibility, pp. 124-129, 1990.
[9] W. Boxleitner, “The ESD Threat to PCB-Mounted ICs,” EOS/ESD Technology,
October/November 1991.
[10] D. L. Lin, “FCBM – A Field-Induced Charged-Board Model for Electrostatic Discharges,”
IEEE Transactions on Industrial Applications, Vol. 29, No. 6, pp. 1047-1052, 1993.
[11] D. L. Lin, and M-C Jon. “Off-chip Protection: Shunting of ESD Current by metal fingers on ICs and PCBs” EOS-16. EOS/ESD Symposium. P279, 1994. .
[12] D. C. Smith, E. Nakauchi, “ESD Immunity in System Designs, Systems Field
Experiences and Effects of PWB Layout,” EOS/ESD Symposium Proceedings, EOS-22, pp.
48-53, 2000.
[13] R. Peirce, “The Most Common Causes of ESD Damage,” Evaluation Engineering,
November 2002.
[14] J. Barth, J. Richner, K. Verhaege, M. Kelly, L.G. Henry, “Correlation Considerations II:
Real HBM to HBM Testing, EOS/ESD Symposium Proceedings, EOS-24, pp. 155-162, 2002.
[15] A. Olney, A. Righter, D. Belisle, E. Cooper, “A New ESD Model: The Charged Strip
Model,” EOS/ESD Symposium Proceedings, EOS-24, pp. 163-174, 2002.
[16] T. Dangelmayer, “ESD Myths and the Latency Controversy,” Compliance Engineering,
Spring 2002.
[17] A. Olney, B. Gifford, J. Guravage, A. Righter, “Real-World Printed Circuit Board
Failures,” EOS/ESD Symposium Proceedings, EOS-25, pp. 34–43, 2003.
- 43 -

Michael Hopkins
Introduction
The Cable Discharge Event, or CDE, is the discharge that occurs when a charged cable is connected to a piece of electronic equipment. This cable is then likely to become charged by a triboelectric process as it is dragged through the building during installation. The insulating sheath rubs against whatever is up in the ceiling, resulting in a charge that is then transferred to the conductors in the cable. Result: a static voltage just waiting to be discharged when the cable is connected to your computer or the company server! But that’s not the only threat – what about the other way around? The cable isn’t charged but the product about to be connected to the cable is charged. Is that the same as a “cable” discharge? The answer, of course, is yes because the result is simply an equalization of charge between the cable and the product to which it’s being connected without regard to polarity or to which one was more recently charged up. It may be that a charged cable holds more charge than a charged product, but the event remains pretty similar in the end.
The Threat Level
Unfortunately, there isn’t much published information about the charges that are developed in or on cables—or the voltages at the time of a discharge. A few white papers have appeared in the last few years 4,5,6,7 , but not a lot of data is provided on the event itself. The published papers tend to deal with experimental effects such as what happens when a cable of x length is charged to y volts, and then discharged. Some papers talk about the effects on products without going into details. In the case of a TIA report 1 , currents for a given charged cable are measured using a target like the one used for looking at ESD currents from simulators, described in IEC
61000-4-2.
The static voltage that appears on the cable is determined by the triboelectric charging that occurs and the capacitance of the cable to everything around it:
V (voltage) is equal to the charge (Q) divided by the capacitance (C): V = Q/C.
The longer the cable, the higher the capacitance (cL, where c is capacitance per unit length and
L the length); the further the cable is pulled through the building, the more rubbing and therefore, more charging (qL, where q is charge per unit length), and therefore, more energy (Q 2 /2C, or q 2 L/2c, scaling with L)..
Any engineering student will tell you that a cable charged up to some voltage will provide a nice rectangular current pulse. That’s pretty clear, assuming you have a perfectly clean switching operation at the output of the cable. However in the real world, it’s likely there will be an air breakdown between the charged cable and its mating connector prior to a hard contact being
1
Static Discharge Between LAN Cabling and Data Terminal Equipment, Category 6 Consortium, TIA December 2002
2
Cable Discharge Event in the Local Area Network Environment, White Paper, Intel Order Number 249812-001, July
2001
4
3
A Simple Model For a “Cable Discharge Event”, Rich Brooks, IEEE802.3 Cable Discharge Ad-hoc, March 2001
Cable Effects Part 1: Cable Discharge Events, Technical Tidbit – January 2002, High Frequency Measurements
Web Page, Douglas C. Smith
- 44 -

made; an arc, if you will, resulting in a transient voltage spike that will likely be as high as the static voltage on the charged cable. In fact, waveforms published in the TIA report show the expected rectangular pulse produced by charged cables under controlled conditions, but the leading edge and any initial transient event is missing.
Intel’s white paper 2 and Doug Smith’s Technical Tidbits 3 show a cable discharge event beginning with a current spike and followed by an oscillatory decay. Data published as white paper by IEEE 4 seems to be along the same lines as Intel and Doug Smith with the initial current spike and ringing decay, but goes further to show that the ringing frequency is dependent on the length of the cable being discharged, i.e., the shorter the cable, the higher the ringing frequency and the longer the cable, the lower the ringing
Discharge from a 4 meter cable charged to about 300V.
(Courtesy of Doug Smith’s Technical Tidbit of January 2002)
Doug Smith’s “Technical Tidbit” does describe the metrology he used to gather discharge current waveforms, but none of the other papers or reports mentioned here provide this information. Without a defined metrology for measuring CDE currents, we can’t quantify such parameters as rise times or peak amplitudes of a CDE event. We know that real ESD events from people tend to have risetimes in the picosecond to nanosecond regions, and this requires high bandwidth measurement equipment and techniques to obtain realistic data. Once the metrology is defined and accepted, we should start to see good data that will describe the event adequately.
Okay, so what does this mean in terms of the threat level? We don’t know for sure, which is why
Working Group 14 of the ESDA has been given the task of putting together a Standard Practice for CDE. The first step being to figure out what the real threat levels might be, which means: come up with the metrology for measuring these events in a way that is both repeatable and reproducible.
Why is This a Threat?
Because it is exactly the same problem as outlined in Chapter 5 of this white paper:
Electrostatic Discharge at the System Level. Upset of system operation and/or damage to
- 45 -

devices is certainly possible and is of great concern to both equipment manufacturers and device manufacturers. I can’t imagine how much Ethernet cable has been charged up while being strung through buildings in the last few years, and how much is still to be done. Perhaps this threat will be mitigated somewhat with the advent of wireless networks, but I think there’s still some time before that completely takes over. Besides, even though the cable is installed and any charges built up during installation have long been removed, the threat of connecting a charged product to the cable still exists. As I mentioned in the introduction, it probably doesn’t matter if the cable is charged or if the product connecting to the cable is charged, the result is the same: a cable discharge event. Meanwhile, cables will continue to be installed and whatever charge exists on the cable will be equalized rather quickly when connected to a piece of electronic equipment, whether it’s your PC, laptop or server.
Standards
There are no industry wide standards for testing for the effects of CDE. TIA recommends using system level methods described in IEC 61000-4-2, and that’s exactly what some manufacturers are now doing. This assumes, of course, that the threat is the ESD like transient that occurs as the charged cable approaches its mating connector. (Note: To get a discharge, the mating connector pins don’t need to be at ground potential, but only at a potential that is different that of the charged cable – the two will try and equalize through a discharge.)
There’s really no published information at this time to show exactly how manufacturers are testing their products, but there is enough anecdotal information to say that at least some manufacturers are simply using ESD simulators, such as those described in IEC 61000-4-2.
Others are charging up lengths of cable (probably using an ESD simulator of some kind) and then discharging the end of the cable directly into a connector. Still others might try using something like a TLP tester to produce a clean rectangular pulse.
One could make arguments for any of these methods, but if comparisons are to be made concerning the ability of a product to withstand such an event, a standardized method of performing the test and evaluating the results is necessary.
At the device level, semiconductor manufacturers have also expressed an interest in a test to determine if their devices will survive a CDE event, and the same thing applies here as with systems or finished products: no current standard method of testing exists, but to be able to compare the performance of one device to another, standards will need to be developed. As is the case with ESD events, the tests applicable to the semiconductor device directly may not be the same as those used at the equipment level.
Summary
It’s clear that a problem exists in industry that requires some attention. Cable Discharge Events do occur and they do cause upset and device failure in equipment and systems. The problem is that there is no good data to quantify the event characteristics, and therefore no agreed upon process for evaluating products for the effects of CDE. In order to get to the point of a well defined test method, we first need an accepted metrology so that we can capture the events, then record and evaluate the data. After that come test standards, without which comparison of product performance to CDE events just isn’t possible.
- 46 -

Steve Voldman and Chris O’Connor
CMOS latch-up represents a semiconductor failure mechanism associated with integrated circuit destructive failure. The loss of control of an integrated circuit associated with CMOS latch-up is due to a failure of the isolation scheme between p-type and n-type semiconductor devices for a given voltage bias condition, or current condition. CMOS latch-up immunity is one of the fundamental goals in the semiconductor process and circuit design. The technology, design rules, and integration are established to minimize the risk to CMOS latch-up from occurring. CMOS technology migration driven by circuit applications, cost reduction, foundry compatibility, mixed signal and system on chip technology have now converged in the industry to manufacturing IC’s on p- bulk substrates. With the migration to high resistivity substrates has lead to an increase in the likelihood of CMOS latch-up. With the rapid proliferation of multiple power supplies, integration of digital and analog devices, and aggressive design rule scaling, CMOS latch-up immunity will continue as a serious CMOS reliability defect. With the increased focus on cost, density, foundry compatibility, mixed signal products, RF technology, high level integration (e.g. system-on-a-chip) and physical limitations of implantation, the environment has significantly shifted in CMOS integration. Additionally, CMOS power supply scaling has lowered the onset of CMOS latch-up, whereas the external source has not been reduced. Today, double and triple well technologies require the optimization and synthesis of wells and isolation structures to provide the optimum CMOS latch-up tolerance. Whereas it was believed that triple well CMOS would eliminate CMOS latch-up, with the mode of design implementation, this has not been the case. In fact, in many ways, the new methodology for implementation of triple well technology has lead to degradation in undershoot tolerance to
CMOS latch-up. With the growth of RF CMOS, and BiCMOS silicon germanium (SiGe) technologies, low doped substrates for noise coupling and high Q elements, the need to continuously lower the substrate doping concentration has accelerated. With multiple well implants, implant dose and scattering issues, voltage conditions, mixed signal chips, the ability to provide a latch-up robust technology has once again become a challenge.
- 47 -

Trigger cur rent vs. N+ / P+ spacing
I trigger
500
450
400
350
300
250
470
445
400
330
280
200
1000 860 600 380 270
N+ / P+ spacing (nm)
Figure1. Trigger Current Reduction with the Scaling of the p+/n+ Spacing
(Source: W. Morris IRPS 2002)
Latch-up testing methods must capture all types of potential latch-up events that may occur on a chip, or at the system level. The ESD Association introduced the Transient Latch-up Upset
(TLU) effort to address positive and negative voltage transitions that may occur during use of semiconductor components. The ESDA has released in June 2003, a TLU standard practice document, referred to as ESD SP5.4-TLU.
The ESD Association Standard Practice for Transient Latch-up addresses specific goals [5, 6, 8].
First, the primary goal was to design a CMOS latch-up test to address short duration transient electrical disturbances. Different transient phenomena were addressed (e.g. fast slew rate pulses, long duration ringing events, short duration supply bounce, EMI, and RFI induced noise). These waveforms must be controlled and reliable waveforms so they could be simulated on latch-up test equipment.
Several waveforms were investigated and many were seen to cause CMOS latch-up. CMOS latchup was achieved with “ESD-like” events with fast rise-time and high current or voltage amplitudes. While reproducible, these ESD pulse events were often responsible for physical
ESD or EOS damage rather than CMOS latch-up. Ultimately, the negative going square pulse waveform was derived to satisfy these requirements.
Additional goals were to address states that are not in the present JEDEC latch-up specification
[9]. In particular, the V
DD
OverVoltage test has become increasingly destructive as device technologies scale to smaller sizes and lower operating voltages. To limit the complexity of the test, focus was placed on the V
DD
transient trigger.
Today, a dialogue continues in the testing community about the test coverage of the negative polarity square pulse compared to other chip and system level noise. In particular, ESD like pulses are available to test engineers via modified ESD test systems and TLP characterization
- 48 -

equipment [6]. Discussion is presently dealing with the simplicity vs. complexity of the waveform needed to fully quantify the latch-up robustness of semiconductor products.
Another leading technique was a capacitor switched into a power supply connected to the DUT.
This caused uncontrolled oscillations as the power supply struggled to regulate with the new load. This method was very difficult to repeat as the transient waveform would be altered by any change in the fixturing including length of wires and model of power supply. Although the
SP started out with this method it was eventually dropped due to these difficulties.
With the switched capacitor method, bipolar damped sine transients were shown to initiate
CMOS latch-up [6, 10]. Using a broadband power amplifier (TLU amplifier), it was possible to create specific transient waveforms to better understand the latch-up response.
A single cycle sine wave was also used to initiate latch-up. Different frequencies, phases and half sine waveforms were used. It was determined from this study that the rising portion of the waveform was always the point where latch-up occurred. For devices which triggered from a positive half sine, these devices were often already known to be susceptible in the JEDEC overvoltage test. A variety of other devices were shown to be triggered from a negative half sine, some of which had no other known latch-up sensitivity. Eventually the positive half of the sine wave was eliminated and the sine shape was changed to a square shape. This simplification had the effect of delineating the portions of the waveform when charge is injected (falling edge and lower plateau) and when charge carriers are evacuated from the substrate and triggering can occur according to the Electron Flood Theory.
Figure 2: Oscilloscope waveform showing TLU failure using method in SP5.4.
Top trace is V
DD
and the bottom trace is I
DD
(500mA/div)
Electron Flood Theory Negative Polarity Event (Trigger Mechanism)
A mechanism for triggering latch-up is a negative polarity pulse event, referred to as an
“electron flood event.” The following steps to the test are as follows:
• A device is powered to normal voltage conditions (e.g. V
DD
).
• Power supply V
DD
is pulled below ground by at least one diode V
BE
(V be
= 0.7 V).
• Power supply is returned to the normal state.
- 49 -

During the reduction of the power supply to negative polarity, the supply current is reversed and current flow into ground is due to the forward biasing of the well-substrate junctions (e.g. p- substrate). In a very short time, the substrate is saturated with these charge carriers. At the next step, V
DD
is rapidly returned to normal; when this happens, the injected charge carriers leave the p- substrate, creating current flows to the ground and V
DD
pads. The magnitude of this current is proportional to the trigger voltage (undershoot on V
DD
) and the rate that V
DD
returns to normal functional state (power supply rise time). This current flows through the substrate and other structures and creates voltage gradients according to the resistivity of those local structures. If this voltage gradient is situated in such a way as to invert a P-N junction, the resulting current flow can initiate and sustain latch-up. Since this injected current is not localized in the substrate, the latch-up could potentially be triggered locally or globally in the semiconductor chip.
Effect of Slew Rate on Latch-up Sensitivity
As the bandwidth of the latch-up broadband amplifier increased, results showed that latch-up failure occurs at smaller trigger levels. Investigations showed a strong correlation of latch-up sensitivity to power supply rise time and the amplitude of the voltage undershoots. If the risetime is too slow, insufficient current will flow in the substrate and voltage gradients will be too small to invert any junctions. It is desired to find a speed that is fast enough to trigger latch-up at the lowest trigger voltage but slow enough that it can be transmitted through typical ATE or bench-top device fixtures.
Figure 3 shows the results of TLU testing on a 74HCT00 device with known latch-up sensitivities. It is apparent that as the slew rate slows to 1 V/µs the trigger threshold for CMOS latch-up increases up to -7 V after which slower risetime would not trigger latch-up at any voltage. At this point, the slew rate of V
DD
was insufficient to produce a sufficient trigger current.
As the slew rate is increased, the trigger voltage seems to saturate at a minimum voltage and only gradually decreases as faster slew rates are tested.
D e v i c e S e n s i t i v i t y t o S l e w R a t e
0
0 1 2 3 4 5 6 7 8 9 1 0 1 1
- 1
- 2
- 3
- 4
- 5
- 6
- 7
# 2
# 3
# 4
# D
S l e w R a t e i n V / u s
Figure 3: Slew Rate Dependency of Latch-up sensitivity using the procedure in SP5.4 and a 74HCT00 device with known latch-up sensitivity.
- 50 -

From the experimental results, it would suggest that there is a slew rate that could serve as a characterization metric for CMOS latchup.
The hardware setup described in the TLU Standard Practice document allows the user to apply any transient waveform within the technical limitations of the test system (signal amplifier and device fixturing). At present this limitation is +/-30V, +/-3A, DC to 1 MHz bandwidth. The clear advantage to this TLU method is the lower likeliness of inducing EOS events. This method also allows for greater test coverage. Additionally it is slow enough to implement on a wide variety of test systems as the effective bandwidth of the waveform is 1MHz or lower. A disadvantage of this method, is that it only stimulates one likely trigger mechanism (note: there exist other possibilities for triggering latch-up such as capacitively coupled into circuits and other nondestructive circuit breakdown events).
Test Hardware
Several forms of test hardware have been used to successfully induce Transient Latch-Up. The
ESD Association WG SP5.4 method uses the source driven transient. New methods, such as using TLP and ESD test systems, have been attempted. In all cases the experimental setup needs to have a means for fixturing the device and a means for measuring V
DD
and I
DD
.
Fixturing can be a simple breadboard or manual switch box with DUT card or as complex as an
ATE switch matrix. Measuring V
DD to the DUT but measuring I
DD
is simple requiring only an oscilloscope probe placed close
will require either a clamp on DC/AC current probe (Hall Effect probe) or instrumentation built into the power amplifier or other test instrumentation. The current probe must have sufficient bandwidth to track with the rapidly changing transient.
Source Driven Transient
A source driven transient is one where the power supply V
DD
and the transient are directly supplied and under full control of the source connected to the DUT. In its most basic form, this configuration consists of a pulse source and a broadband power amplifier. These are capable of buffering the high impedance pulse source to a power level capable of simultaneously supplying
DC power to V
DD
and AC power for the transient noise signal.
A Broadband Power Amplifier is DC and AC coupled to the output. Any amplifier capable of faithfully buffering the specified transient noise signal and having a DC offset in the range of V
DD required by the DUT is a candidate. Ideally this instrument would have a DC to ≥ 1 MHz bandwidth and have a wide voltage and current range allowing it to reproduce complex waveforms with slow as well as fast changing features. Fast acting current limiting to protect the DUT and voltage clamping to protect fixture equipment like switch matrices are desirable features but not required to perform the test.
The main advantage to the source driven method is the very wide variety of transients that can be utilized. Virtually any noise signature, within the bandwidth and amplitude limitations, can be reproduced. The transient pulse source can be a basic instrument (e.g., function generator, pulse source or an advanced tool, an arbitrary waveform generator, a recorded waveform, or the output from a purposely-built circuit). These fast changing power amplifiers cover a wide range of “real world” noise that can be found on actual products and experimentally controlled signals. Another advantage is the ability to integrate this method into ATE and specifically built
TLU test systems. A disadvantage of this method is that any amplifier will have a maximum slew
- 51 -

rate and amplitude thereby excluding ESD like events. It is thought that ESD like triggers may induce latch-up via a different mode.
Stored Charge Transient (powered ESD threats)
Stored Charge Transients are electrical disturbances caused by the discharge of an electrostatic charged object into the power supply (V
DD
) of the DUT. These transients are similar to ESD triggers used in conventional CDM and MM device testing but they have generally lower amplitude to avoid causing ESD damage.
Equipment used for traditional ESD testing can be used for TLU when a power source for V
DD
is added. Combination ESD/Latch-up testers can be adapted to this task with proper decoupling of the DC source.
The advantage to this method is that it can be readily adapted from existing test systems already used for similar testing. The waveform is familiar and readily accepted as representing a real world threat. The disadvantage is that this method often results in ESD or EOS damage rather than latch-up. Another problem is one that persists for all very fast changing signals; it is difficult to reproduce precisely in different fixtures or on different equipment. Only broad features of the waveform like peak amplitude and rise-time are controlled while more precise control of the shape would be desirable.
Another type of equipment capable of delivering a stored charge to a V
DD
source is a TLP test system (See ESD Association DSP5.5.2 on Transmission Line Pulse (TLP) testing). The advantage for TLP is the present availability of equipment from several vendors and its nondestructive nature. The higher slew rates attainable on the TLP waveforms will allow characterization of faster classes of transients and extension of the data showing sensitivity of slew rate on trigger level.
Future Directions of the TLU Test Method
The ESD Association DSP5.4 TLU test method provides alternate trigger states that hold promise as a means for ultimately reducing field failures due to electrical transients. CMOS latch-up is a concern today in advanced technologies. Business pressure to scale and reduce costs has lead to designers to take shortcuts. This is impacting chip design, package design and system integrity. Additionally, user plugged accessories (e.g., USB interfaces and battery chargers) lead to transients to occur on power lines. Indeed, system level ESD testing is done to these assemblies to find these problems but it would be useful to be able to anticipate these problems on a chip or board level design.
Latch-up sensitive technologies such as portable electronics, telecommunications, automotive and low power high speed ICs can benefit from the latch-up research and product test.
Investigations into power supply sequencing, common or differential mode noise on multiple supplies, and “hot plugging” could all be simulated with various TLU tests. Furthermore, the isolation schemes used to separate these V
DD
domains on the die can be tested against a number of anomalous signal conditions.
TLU data could be used by product designers to improve simulation models for devices so that investigations like Signal Integrity Analysis can be used to detect latch-up conditions. With
- 52 -

foreknowledge of sensitive devices, PC boards and application circuits can be designed to adequately regulate supply voltages and bypass noise, so that such chips can be used reliably and safely in consumer products.
At present, the ESD Association Standard Practice (SP5.4) on Transient latch-up is well suited to be used as a characterization test. The basic test method provides a structure to base the test procedure on, yet it is flexible enough to be used with any number of alternate waveforms in a search for the optimal trigger. The analyst can choose to use simple fixturing with DC bias or fixture within a system capable of functional vectoring. As a qualification procedure, the test does not provide criteria for pass or fail limits or enough parameters constraining the shape of the trigger waveform to ensure reproducibility.
For the practice to be utilized as a standard, additional data must be compiled to determine if the method is repeatable and reproducible. Data showing the dependence on the transient’s wave shape such as the polarity, rise time, fall time, pulse width or any other parameter would contribute to the understanding greatly.
References
[1] R. Troutman, “Epitaxial Layer Enhancement of N-Well Guard Rings for CMOS Circuits,”
IEEE Trans. On Elec. Dev. Letters, Vol ED-4, pp.438-440, Dec. 1983.
[2] R. R. Troutman, and H.P. Zappe, “ A Transient Analysis of Latch-up in Bulk CMOS,” IEEE
Trans. Elec. Dev., ED-30, pp. 170-179, Feb. 1983.
[3] R. Troutman, “Latch-up in CMOS Technology: The Problem and the Cure,” Kluwer
Publications, 1986.
[4]
Threshold
Newsletter, ESD Association,
September/October, 2003.
[5] TLU Standard Practice Document TLU SP5.4
[6] TLU Working group WG5.4 “Transient Latch Up (TLU) Technical Report 1” Jan 2000
[7] SF Hsu, MD Ker “Dependencies of Damping Frequency and Damping Factor on Bi-Polar trigger waveforms on Transient Induced Latch-up” Paper 2.A.4 ESDA Symposium 2006
[8] O’Connor, Weiss “looking for Latchup” Test and Measurement World magazine, Sept 2003
Reed Bushiness information
[9] JEDEC EIA/JESD 78 “IC Latch Up test” March 1997
[10] Morgan, Hatchard, Mahanpour, “Transient Latch-Up test using a New Bipolar Trigger”
EOS/ESD Proceedings 1999.
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David Swenson and Timothy Maloney
Introduction
Numerous discussions about nanoparticles and nanotechnologies have taken place in industry forums over the past decade or longer. The amazing and far reaching technology is expected to impact nearly every industry, including and perhaps most strikingly, the electronics arena. As of this writing, many of the proposed applications are in the research lab while others are just taking shape in the minds of inventors around the world. The first large scale application of nanoparticle technology appears to be in the production of conductive ink that will pave the way for a wide variety of printed electronics. Printed electronics refers to the production of active and passive components through (relatively) conventional printing techniques, thus eliminating wafer fabrication for some forms of simple transistors or diode related products. Printed electronics is not likely to replace high end applications such as micro-processors or large memory but it does appear that printed systems can fulfill some low to moderate transistor based functions.
Background
Printing processes include conventional off-set, lithographic, rotogravure, ink-jet, laser, screen printing, stencils and other methods of transferring a material to a surface. In any printing process, a fluid or fluid-like substance, generally an ink that carries a pigment (color), is deposited onto a substrate to form an image. Curing or drying is required to set the ink. In many cases, multiple passes are used to create patterns, including application of different colors to create a visible image, reproduce a picture or create some other pattern of interest. Printing is among the oldest chemical and mechanical process created by man.
Printed electronics, up to this point in time, has usually referred to the formation of circuit patterns on rigid or flexible substrates. Circuit patterns are most generally made using screen printing techniques or even stencils. These applications require relatively large and well defined line widths suitable for replication with the bulk printing techniques.
Another type of printing in electronics is the creation of solder interconnects on circuit boards or flexible substrates. Solder pads or bumps are applied using screen printing and stencils and also through micro-dispensing and jetting techniques that are considered a type of printing process.
New inks, formulated with specialty nanoparticles can form conductive patterns on any rigid, semi-rigid, or flexible substrate, including paper. A shortcoming of some conductive inks is the need to use high temperature curing, thus restricting the choice of substrates. A new family of nanoparticle based conductive inks can be cured using a flash of special wave-length light that heats and cures the ink with little thermal impact to the substrate. Thus, even paper could be used as a substrate if it fits the application. Nanoparticle based conductive inks have been successfully applied to form intricate patterns using ink-jet printing equipment. Installation of curing lights immediately following the printing step allows for multiple passes using staged printing heads resulting in fairly high speed processing. Basic transistor and diode structures can be formed in this manner leading to a wide variety of applications.
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Applications
Printed electronics will find application in: visual displays, RFID tags, photovoltaics, lighting, sensors, membrane keypads, toys and novelty items, smart cards and tickets and some active electronics. While the printed electronics area is just beginning to see development, some of the larger volume applications are starting to find their way into the marketplace.
RFID tags include an antenna designed for a specific application range and a chip device that controls the operation. Printing techniques to form the antenna are well understood at this point in time and development of the printed control transistor is well along. Many in the industry expect to see printed RFID tags in wide use by 2008. If process techniques can be streamlined, the cost of RFID tags could rival barcodes in the future. This alone will surely change the retail and commercial market, creating a large scale demand for nanoparticles; although at a probable price point that will challenge the suppliers to find ways to make large volumes of nanoparticles at prices that can support the fledgling industry.
Small visual displays for consumer products are being made today with printed electronics. As techniques and materials improve, printed displays will lead the way for very low cost flat-screen televisions, lighter and thinner portable computers and other equipment where a low cost, low power consumption visual display would be of value. Eventually, printed electronics will allow for very large, high resolution flat panel displays, and even flexible flat-panel displays. Smart shelving and smart packaging also fall into this category. These include small displays that are attached to a shelf in a store or warehouse or onto other items such as pallet loads of product on which pricing or other information can be changed remotely through the use of wireless systems. While this sort of product exists today, printed electronics will reduce the cost sufficiently enough to make the application more attractive to a larger commercial base. Printed electronics could also be used to create electronic advertising in magazines. The possibilities in this area are boundless.
Novelty products will benefit from printed electronics very soon. Items such as talking or musical greeting cards will be easier to make using printed electronic systems. Smart cards and tickets/passes for shows, movies, theater, airline, bus and rail as well as others will eventually be made using printed electronics.
ESD Considerations
A printed transistor operates no differently than a silicon based device so it is expected that the printed version will be susceptible to ESD damage as well. However, line widths and other device geometry will make the printed version quite robust. Even the printing technologies available today do not lend themselves to extremely fine pitches. It would seem likely that line widths of 100’s to 10’s of microns would be about the limit for printing technologies. Particle to particle electrical interaction is needed in conductive inks albeit the thickness of an image could be extremely thin. A major electrostatic challenge will appear in the actual printing process since different dynamics come into play. Depending on the substrate, charge generation could be significant. While this charge may not cause transistor damage, unless it forms in later process steps, it probably will cause more conventional printing problems such as dust and lint attraction, ink separation/repulsion, and image distortion. Ink separation is a common problem but will become significant in conductive structures since separation will likely result in electrical opens.
Ink repulsion could result in electrical shorts in fine line width images.
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If printed electronics becomes able to influence flat-panel displays and photovoltaics, as suggested above, it will be because active devices (transistors) and nonlinear devices (diodes) have been successfully fabricated. This work is ongoing and shows perhaps the most promise with organic semiconductors. Completed printed electronic circuits would likely include both the organic semiconductors and nanoparticle technologies. With this low-cost ability to realize more conventional electronic functions, one can imagine low-cost printed electronic devices being used for ESD protection as well. This would be in much the same way as low-cost polymer electronic devices have been used to protect electronic equipment at certain entry points for
ESD zaps. If printed electronic devices can be shown to have some ability to divert or dissipate
ESD zaps, their low cost will readily justify their use at the platform level.
Ionization systems used in printing applications most often employ bar shaped devices that are placed across the substrate and reside about 1 inch above the actual surface. Electrical and nuclear based ionization are used in printing applications. Since an electronic part is being made in printed electronics, near perfect ion balance will be needed so that no unnecessary induced voltage will be present. Since the charge on the substrate could be quite high
(measured through the electrical field as10 kV or higher), care must be taken to reduce the charge between each printing step so that the conductive ink is deposited on a relatively neutral substrate. This will simultaneously reduce electrostatic attraction issues, ink separation/repulsion, image distortion and the risk of device damage.
Conclusion
Printed electronics will likely become the first major bulk application for nanoparticles. Printing techniques, including ink-jet, will be used to form an incredible array of products. By the year
2008, the costs and efficiencies in producing nanoparticle based printed electronics will displace silicon based electronic applications across industry in high volume, low cost applications. The first significant applications will be in RFID tags, printed displays and novelty items. By 2010, printed electronics should allow creation of very low cost flat-panel displays for a wide variety of commercial and consumer applications.
Development of even slightly advanced electronic functions in printed electronics opens the door to low-cost ESD protection devices that could be used at the platform level.
Electrostatic issues will likely be different in that the processing of printed electronics will require more care during the actual printing operation. Well known industrial techniques will have to be applied to printed electronics.
References
“A Roadmap for Printable Electronics – August 2005” , NanoMarkets, LC, P.O. Box 3840, Glen
Allen, VA 23058
Personal Communication – Nanotechnologies, Inc., 1908 Kramer Lane, Building B, Austin, TX
78758
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Charvaka Duvvury and Steven H. Voldman
As discussed in the preceding chapters there is much that needs to be understood in terms of future ESD reliability and applications. The fundamental effects of ESD will continue to be a challenge albeit reduced anticipated target levels. In fact, without this understanding the complexity of the silicon technology would overtake the impact on ESD design and the ability to maintain the required reliability. Therefore aggressive research to keep up with these demands would be most effective.
This future research can be divided into several crucial areas. Those that deal with topics at the component level and those deal with the system level. The device level topics can be further subdivided into areas of CMOS, Bipolar, SiGe, GaAs, etc. These are explored into specific topics as discussed below.
Component Level ESD Work
A. Silicon Device Level
The most critical issue for exploring the future devices under ESD would require a thorough development of thermal simulation capability for ESD. For example, the 3-dimensional transistors called the MUGFETs (also referred to as FINFETs) described in Chapter 1 are expected to be very sensitive to thermal heating. This would be a very complicated phenomenon where one needs to explore the coupling between the process technology and the transistor geometry to be able to optimize the device. This is especially challenging considering that these devices built on insulators where the thermal effects get further trapped. Other features include the introduction of strain in silicon (now known as strained silicon ) to increase the electron mobility and hence the transistor speed or elevate the transistor junctions (called elevated source drain junctions) or even transistors so far advanced as to be built on nothing
( silicon on nothing ) . Compounding to the device level sensitivity, the metal interconnect plays an equally important role in the heating effects that can constrain ESD design. The more recent advances include carbon nano-tubes . To summarize at the device level, the areas of promising research are in:
• Thermal simulations of multi-gate and 3-D transistors
• Thermal limitations of advanced interconnect including carbon nano-tubes
• Gate oxide ESD reliability for advanced dielectric stacks
Today, bipolar transistors are being utilized for both wired and wireless applications from cell phones to internet data transfer. In these systems, is a wide variety of homo-junction and heterojunction technologies. Significant research is needed in the area of advanced bipolar development. This includes Silicon Germanium (SiGe), Silicon Germanium Carbon (SiGeC),
Gallium Arsenide (GaAs), and Indium Phosphide (InP). As these technologies are developed, revolutionary changes are being made in the material and the physical design of the structures; the radical changes in the physical design can influence the ESD robustness of the structures and have considerable implications to product and system level ESD for RF applications. In addition to the hetero-junction bipolar transistors itself, there are many passive elements which are from the base technology which require an understanding of the ESD sensitivity. For the understanding of ESD robustness of RF communication systems, the devices, circuits and how the devices and circuits interact is greatly needed for the future.
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B. Circuit Level
Often underdeveloped are the circuit level simulations to understand and design for ESD. The circuit designers have not had the proper tools to accurately evaluate the ESD interactions in their circuit applications. The tools are at best an approximation of the particular scenario and are not really predictive in nature. As the circuit designs become more and more complex, the
ESD considerations become critical and have to be recognized in timely manner to avoid conflicting redesigns. At the same time overall chip interactions might very well be even more critical especially considering multiple power domains or the design of system on a chip (SoC).
The circuit level areas of ESD development work might include:
• RF circuit designs to overcome the severe impact from ESD protection schemes
• IO buffer to logic circuit designs to minimize ESD effects
• Full-chip ESD tool to predict ESD current paths
• System on a chip design and power domain interactions during ESD
• Multi-chip Module designs
System Level ESD Research
While the research often is focused on device level for component ESD reliability for HBM or
CDM, there has been very little if any focus on component-system interaction and how it influences system level ESD robustness. For example, the transient interactions of the device and the surrounding parasitic current paths under the IEC pulse can cause complex interactions and device sensitivity. A thermal modeling approach should be very useful to derive the critical design parameters at the chip level to address the system level high current pulse. The other issues of transient latchup (Chapter 11) and cable discharge events (Chapter 10) need to be similarly coupled through device TCAD simulations.
Today, new testing methodologies are needed to quantify the impact of the chip level ESD degradation and how it affects high speed communication systems. Additionally the failure criteria also differ between the chip level and the system. While the chip degradation influences the time-domain reflection (TDR) response, impedance, and leakage, the system level concern parameters are rise time, fall time, and jitter. Hence, the ESD issues on a chip level, are quite distinct from those observed on a system level. With high level integration, the need to develop testing methods, as well as standards that bridge the chip-to-system level interaction will be more important.
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