CSE 20221: Logic Design
Using Verilog in the Xilinx ISE
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Steps in using Xilinx with Verilog
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Create a new project
Determine inputs and outputs
Add a new Verilog source and fill in Inputs/outputs
Enter the description of the circuit
Perform a syntax check
Switch the design view to simulation
Select the design file and add new Verilog test
fixture source
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Select New Source for Design Model
new source icon
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Choose implementation
view
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New Verilog Source File
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Input and Output Declarations
set inputs and
outputs
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Enter Design Model (structure example)
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Boolean Equation Behavioral Model
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Select New Source for Test Fixture
Choose simulation view
new source icon
File associated with
test fixture
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Test Fixture Source Wizard
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Multiple Modules
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Verilog Test Fixture
Note hierarchy
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Spartan 3E Specifications
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Spartan Pricing
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CSE 20221: Logic Design
Using the 4-Digit 7-Segment Display on
the Digilent Basys Board
https://www.digilentinc.com/Data/Products/BASYS2/Basys2_rm.pdf
listed under links in course web site
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LEDs
anode (+)
cathode (-)
current flow
current limiting resistor
Digilent Basys board
Spartan 3E pin out
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Current limiting resistor calculation
• R > (Vcc- Vd) / Idmax
• Assume:
– the led voltage drop, Vd = 1.3 V
– the maximum diode current, Idmax = 10 mA
– the supply voltage, Vcc = 3.3 V
R > 200 Ω
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Seven-Segment Display
• Apply low voltage to cathodes (CA-CG) to select
segments (logic 0 = low voltage on Basys board)
• Apply high voltage to anodes (AN1-AN4) to select digit
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Seven-Segment Display Basys Pin Out
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transistor switches are “p-type”,
assert “0” (low voltage) to turn
them on
assert “0” on pins F12, J12, M13,
K14 to select appropriate digit
assert “0” on pins L14, H12, N14,
N11, P12, L13, M12, L13, M12,
N13 to select appropriate
segments
Need to multiplex cathode data
(more on that in a later lab)
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The Design Process
ANALYSIS
• Interpret the problem statement
• Identify inputs and outputs
• Assign assertion voltage levels
• Develop a high level representation, e.g., block
diagram
DESIGN
• Transform the high level information into
applicable design representation, e.g., truth
table, Boolean equation, schematic, high-level
languages
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Design Process Continued
TESTING
• Simulate – verify and validate behavior
verify – is the functionality correct
validate – does functionality match customer’s intent
• Download design to target device
•verify and validate hardware functionality
TESTING with Verilog
• Simulations should be done for each module
• Simulation of the entire system follows successful
simulation of each module
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Lab 4 Design Problem Statement
• Design a circuit that will display a hex number on
a 7-segment LED display.
• Use Verilog to model the circuit.
• The value of the hex number corresponds to its
binary equivalent value represented by the
position of four switches: sw3, sw2, sw1, sw0.
• sw3 is msb (most significant bit) and sw0 is lsb
(least significant bit)
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Identify Inputs and Outputs
• Inputs: sw0, sw1, sw2, sw3
• Outputs: a, b, c, d, e, f, g, anode1
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Block Diagram
• A block diagram is a top-level representation of
the overall system which includes:
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inputs / outputs
major functional units
interconnections between units
interconections to external world (hardware interface)
• Block diagrams provide a
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means to communicate between designers
way to make a complex system more understandable
way to partion functionality
mechanism to conceptualize a design concept
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Block Diagram
SW3
0v
interface
SW2
SW1
5v
SW0
BCD to 7-segment
decoder
ab c d e f g
interface
pull-up resistor
can be subdivided
into additional blocks
A pull-up resistor forces the voltage at the input to equal 5 v when the
switch is open. The input shouldn’t be left to “float”, which can cause
erratic values.
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Translate to Design Format
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Truth table
Karnaugh map
Schematic
HDL
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Simulation
• Verification – does the circuit simulate according
to its intended design?
• Validation – does the circuit function according to
what the customer wanted?
• Make any necessary design changes to correct
any invalid behavior
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Prototype
• Download design to prototype board
• Verify correct functionality
• Repeat necessary design steps to correct any
problems
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Design: An Iterative Process
• The design process is often presented as a
sequence of well organized steps
• In reality, design is an iterative process:
– cyclic, i.e., revisit the different steps:
• analysis
• design
• testing: verification and validation
• A product “evolves” over several design and
product iterations
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Homework
Using the Xilinx ISE, create a Verilog model for the g
segment of a seven-segment display, where the value for
the segment must be set to 0 for the LED to light (active
low). Your circuit must display a hex number, i.e., 0, 1 …
8, 9, A, b, c, E, and F. Submit a text file printout of your
Verilog .v file and a printout of your simulation results.
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