IRFP9240
Data Sheet
January 2002
12A, 200V, 0.500 Ohm, P-Channel Power
MOSFET
This P-Channel enhancement mode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdown avalanche mode of operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.
Features
• 12A, 200V
• rDS(ON) = 0.500Ω
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
Symbol
Formerly developmental type TA17522.
D
Ordering Information
PART NUMBER
IRFP9240
PACKAGE
TO-247
G
BRAND
IRFP9240
S
NOTE: When ordering, use the entire part number.
Packaging
JEDEC STYLE TO-247
SOURCE
DRAIN
GATE
DRAIN
(TAB)
©2002 Fairchild Semiconductor Corporation
IRFP9240 Rev. B
IRFP9240
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
TC = 125oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
IRFP9240
-200
-200
-12
-7.5
-48
±20
150
1.2
790
-55 to 150
UNITS
V
V
A
A
A
V
W
W/oC
mJ
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
PARAMETER
BVDSS
ID = -250µA, VGS = 0V (Figure 10)
-200
-
-
V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = -250µA
-2.0
-
-4.0
V
-
-
25
µA
-
-
250
µA
-12
-
-
A
Zero Gate Voltage Drain Current
SYMBOL
IDSS
TEST CONDITIONS
VDS = Rated BVDSS, VGS = 0V
VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC
On-State Drain Current (Note 2)
Gate to Source Leakage Current
Drain to Source On Resistance (Note 2)
Forward Transconductance (Note 2)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
(Gate to Source + Gate to Drain)
Gate to Source Charge
ID(ON)
IGSS
rDS(ON)
gfs
td(ON)
tr
td(OFF)
VDS > ID(ON) x rDS(ON)MAX, VGS = -10V
VGS = ±20V
-
-
±100
nA
ID = -6.3A, VGS = -10V (Figures 8, 9)
-
0.380
0.500
Ω
VDS ≤ -50V, ID = -6.3A (Figure 12)
3.8
5.7
-
S
VDD = -100V, ID ≈ -12A, RG = 9.1Ω,
VGS = -10V, RL = 7.6Ω, (Figures 17, 18)
MOSFET Switching Times are Essentially Independent of Operating Temperature
-
18
22
ns
-
45
68
ns
-
75
90
ns
-
29
44
ns
VGS = -10V, ID = -12A, VDS = 0.8 x Rated BVDSS
Ig(REF) = -1.5mA (Figures 14, 19, 20)
Gate Charge is Essentially Independent of Operating Temperature
-
38
57
nC
-
8
-
nC
tf
Qg(TOT)
Qgs
Gate to Drain “Miller” Charge
Qgd
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = -25V, VGS = 0V, f = 1MHz
(Figure 11)
Internal Drain Inductance
LD
Measured From the Contact Screw on Header
Closer to Source and Gate
Pins to Center of Die
Internal Source Inductance
LS
Measured From the
Source Pin, 6mm (0.25in)
From Header to Source
Bonding Pad
Modified MOSFET
Symbol Showing the
Internal Devices
Inductances
D
-
21
-
nC
-
1400
-
pF
-
350
-
pF
-
140
-
pF
-
5.0
-
nH
-
12.5
-
nH
-
-
0.83
oC/W
-
-
30
oC/W
LD
G
LS
S
Thermal Resistance Junction to Case
RθJC
Thermal Resistance Junction to Ambient
RθJA
©2002 Fairchild Semiconductor Corporation
Free Air Operation
IRFP9240 Rev. B
IRFP9240
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Continuous Source to Drain Current
TEST CONDITIONS
ISD
Pulse Source to Drain Current
(Note 3)
Modified MOSFET Symbol
Showing the Integral Reverse P-N Junction Rectifier
ISDM
MIN
TYP
MAX
UNITS
-
-
-12
A
-
-
-48
A
-
-
-1.5
V
-
210
-
ns
-
2.0
-
µC
D
G
S
Source to Drain Diode Voltage (Note 2)
Reverse Recovery Time
Reverse Recovery Charge
VSD
TJ
trr
TJ
QRR
TJ
= 25oC, ISD = -12A, VGS = 0V, (Figure 13)
= 25oC, ISD = -11A, dISD/dt = 100A/µs
= 25oC, ISD = -11A, dISD/dt = 100A/µs
NOTES:
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 50V, starting TJ = 25oC, L = 8.2mH, RG = 50Ω, peak IAS = 12A (Figures 15, 16).
Typical Performance Curves
Unless Otherwise Specified
15
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
0.2
12
9
6
3
0
0.0
0
25
50
75
100
TC , CASE TEMPERATURE (oC)
125
150
25
75
50
125
100
150
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
1
ZθJC, NORMALIZED
THERMAL IMPEDANCE
0.5
0.2
0.1
0.1
0.05
PDM
0.02
0.01
10-2
t1
t2
SINGLE PULSE
10-3
10-5
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
10-4
0.1
10-3
10-2
t1, RECTANGULAR PULSE DURATION (S)
1
10
FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2002 Fairchild Semiconductor Corporation
IRFP9240 Rev. B
IRFP9240
Typical Performance Curves
Unless Otherwise Specified (Continued)
-103
20
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
-102
100µs
1ms
-10
10ms
OPERATION IN THIS
AREA IS LIMITED
BY rDS(ON)
DC
-1
-1
VGS = -7V
16
12
VGS = -6V
8
VGS = -5V
4
TJ = MAX RATED
SINGLE PULSE
-0.1
VGS = -4V
-10
-102
VDS, DRAIN TO SOURCE VOLTAGE (V)
0
-103
0
-102
VGS = -10V
16
ID, DRAIN CURRENT (A)
VGS = -8V
12
VGS = -7V
8
VGS = -6V
4
40
60
80
100
FIGURE 5. OUTPUT CHARACTERISTICS
20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
20
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
ID, DRAIN CURRENT (A)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = -10V
VGS = -8V
10µs
VGS = -5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDS ≤ -50V
-10
TJ = 150oC
TJ = 25oC
-1.0
VGS = -4V
0
0
2
4
8
6
10
-0.1
0
-2
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 6. SATURATION CHARACTERISTICS
3.0
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (Ω)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
4
3
VGS = -10V
2
1
VGS = - 20V
0
-10
-30
-20
ID, DRAIN CURRENT (A)
-40
-6
-8
-10
FIGURE 7. TRANSFER CHARACTERISTICS
5
0
-4
VGS, GATE TO SOURCE VOLTAGE (V)
2.4
1.8
1.2
0.6
0
-50
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = -10V, ID = -6.3A
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
NOTE: Heating effect of 2µs pulse is minimal.
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
©2002 Fairchild Semiconductor Corporation
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
IRFP9240 Rev. B
IRFP9240
Typical Performance Curves
3000
ID = 250µA
1.15
C, CAPACITANCE (nF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.25
Unless Otherwise Specified (Continued)
1.05
0.95
VGS = 0V, f = 1MHz
CISS = CGS + CGD
2400 CRSS = CGD
COSS ≈ CDS + CGD
1800
CISS
1200
COSS
0.85
600
CRSS
0.75
-40
0
40
80
120
0
160
-1
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
-5
-10
-2
-5
VDS, DRAIN TO SOURCE VOLTAGE (V)
-102
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10
-100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDS ≤ -50V
8
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ISD, DRAIN CURRENT (A)
gfs, TRANSCONDUCTANCE (S)
-2
TJ = 25oC
6
TJ = 150oC
4
2
0
0
-4
-8
-12
-16
TJ = 150oC
-1.0
-0.1
-0.4
-20
-0.6
I D , DRAIN CURRENT (A)
VGS, GATE TO SOURCE (V)
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
VSD, SOURCE TO DRAIN VOLTAGE (V)
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT
20
TJ = 25oC
-10
FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
ID = -12A
VDS = -160V
16
VDS = -100V
VDS = -40V
12
8
4
0
0
12
24
36
48
60
Qg(TOT), TOTAL GATE CHARGE (nC)
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
©2002 Fairchild Semiconductor Corporation
IRFP9240 Rev. B
IRFP9240
so
Test Circuits and Waveforms
VDS
tAV
L
0
VARY tP TO OBTAIN
-
RG
REQUIRED PEAK IAS
+
VDD
DUT
0V
VDD
tP
VGS
IAS
IAS
VDS
tP
0.01Ω
BVDSS
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
tON
tOFF
td(OFF)
td(ON)
tr
0
-
DUT
VGS
VDS
VDD
90%
90%
VGS
0
+
10%
10%
RL
RG
tf
10%
50%
50%
PULSE WIDTH
90%
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 17. SWITCHING TIME TEST CIRCUIT
-VDS
(ISOLATED
SUPPLY)
CURRENT
REGULATOR
0
VDS
DUT
12V
BATTERY
0.2µF
50kΩ
0.3µF
Qgs
Qg(TOT)
DUT
G
VGS
Qgd
D
VDD
0
S
Ig(REF)
IG CURRENT
SAMPLING
RESISTOR
0
+VDS
ID CURRENT
SAMPLING
RESISTOR
FIGURE 19. GATE CHARGE TEST CIRCUIT
©2002 Fairchild Semiconductor Corporation
Ig(REF)
FIGURE 20. GATE CHARGE WAVEFORMS
IRFP9240 Rev. B
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FAST 
FASTr™
FRFET™
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GTO™
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MicroPak™
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Power247™
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QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER 
SMART START™
STAR*POWER™
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SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
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STAR*POWER is used under license
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DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
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systems which, (a) are intended for surgical implant into
support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4