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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 5, MAY 2008
A Universal UHF RFID Reader IC
in 0.18-µm CMOS Technology
Pradeep Basappa Khannur, Senior Member, IEEE, Xuesong Chen, Dan Lei Yan, Dan Shen,
Bin Zhao, M. Kumarasamy Raja, Ye Wu, Rendra Sindunata, Wooi Gan Yeoh, Member, IEEE, and
Rajinder Singh, Member, IEEE
Abstract—A highly integrated UHF RFID reader IC in 0.18- m
CMOS process covering the entire 860 MHz to 960 MHz RFID
band supporting the EPCglobal™ Class-1 Generation-2 and
ISO-18000-6A/B/C standards is presented. The IC features a
transmitter with an output of 10 dBm and a receiver with
sensitivity of 96 dBm in listen-before-talk mode (LBT) and
85 dBm in talk-mode. Direct-conversion architecture is used
for the receiver for a high level of integration and low power consumption. On-chip dual-loop synthesizer generates high-purity
LO signal with frequency resolution of 50 kHz and phase noise of
101 dBc/Hz at 100 kHz offset over the entire 860 to 960 MHz
band. The IC integrates 10-bit DACs, pulse-shaping filters, an
IQ modulator and a power amplifier in the transmit chain and a
low-noise amplifier (LNA), an IQ downconverter, channel-select
filters, variable-gain amplifiers and 10-bit ADCs in the receive
chain. On-chip ASK demodulator provides demodulated I and Q
6 mm. It
raw data outputs. The chip has a die area of 6 mm
operates over a wide range of voltage and temperature, from 1.6 V
to 2.0 V and from 25 C to 75 C and consumes 540 mW from
a 1.8 V supply at 25 C.
reader receiver sensitivity in the presence of self-jammer signal
and location of the tag [1]. Near-field inductive-loop passive
RFID systems, which operate at the low-frequency (LF) of either 125 or 134 kHz or high frequency (HF) of 13.56 MHz, are
limited to a read-range of approximately 1 m. Ultra-high frequency (UHF) RFID systems operate in the Industrial–Scientific–Medical (ISM) bands between 860 and 960 MHz. They
have much longer read range of 3 m to 10 m for a passive tag.
EPCglobal™ Class-1 Generation-2 [2] and ISO 18000-6C [3]
are the important governing UHF (860 MHz to 960 MHz) RFID
standards, which define the air interfaces, being widely adapted
by the industry. The regulations, ETSI EN 302 208–1 [4] in Europe and FCC Title 47, Part 15 [5] in United States of America,
define limitations on spurious emissions. These universal air interface standards and regulations along with the advancement
in tag technology are helping the widespread adoption of UHF
RFID systems.
Index Terms—Backscatter modulation, CMOS,
transponder, reader, RFID, RFID interrogator, UHF.
A. Components of a UHF RFID System
+
+
+
passive
I. INTRODUCTION
R
ADIO-FREQUENCY identification (RFID) is probably
the best choice for automatic identification, which calls
for non-line-of-sight, wireless, contactless, high data rate, multiple tag identification, lowest operating cost, long read range,
operation in dirt/damp environment and re-programmability of
the tag. At present the cost of the RFID system, especially that
of tag, is the main concern for replacing barcode systems. Once
the cost of a tag approaches that of a barcode, RFID may replace barcode in most of the barcode applications and will also
lead to emergence of newer applications. A few promising applications of RFID are supply chain management, access control,
airport baggage handling, auto registration, non-stop toll collection, theme parks, etc.
The read/write range performance of a RFID system depends
mainly on the choice of frequency, radiated power from the
reader, sensitivity of tag, tag’s modulation efficiency, data rate,
Manuscript received September 14, 2007; revised February 8, 2008.
The authors are with the Institute of Microelectronics, A*STAR, Singapore
Science Park II, Singapore, 117685 (e-mail: pradeep@ime.a-star.edu.sg,
khannur@ieee.org; chenxs@ime.a-star.edu.sg; yandl@ime.a-star.edu.sg;
mars_shen9385_cn@sina.com; zhaobin@ime.a-star.edu.sg; raja@ime.a-star.
edu.sg; maggie.wuyeus@gmail.com; rendra@ime.a-star.edu.sg; wooigan@
ime.a-star.edu.sg; rajinder@auxineon.com).
Digital Object Identifier 10.1109/JSSC.2008.920355
A UHF RFID system consists of reader(s), tag(s) and a
computer (optional) as shown in Fig. 1. The reader(s) sends
information to one or more tags by modulating an RF carrier
using double-sideband amplitude-shift-keying (DSB-ASK),
single-sideband amplitude-shift-keying (SSB-ASK) or
phase-reversal amplitude-shift-keying (PR-ASK) modulation
at a bit rate ranging from 26.7 to 128 kbps [2], [3]. Modulation
is achieved using a pulse-interval-encoding (PIE) format. Here,
data is passed to the tag by pulsing carrier wave at differing
time intervals to indicate a 0 or 1. The tag receives both the
information and the operating energy from the reader’s RF
signal. If the tag lies within the reader’s range, an alternating
RF voltage is induced on the tag antenna which is rectified
to provide a direct current (DC) supply voltage for the tag’s
operation. The tag responds by modulating the impedance
placed on the antenna terminals. In doing so, it backscatters an
information signal to the reader. The reader demodulates and
decodes the tag’s data.
B. Problem of Self-Jammer at the Reader Receiver Input
A passive UHF RFID system is a half duplex system [1].
The biggest differentiator of an RFID transceiver is the requirement to handle large transmitter leakage during tag reception
[6] which calls for the design of a wide dynamic range receiver
with a very high input 1-dB compression point. Other option is
to use some sort of self-jammer cancellation technique, which
can be realized either on-chip [7] or off-chip. Reader IC presented in this paper requires external self-jammer cancellation
0018-9200/$25.00 © 2008 IEEE
KHANNUR et al.: A UNIVERSAL UHF RFID READER IC IN 0.18-µm CMOS TECHNOLOGY
1147
Fig. 1. Simplified block diagram of an UHF RFID system.
Fig. 2. Chip architecture.
scheme for long range applications when the transmitted power
is 30 dBm as the receiver cannot handle more than 10 dBm
of self-jammer signal.
This paper describes UHF RFID reader IC architecture and
implementation in 0.18- m CMOS process, which is designed
for short-range (1–2 m) applications. Sections II and III describe
the chip architecture and key building blocks, respectively. In
Section IV, performance of the IC and complete reader module
with an external power amplifier, a microcontroller IC, reference
crystal oscillators, a directional coupler are presented. Conclusions are provided in Section V.
II. CHIP ARCHITECTURE
The chip architecture is shown in Fig. 2. The transmitter part
consists of 10-bit digital-to-analog converters (DAC), pulse
shaping filters (PSF) for I and Q channels, an IQ modulator, and
a linear Class-A power amplifier. A dual-loop phase-locked
loop (PLL) synthesizer with voltage-controlled oscillators
(VCOs) is integrated on the same chip. The IC communicates
with the external world using a serial peripheral interface (SPI).
Dual-loop synthesizer together with passive RC polyphase filter
generates the desired frequency in the form of in-phase (I) and
quadrature-phase (Q) components for feeding to transmit chain
for modulation and to receive chain for direct down-conversion.
I and Q transmit data from the baseband are fed to 10-bit
DACs. Various modulations namely, DSB-ASK, PR-ASK or
SSB-ASK, as desired by the standards [2], [3], are generated
by feeding proper data bits to 10-bit DACs (I and Q). Tunable
PSFs with selectable cut-off frequencies, 40 kHz, 80 kHz or
160 kHz, help to shape the waveform to meet stringent transmit
mask requirement as specified by ETSI EN 302 208–1 [4] and
FCC Title 47, Part 15 [5]. The modulated signal is amplified by
the linear Class-A power amplifier to 10 dBm.
The receiver uses a direct-conversion architecture to move the
self-jammer to DC at the output of the mixer for removal. The
receiver front-end is designed to achieve high sensitivity in the
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 5, MAY 2008
Fig. 3. Dual-loop PLL synthesizer architecture.
LBT mode and a high input 1-dB compression point in the talkmode. Since the receiver is direct-conversion, fully-differential
architecture is chosen from the output of the low-noise amplifier (LNA) onwards. The receiver input is kept single-ended to
avoid use of any external balun. The IQ downconversion mixer
outputs are AC coupled to block the DC offset, which provides
high pass characteristics. Settling time becomes critical since
the reading of a tag has to happen in a short time. The RFID
protocols specify quite short preambles compared to other communication protocols. The value of DC blocking capacitor is
chosen depending on the data rate of the tag. Before feeding
the channel-select filter (CSF), the signal is first amplified by
12 dB. For low tag data rates and in LBT mode, 330 kHz CSF
bandwidth is chosen and for higher data rates, say 640 kbps,
1.5 MHz CSF bandwidth is chosen. The variable-gain amplifier
(VGA), which follows the channel-select filter, provides gain
control of 47 dB in 1 dB step. The output of VGA is demodulated by ASK demodulator, which provides raw digital data for
processing in the microcontroller. 10-bit ADCs provide parallel
digital outputs for further processing by digital signal processor
(DSP), if desired.
III. KEY READER IC BUILDING BLOCKS
A. Dual-Loop PLL Synthesizer
Due to the stringent spectrum mask requirement [4], [5] for
the transmitter and very good sensitivity for the receiver, the
design of synthesizer for good phase-noise and low spur levels
becomes more critical for UHF RFID reader. The design here
focus on achieving good phase-noise and low spur levels with
frequency resolution of 50 kHz over the entire 860 to 960 MHz
band. Dual-loop PLL architecture, as shown in Fig. 3, is chosen
for synthesizer [8] for ease of implementation and to achieve
first time success in silicon implementation though this architecture has the following disadvantages: higher spurs, more die
area and higher power consumption, compared to fractional-N
synthesizer. Design and layout are optimized to meet overall
reader requirements. Dual-loop PLL synthesizer includes two
integer-N synthesizers and one SSB mixer. Output frequency of
Synthesizer-1 can be calculated using the relation
MHz
and are the programmable- and swallow-counter values of
Synthesizer-1, respectively. Frequency range of Synthesizer-1
is from 2020 to 2220 MHz. Similarly, the output frequency of
Synthesizer-2 can be calculated using the relation
kHz
and
are the programmable- and swallow-counter values
of Synthesizer-2, respectively. The frequency range of Synthesizer-2 is from 2400 MHz to 2560 MHz. Before feeding to the
SSB mixer Synthesizer-1’s frequency is divided by 2 and that of
Synthesizer-2 by 16. Hence, after division, phase noise of Synthesizer-1 and Synthesizer-2 improves by 6 dB and 24 dB, respectively. After mixing the divided outputs from Synthesizer-1
and Synthesizer-2 in the SSB mixer, lower-sideband signal from
KHANNUR et al.: A UNIVERSAL UHF RFID READER IC IN 0.18-µm CMOS TECHNOLOGY
1149
Fig. 4. Schematic diagram of VCO1.
860 to 960 MHz with a frequency resolution of 50 kHz is obtained and unwanted upper-sideband is suppressed. The frequency of the desired lower-sideband signal at the output of SSB
mixer is obtained using the relation
Measurement shows the upper-sideband suppression greater
than 37 dB and is further suppressed in the full-chip, by IQ
modulator and PA as they are tuned for 860 to 960 MHz frequency band. Measured inter-modulation spur levels are better
than 50 dBc, which needs further improvement.
The following subsections explain key building blocks of
dual-loop PLL synthesizer.
1) Voltage-Controlled Oscillator: The complementary
cross-coupled differential topology [9], [10] is adopted in the
design of both the VCOs to get more linear tuning range. Fig. 4
shows the schematic diagram for VCO1 used in Synthesizer-1.
It is this topology, with attention to symmetry on both the full
circuit and each half circuit, reduces the phase noise. In order
to improve the phase-noise further and reduce reference spur
levels, tuning sensitivity has been reduced by using multiple
bands for VCOs. The VCO1’s tuning sensitivity is 80 MHz/V.
The VCO1 has eight bands and the desired band can be selected through controls Va to Vc. Va to Vc are used to control
binary-coded accumulation-mode MOS varactors (C1 to C3).
Similarly, the VCO2 is designed with four bands and has a
tuning sensitivity of 150 MHz/V. As the frequency division
ratio of VCO1 output is smaller than that of VCO2 output,
phase noise of VCO1 becomes more critical for output signal’s
phase noise. In order to get low phase noise, VCO1 is biased
with 12 mA current and an external capacitor is shunted to
current source in order to bypass the flicker noise.
2) PFD and Charge-Pump: A dead-zone free classic phase
frequency detector (PFD) is employed for phase and frequency
comparison to ensure a wide lock range. The charge-pump current sources are controlled by PFD output to deliver the right
Fig. 5. Schematic diagram of charge-pump circuit.
amount of charge to the loop filter. Ideally, if the charge-pump
up and down currents ( and ) are equal, no leakage charge is
injected in loop filter. Due to device mismatch, channel length
modulation effect and charge leakage, there is always a disparity
in up and down charge-pump currents. This leads to high reference spurious tones at VCO output. By optimally choosing
the size of the switches of charge-pump [11], injected charge of
PMOS is made equal to the injected charge of NMOS so that the
net overlap charge injection is zero. In Fig. 5, A1 forms a dynamic feedback loop, so the
and
would have
the same voltage. The feedback loop will regulate
and ensure
is equal to . To achieve better in-band phase-noise,
large charge-pump current of 1.2 mA is used. The loop filters
are kept external to the chip for both the PLL synthesizers for
more flexibility. Measured reference spur levels are lower than
55 dBc.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 5, MAY 2008
Fig. 8. Block diagram of preamplifier with DC offset cancellation.
Fig. 6. Block diagram of receiver RF front-end.
Fig. 7. Schematic diagram of LNA.
B. Receive Path
1) Receiver RF Front-End: As shown in Fig. 6, in the LBT
mode a 12 dB attenuator is bypassed to achieve a receiver sensitivity of better than 96 dBm. In the talk-mode the attenuator
is brought in to improve the input 1-dB compression point by
12 dB to handle self jammer signal up to 10 dBm. This decreases the sensitivity by 12 dB in talk-mode achieving around
85 dBm, which is sufficient (assuming tag’s sensitivity is
15 dBm). The LNA consists of two stages as shown in Fig. 7.
The first stage is the gain stage which uses single-ended cascode
topology with source degeneration and the second stage is a
unity-gain active single-to-differential stage, whose outputs are
fed to double-balanced I and Q passive mixers as RF inputs. To
achieve low 1/f noise and good linearity, passive mixers [12]
have been used, which also help to save power and area. The
outputs of the IF buffer are AC-coupled to the inputs of the
12 dB IF preamplifier, which is followed by CSF and VGA.
2) Preamplifier, Channel-Select Filter and Variable-Gain
Amplifier:
a) Preamplifier: The preamplifier stage consists of three
main blocks namely fixed-gain voltage amplifier, adder and
Gm-C cell as shown in Fig. 8. The fixed gain circuit provides
a 12 dB gain. To cancel the DC offset, Gm-C cell is used as a
simple low pass filter that feeds back the output DC offset to the
adder to subtract the DC components of the input signal. Gm-C
filter can provide high gain to the cancellation loop while consuming small current (a few A) [13]. A large capacitance is
required to keep the cutoff frequency of the low pass filter low.
The fixed-gain amplifier is designed based on the differential
pair with diode connected load.
b) Channel-Select Filters: In order to obtain reduced sensitivity to the inherent variations in the process, the CSF is designed using ladder filter architecture with integrator based approach [14] as shown in Fig. 9. The pole locations of the filter are
chosen to implement a Chebyshev transfer function with 0.5 dB
passband ripple and to provide attenuation at desired frequencies. The CSF is able to configure the order of the filter between
fourth order for 1.5 MHz cutoff frequency and seventh order for
330 kHz cutoff frequency. This serves to adapt to the talk-mode
and LBT mode respectively.
c) Variable-Gain Amplifier: The VGA provides gain adjustment from 0 dB to 47 dB in 1 dB gain step. It is composed of
coarse gain and fine gain stages [15]. The coarse gain stage consists of five fixed-gain amplifiers with each of them providing
8 dB of gain. The gain can be adjusted in 8 dB step, over 40 dB
gain range, by selecting one of the outputs of the fixed-gain amplifier. The fine gain is realized by an op-amp with resistive
feedback configuration. By controlling the ratio of the feedback
resistors using switches, the gain can be adjusted in 1 dB step
over 7 dB gain range.
The RSSI circuit detects the strength of the input in dB and
is used to control the VGA gain. Successive detection architecture is adopted for realizing the logarithmic amplifier [16]. The
measured dynamic range of the RSSI is 50 dB and the detection
error is less than 1.5 dB.
A high swing comparator is used for ASK demodulation. The
10-bit I and Q ADCs use pipe-lined architecture as the conversion rate is 10 MSPS.
C. Transmit Path
1) 10-Bit DACs, Pulse-Shaping Filters: Current-steering
10-bit DACs are implemented for low power consumption
without sacrificing the required performance. The PSF immediately follows the DAC and serves two purposes: shaping
the baseband waveform so that its spectrum fits well into the
transmit mask, and removing the spectral spur introduced by the
DAC. A fifth-order low-pass-filter is realized using three stages
of biquad structures. First two stages realize four poles, which
KHANNUR et al.: A UNIVERSAL UHF RFID READER IC IN 0.18-µm CMOS TECHNOLOGY
1151
Fig. 9. Schematic diagram of channel-select filter.
Fig. 10. Schematic diagram of power amplifier with power control.
are Chebyshev and the last stage constitutes a Butterworth pole.
The filter is switchable and selects one of the three pass bands,
40, 80, or 160 kHz for 0.5 dB bandwidth.
2) IQ Modulator and Power Amplifier: Care is taken in design and layout of the IQ upconversion mixer to ensure that
the noise within the signal band is minimized. The Gilbert-cell
mixers are used for I and Q mixers. Both I and Q sections of the
modulator are used for generating SSB-ASK modulation. The
linear Class-A power amplifier [17] shown in Fig. 10 amplifies
the signal to 10 dBm. Single stage cascode structure is chosen
for better isolation from output to input. The input transistor M1
is biased to operate in Class-A mode. M2 is self biased from the
output through R1 and C3, which helps to improve the linearity
[18]. The power amplifier has output 1-dB compression point
of 11 dBm and power added efficiency of 16%. The output
power is programmable from 5 dBm to 10 dBm. It needs to
be mentioned here that the power amplifier is operated at 5 dB
back-off from its output 1-dB compression point as the input is
ASK modulated signal.
IV. MEASURED RESULTS
The reader IC was fabricated using a standard 0.18- m
CMOS process in a commercial foundry. The IC was packaged in a low-cost commercial TQFP100 package (14 mm
14 mm). The IC performance was evaluated separately on FR4
board from 25 C to 75 C. Measured talk-mode sensitivity
is 85 dBm for 40 kbps, 1% packet error rate (PER) with
self-jammer power of 16.5 dBm. For 100 kbps data rate, the
transmit spectrum mask for multiple interrogator environment
meets the EPC Class-1 Gen-2 standard as shown in Fig. 11.
PSF characteristics for 40 and 80 kHz bandwidth selections are
shown in Fig. 12. Measured carrier phase-noise at 910 MHz
is shown in Fig. 13, which is 101 dBc/Hz at 100 kHz offset.
Carrier phase-noise is consistent over the entire band, 860
to 960 MHz [19]. All the modulations namely, DSB-ASK,
PR-ASK, and SSB-ASK are supported [19]. The modulation
depth can be programmed from 10% to 100%. Standalone CSF
response has been measured for LBT mode and talk-mode,
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 5, MAY 2008
Fig. 11. Measured transmit mask for multiple interrogator environment at
100 kbps data rate.
Fig. 14. Chip microphotograph (Die size: 6 mm
2 6 mm).
Fig. 12. Measured PSF characteristics for 40 kHz and 80 kHz bandwidth
selections.
Fig. 15. Complete UHF RFID reader module (Board size: 78 mm
Fig. 13. Measured carrier phase-noise from TX output at 910 MHz.
which match the design very well [19]. The measured INL and
DNL of ADCs are 1.3 LSB and 0.55 LSB, respectively. The
chip microphotograph is shown in Fig. 14, which measures
6 mm
6 mm. The UHF RFID reader IC presented in this
2 50 mm).
paper is compared with other recently published works and
summarized in Table I.
The UHF RFID reader IC presented in this paper is used
to build a credit card size reader module on a two-layer FR4
PCB as shown in Fig. 15. Other side of board is used as a
ground plane. An external power amplifier is used to boost the
transmit power to 18.5 dBm. The antenna used in the reader
system has a gain of 6 dBic. Three commercial RFID tags of different standards have been tested for read range performance at
24.5 dBm effective isotropic radiated power (EIRP) and compared with a commercial discrete UHF RFID reader as shown
in Table II. The performance is very close to that of a discrete
reader.
V. CONCLUSION
The performance of a 0.18- m CMOS passive UHF RFID
reader IC covering the entire 860 MHz to 960 MHz has
KHANNUR et al.: A UNIVERSAL UHF RFID READER IC IN 0.18-µm CMOS TECHNOLOGY
1153
TABLE I
UHF RFID READER ICS PERFORMANCE COMPARISON
TABLE II
READER MODULE RANGE PERFORMANCE RESULTS—WITH
been presented at the chip level and complete reader module
level. It has been demonstrated that the transmitter generates 10 dBm power with selectable modulations namely
DSB-ASK, PR-ASK, SSB-ASK, with programmable modulation depth and power. The receiver has a sensitivity of 96 dBm
in the LBT mode and 85 dBm in the talk-mode for 40 kbps.
The IC meets the requirements as specified in the standards,
EPCglobal™ Class-1 Generation-2 and ISO-18000-6A/B/C.
It has been shown that performance of the reader module,
built using the presented reader IC, matches very closely with
+24.5 dBm EIRP
the commercial discrete readers. Thus, the RFID reader IC
presented will help in wide deployment of UHF RFID systems,
where the cost and the size of the UHF reader module are
critical.
ACKNOWLEDGMENT
The authors wish to acknowledge Aruna B. Ajjikuttira, Chee
Hong Yong, Haiqi Liu, and the layout engineers for their contributions. The authors also wish to thank Chip Hong Ang and
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 5, MAY 2008
Sio Peng Goi for the reader module development using the presented UHF RFID reader IC and providing performance comparison with a fully discrete reader module, and the anonymous
reviewers for their critical and useful comments.
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[20] I. Kwon, H. Bang, K. Choi, S. Jeon, S. Jung, D. Lee, Y. Eo, H. Lee, and
B. Chung, “A single-chip CMOS transceiver for UHF mobile RFID
reader,” in 2007 IEEE Int. Solid-State Circuits Conf., San Francisco,
CA, Feb. 2007, pp. 216–598.
Pradeep Basappa Khannur (M’01–SM’03) was
born in Dharwad, Karnataka, India, in 1964. He
received the B.E. degree in electronics and communication from Karnatak University, Dharwad, India,
in 1985, and the M.Sc. degree with specialization in
integrated circuit design from the Nanyang Technological University, Singapore, in 2007.
He joined Bharat Electronics Limited, Bangalore,
India, in December 1986, where he was involved
in the development of C-band monopulse radar
for Indian space and defense applications and was
conferred the R&D Award for his contributions. He joined Tritech Microelectronics Limited, Singapore in June 1997 as a Senior Design Engineer, where he
was involved in active RFID tag IC development and ATE hardware design for
testing the same. In February 2000, he joined the Institute of Microelectronics
(IME), A*STAR, Singapore, as a Research Engineer, and since then he has
worked on numerous CMOS RF IC development projects such as Bluetooth,
2.45 GHz cordless phone IC, 2.45 GHz passive RFID tag IC, multi-band
RFID reader IC, and 900 MHz passive UHF RFID reader IC. Currently, he
is a Member of Technical Staff at IME and leading the UHF RFID reader IC
design and development team. He has four filed/granted U.S. patents and has
authored or co-authored five papers. His interests include CMOS RF IC design
for wireless communications, RF IC architectures and their building block
integrations.
Xuesong Chen was born in Hubei, China, in 1976.
He received the B.E. degree in electronic information engineering from the University of Science and
Technology of China, Hefei, China, in 1999, and the
M.S. degree in computer science from the National
University of Singapore, Singapore, in 2002.
From 1999 to 2001, he was with the Institute
for Infocomm Research working on 3-D medical
imaging modeling. From 2001 to 2004, he was
with Singapore Technologies Electronics working
on satellite and microwave transceivers design. In
2005, he joined the Institute of Microelectronics, Singapore, to work as a RFIC
engineer, mainly focused on CMOS transceiver architecture and circuits design.
Dan Lei Yan received the B.E. degree in electrical
engineering from TanJin University, TianJin, China,
in 1994, and the M.S. degree in electrical engineering
from Nanyang Technological University, Singapore,
in 2004.
He was a Senior Analog Design engineer with
AIWA Singapore Electronics Ltd. from 1997 to
2001. He was with Agilent Singapore Ltd. as a
Senior Design Engineer from 2002 to 2005. He is
now a Research Engineer in Integrated Circuits and
Systems Laboratory, Institute of Microelectronics,
A*STAR, Singapore. His current interests are research and development of
CMOS low-power, low-noise fractional-N synthesizer, CMOS optical clock and
data recovery circuits, and CMOS RF IC design for wireless communications.
KHANNUR et al.: A UNIVERSAL UHF RFID READER IC IN 0.18-µm CMOS TECHNOLOGY
Dan Shen received B.S.E.E. and M.S. degrees from
Shanghai Jiao Tong University, Shanghai, in 1999
and 2001, respectively.
From 2001 to 2002, he worked at Trident Micro
on video analog IC design. He continued to work on
video analog IC in Huaya Micro from 2002 to 2004.
From 2004 to 2007, he was with Institute of Microelectronics, Singapore, where he worked on data converters for wireless UWB and RFID applications. He
is currently working with Cirrus Logic, Austin, TX,
where he is designing sigma-delta data converters for
audio products. He has published four papers at international conferences.
Bin Zhao received the B.Sc. degree from Peking University, Beijing, China, in 1990, and the M.Sc. degree
from the Microelectronics R&D Center of the Chinese Academy of Sciences in 1993.
From 1993 to 1996, he was with Trident Microsystem (Beijing Branch) and Myson Technology
as an ASIC engineer. From 1996 to 1998, he worked
as a Research Scholar in the EEE Department of
National University of Singapore, and received
the M.Eng. degree in 1998. Then, he worked as
Electronic Engineer at Philips Electronics Singapore
for two years. Since 2000, he has been with Institute of Microelectronics,
A*STAR, Singapore. Currently, he is a Senior Research Engineer. His research
interests are low-power digital IC implementation for communication systems
and RFID tag/reader ICs.
M. Kumarasamy Raja received the Diploma and
Graduation in electronics and communication engineering in 1987 and 1993, respectively. He received
the M.S.E.E. degree from the Indian Institute of Technology, Madras (IITM), in 2002. He is currently pursuing the doctorate part-time at the National University of Singapore (NUS), Singapore.
He was with Ministry of Defence, Government of
India from March 1989 to February 1995, working
on testing of battle tank communication and control
systems. From March 1995 to September 2001, he
was with Centre for Development of Telematics (C-DOT), Telecom Technology
Centre of India, working on development of RF/IF transceivers for TDMA based
Telecom Transmission equipment. Since September 2001 he is with Institute of
Microelectronics (IME), A*STAR, Singapore, working on RF/Analog/Optical
CMOS IC design. Research areas of interest include RFIC, high speed ICs for
optical communication, Analog ICs, DSP based communication circuits.
Ye Wu received the B.S. degree in material science
engineering from Inner Mongolia University of Science and Technology, China, in 1995, and the M.S.
degree in electrical engineering from University of
Florida, Gainesville, in 2000.
She joined Fujitsu Compound Semiconductor Inc.,
San Jose, CA, in 2001, and worked on distributed amplifier for very high speed fiber optical application.
She joined the Institute of Microelectronics, Singapore, in 2004, and developed IQ Modulator for UHF
RFID reader and high-speed transimpedance amplifier for passive optical network application.
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Rendra Sindunata was born in Indonesia in 1983.
He received the B.E. degree in electrical and electronic engineering from Nanyang Technological University, Singapore, in 2006.
Since 2006, he has been working at the Institute of
Microelectronics, Singapore, as a Research Officer.
He has been involved in the design of IF filter,
variable gain amplifiers, received signal strength indicator and readout circuit for biosensor application.
Wooi Gan Yeoh (M’02) received the B.Eng. degree
(with honors) in electrical and electronic engineering
from Nanyang Technological University, Singapore,
in 1996, and the M.Eng. degree in electrical engineering from the National University of Singapore,
Singapore, in 2001.
Since 1996, he has been with the Institute of
Microelectronics, Singapore, where he was involved
with digital integrated circuit (IC) automatic test
equipment (ATE) testing, on-wafer dc parametric
testing, and analog IC design. He has also been
involved with the process development and 2.5-GHz RF IC design using RF
multi-chip module (RF-MCM) and GaAs technology. He then began to focus
on developing various RF and high frequency analog circuits for wireless
communications such as WCDMA RF/IF and cordless phone using CMOS
process. He was also involved in developing low-power low-voltage passive
Radio Frequency Identification (RFID) Tag IC for UHF and 2.45-GHz operations. He has authored and co-authored more than twenty five publications.
He holds five patents and has two patents pending. Today, he is managing
a group of fifty over IC designers working on various high frequency ICs
such as ultra-wideband transceiver, RFID Reader and tag ICs, low-power RF
transceiver for wireless sensors, optical communication ICs, MEMS ASICs as
well as RF and noise modeling.
Mr. Yeoh served as the Chairman of IEEE Solid-State Circuits Society of
Singapore Chapter from 2006 to 2007.
Rajinder Singh (M’97) received the B.Sc. and M.Sc.
degrees from the University of Delhi and the M.Tech.
and Ph.D. degrees from the Indian Institute of Technology, Delhi.
He was with IIT Delhi from 1981 to 1990 where
he worked on charge transfer devices, analog designs
and ratio-accurate capacitors and FETs. After a brief
stint at teaching, he joined ST Microelectronics in
1991 and worked at Grenoble and Delhi until 1995 on
standard analog cell designs, delta-sigma convertors
and non-quasi-static modeling of MOSFETs. From
1995 to 2007, he was with the Institute of Microelectronics, Singapore, where
initially he worked on GaAs based RFIC designs and in 1998 was entrusted
with the management of the IC design group. The group soon pioneered CMOS
RFIC designs in Singapore starting with CMOS Bluetooth delivered in 2001
that was followed by WCDMA blocks, 2.4 GHz RFID Tags and UHF RFID
Reader and UWB designs etc. in subsequent years. From 2005 he also started
building ultra low-power design capability for bio-electronics and sensor interface applications at IME. From 1993 to 1995, he was seconded to BaseComm
and FTD Tech as its CTO. Currently, he is serving as Chief Strategic Operations
Officer with Auxineon, Singapore. He has five filed/granted US patents and has
authored or co-authored about 20 publications.