13
CHAPTER 2
ARCHITECTURES OF OPERATIONAL
TRANSCONDUCTANCE AMPLIFIER
2.1
INTRODUCTION
Operational Transconductance Amplifier (OTA) is an integral part
of many analog and mixed signal systems. The topology of OTA’s plays a
critical role in the design of low power system. The design of OTA continues
to pose challenge as the supply voltage and transistor channel length scale
down with each newer generation of CMOS technologies. The OTA is the
versatile building block of any analog processing system. Designing these
building blocks in terms of gain, power consumption and gain bandwidth
product efficiently is still a challenging task. Operational Transconductance
Amplifiers are mainly classified into Single ended output OTA’s and
Differential ended output or Fully Differential OTA’s.
In this chapter, various single ended and fully differential OTA’s
available in the literature are discussed and their performances are compared
with each other. Under single ended structures, telescopic and folded cascode
OTA architectures with Wilson and Cascode current mirror load are
described. In fully differential category, two stage OTA and gain boosted
OTA are detailed along with telescopic and folded cascode OTA’s. The fully
differential OTA’s have several advantages over single-ended output OTA’s
such as a stable input common mode voltage, reduced harmonic distortion,
doubling of the output voltage swing and suppression of coupled noise due to
14
substrate and power lines. Hence, in this work, a high performance CMOS
fully differential OTA has been proposed using the folded cascode
architecture to achieve high gain, high output swing and a good slew rate. The
proposed OTA structures use an NMOS transistor in its input differential
stage to achieve high transconductance gain. The Selection criterion is
based on various parameters like transconductance gm, DC gain, gain
bandwidth product (GBW), Common Mode Rejection Ratio (CMRR) and
average power.
Signal processing system contains one or more analog
continuous time filters that are used in a wide range of applications. Low
pass filters act as an important signal processing element in any analogue
base band circuitry. These filters are specifically very useful in continuous
time filtering. In recent years, Gm-C filters have evolved as a suitable
processing element in low power and high frequency operations. A second
order Butterworth Gm-C low pass filter is used as a channel selection
filter in the wireless communication receiver. The proposed OTA structure
is implemented in a second order Butterworth Gm-C Low pass filter
because of its ability to operate at low supply voltage and power over a
wide tuning range.
2.2
LITERATURE SURVEY
Currently research studies are focussing on designing high
performance analog circuits at reduced power and supply voltage. The
transconductance amplifiers remain as the key element in various analog
integrated circuits. The realization of the OTA in low power circuits to
achieve high DC gain and high gain bandwidth is a tough task.
The overview of the single ended differential amplifier is provided
by Gray and Meyer et al (1982). In this paper, the discussion is carried out
15
for a two stage OTA and its alternative structures are discussed. This gives
insight into improving performance parameters like voltage gain, Common
mode rejection ratio and Power supply rejection ratio etc. However, the
design considerations for the fully differential circuits have not been detailed
in it. The basic architectures of various single ended and fully differential
structures are described along with their design complexities, limitations and
disadvantages by Gregorian and Razavi (1999). This helps in choosing a
specific category of OTA for a particular application. It also details about the
various advantages of fully differential structure over the single ended
structures. Hernes and Sansen (2005) discuss the classification of single stage,
two stage and three stage structures based on harmonic distortion. A
performance comparison of single stage amplifier and two stage amplifier
shows that single stage amplifier works well at high frequency while two
stage amplifier is good at mid frequency range. The study also assures that
noise level is maintained low for differential amplifiers with an increasing in
common mode rejection ratio and power supply rejection ratio. The input
stage transistors affect the overall operation of a circuit at high frequencies
and output transistors at low frequencies. Thus, the choice of transistor made
at the input and output stage also decides the amount of nonlinearity present
in the circuit. Jakbson et al (1992) give a clear explanation about flicker (1/f)
noise in MOS transistors. The usage of p-channel transistors as the input
differential stage in an amplifier reduces the third order and total harmonic
distortion. This enhances the choice of OTA, based not only on gain and gain
bandwidth product but also on noise performance. A two-stage OTA for
digital audio applications is designed by Dessouky and Kaiser (2001). This
OTA is used in delta sigma modulator, where the first stage is a folded
cascode stage and the second stage is a common source amplifier. There is a
limitation on slew rate in both the stages. Furthermore, there is an increase in
16
power dissipation as large bias current is drawn from the second stage due to
large load capacitance. This inhibits the use of OTA in low power
applications.
A two-stage class A/AB OTA is discussed in Brandt et al (1991)
which comprises of the differential pair at the first stage and active current
mirrors with class AB operation at the second stage. The class AB operation
does not limit the slew rate that often happens to the class A stage. So, there is
no trade off between static power consumption and slew rate in class AB
OTA when the large input signal is applied. This OTA is also present in the
delta sigma modulator which is being used in audio applications. It again uses
miller compensation for stability and cascode compensation for improved
amplifier bandwidth and better slew rate. Thus, multistage amplifiers are
preferred for very high mid band gain. However, each stage adds a new pole
which requires additional compensation in frequency. This results in
increased power consumption as the circuit draws a large amount of current.
The two stage operational transconductance amplifier described by Behzad
Razavi (2002) achieves high gain and voltage swing due to the presence of
two stages in the circuit. This helps in obtaining good signal to noise ratio and
dynamic range. However, this amplifier also requires a miller compensation
to maintain stability, which reduces unity gain bandwidth and speed. Yet
again, the power consumption is increased due to increased area. So, single
stage amplifiers are the best choice to work in reduced voltage and power
circuits.
Houda et al (2006) designed the single stage Telescopic OTA
structure which proves to achieve high gain and unity gain bandwidth. But,
the structure attains less output voltage swing and the input common mode
level should be maintained to match the output common mode level. This
17
affects the linearity of the circuit. Furthermore telescopic structures cannot be
implemented as a unity gain buffer. This inhibits its performance in practical
applications. The performance of a Folded Cascode OTA alleviates the
drawbacks of the Telescopic structures and attains comparable gain and unity
gain bandwidth with a greater output swing. Additionally, the dynamic range
is improved as the input and output common mode level need not to be
matched. It can also be easily configured into a unity gain buffer. Thus, the
folded cascode architecture remains as a perfect choice in the implementation
of a Gm-C filter for communication receivers, despite its disadvantages such
as increased power consumption and noise.
2.3
OTA FUNDAMENTALS
The OTA is a transconductance device in which the input voltage
controls the output current. An OTA is basically an operational amplifier
(opamp) without an output buffer. It can drive only capacitive loads. The
OTA can also be defined as an amplifier where all nodes are at low
impedance except the input and output nodes. The characteristic feature of an
ideal transconductance amplifier is that it has infinite input and output
resistances. An ideal OTA is defined as
I = g (V
V )
(2.1)
The transconductance (gm) makes the OTA work as a voltage
controlled current source; whereas the opamps are voltage controlled voltage
source. The basic schematic symbol of OTA is shown in Figure 2.1.
18
V+
Io +
+
Io
gm
V-
Io -
-
Figure 2.1 Circuit Symbol of OTA
An OTA which is basically a voltage to current transducer (VCT)
has been receiving considerable attention due to its usefulness and versatility
in many filtering and signal processing applications. Various OTA’s have
been reported in literature and many efforts have been put by researchers to
improve the OTA performances in terms of gain, slew rate, gain bandwidth
product and power dissipation.
2.3.1
Performance Parameters
There are various parameters to validate the performance of the
OTA. The important parameters that help in the designing of OTA are gain,
slew rate, power dissipation, common mode rejection ratio, power supply
rejection ratio and harmonic distortion. The performance of an OTA is
classified based on time domain and frequency domain parameters as given
by Phillip and Holberg (2002). The frequency domain parameters are
bandwidth, quality factor, gain, and phase. Slew rate is an important
parameter that influences the circuit design in its time and frequency domain.
19
Slew rate
Slew rate (SR) defines the fastest possible rate of change of OTA’s
output voltage, whose rate of change is limited due to the electronic circuitry
inside the OTA. It supplies small current to charge and discharge the
capacitor C.
The capacitor charge Q is calculated by integrating the current
i = gm (v+-v-) = gmvin Q = v C =
g v dt =
i dt
(2.2)
The rate of change of the output voltage is obtained as
= =
v
(2.3)
The maximum of this voltage is attained as
SR =
=
(2.4)
The maximum slope of a sinusoidal output voltage, v0 (t) =V0Sin t is
V0 .
Thus,
|
= SR =
V
(2.5)
Slew rate is related to frequency parameters by
SR =
where
t
i|
(2.6)
= gm/C is the unity gain frequency. The above equation shows that
slew rate increases with increasing
t
and power supply current.
20
Gain
The gain is a measure of the ability of an amplifier to increase the
power or amplitude of a signal from the input to the output. It is usually
defined as the mean ratio of the signal output of a system to the signal input of
the same system. It may also be defined on a logarithmic scale, in terms of the
decimal logarithm of the same ratio (dB gain). DC gain can be improved by
increasing the transconductance of the input transistors or the output
impedance. The open loop gain of an amplifier determines the precision of the
feedback system. A high open loop gain is necessary to suppress nonlinearity.
Circuit setup for calculation of open loop gain is given in the Figure 2.2. The
open loop gain is given by Equation (2.7)
A (dB) = 20log
(2.7)
Vdd
Vi +
+
+
gm
Vi -
-
Vo+
+
Vo-
-
CL
-
CL
Vss
+
Figure 2.2 Test Setup for Open Loop Gain Calculation
Power dissipation
The power dissipation is easily calculated from the supply voltage
and current when the output is open circuited. When current flows into a load,
21
it is easy to calculate the total dissipation and then subtract the load
dissipation to obtain the device dissipation. When the load capacitance is
increased, both the slew rate and the unity gain frequency of the OTA circuit
are reduced. To maintain a constant settling behavior, the power consumption
of the OTA must be increased linearly with an increase in the load
capacitance.
Common Mode Rejection Ratio (CMRR)
The relative sensitivity of an OTA to a difference signal as
compared to a common mode signal is called common mode rejection ratio
(CMRR) and is the figure of merit of the differential amplifier. CMRR is
given by
CMRR =
A
A
(2.8)
Where ADM is the differential mode gain and ACM is the common mode gain.
Ideally ADM should be large and ACM should be zero. The higher the value of
CMRR, better is the performance of OTA. Ideally, changes in the common
mode input should have no effect on the differential gain of the amplifier. As
it is practically not possible, Common-Mode Rejection Ratio is defined as the
ratio of differential mode gain to common mode gain. The circuit setup for
calculation of Common-Mode Rejection Ratio (CMRR) is given in
Figure 2.3.
22
Vdd
Vi +
+
+
gm
Vi -
-
Vo+
+
Vo-
-
CL
-
CL
+
Vss
+
-
VCM
Figure 2.3 Test Setup for CMRR Calculation
Power Supply Rejection Ratio (PSRR)
The change in the supply of an OTA changes its output voltages.
Hence, it has voltage transfer functions from any node to another node. In
many cases, the transfer functions from the input to the output and from the
power node to the output node are important. If the transfer function of the
power node to the output node is called the power supply gain (Ap), and the
transfer function of the input node to the output node is called the open loop
transfer function (A), the PSRR is defined as
PSRR(s) = 20log
( )
( )
dB
(2.9)
If the OTA involves two power supplies namely positive power supply V DD
and negative power supply VSS, a power supply gain for each power node can
be defined separately. In this case Ap, Vdd (Ap, Vss) is called the transfer
23
function from the Vdd (Vss) node to the output node where by the Vss (Vdd) is
ac grounded. The PSRR of each power supply can be defined as
PSRR, Vdd =
,
and
PSRR, Vss =
(2.10)
,
Power-supply rejection ratio is defined as the gain from input to
output divided by the gain from supply to the output. The circuit setup for
calculation of power-supply rejection ratio (PSRR) is given in Figure 2.4.
VDD
-
Vdd
+
Vi +
+
+
gm
Vi -
-
Vo+
+
Vo -
-
CL
CL
+
Vss
+
VSS
Figure 2.4 Test Setup for PSRR Calculation
Small-signal bandwidth
The high frequency behavior of amplifiers plays a critical role in
many applications. For example, as the frequency of operation increases, the
open loop gain begins to drop, as shown in Figure 2.5, thus creating large
errors in feedback system. The small signal Bandwidth is usually defined as
24
the “unity-gain” frequency, fu, which exceeds 1GHz in today CMOS OTA’s.
The 3-dB frequency, f3-dB, may also be specified to allow easier prediction of
closed loop frequency response.
20 log(AV)
0
f 3-dB
fu
f (log scale)
Figure 2.5 Small Signal AC Response
Total Harmonic Distortion
When a sinusoidal waveform is applied to a nonlinear timeinvariant system, the output signal will have frequency components at
harmonics of the input waveform, including the fundamental (or first)
harmonic. The total harmonic distortion, (THD) of a signal is a measure of the
harmonic distortion present and is defined as the ratio of the sum of the
powers of all harmonic components to the power of the fundamental
frequency (Martin et al., 2002). The THD is a measure of the extent of that
distortion. In units of dB, THD is found using the following relation:
THD = 10 log
(2.11)
Where Vf is the amplitude of the fundamental and Vhi is the amplitude of the
ith harmonic component.THD is presented as a percentage value.
25
THD is always a function of the amplitude of the input (or output)
signal level, and thus the corresponding signal amplitude is also reported. The
power of only the first few harmonics is included since the distortion
components usually fall off quickly at higher harmonics for practical reasons.
Third Harmonic Distortion (HD3)
The third harmonic distortion HD3 is specified as the ratio of the
magnitude of the third power term to the level of the fundamental frequency.
HD3 =
(2.12)
where HD1 and HD3, are the amplitudes of the fundamental and thirdharmonic terms respectively.
The above said performance parameters were
obtained for various OTA’s using CMOS 0.35
m technology and were
simulated using H-Spice, Synopsys EDA tool.
2.4
DIFFERENTIAL
TWO-STAGE
TRANSCONDUCTANCE
AMPLIFIER
The differential two stage transconductance amplifier shown in
Figure 2.6 is formed by differential cascade pair transistors M1 and M2 as the
first stage and common source amplifier as the second stage as in Shailesh
and Khalid (2008). Since two transistors are present at the output, the
presence of two stages helps the circuit to attain high gain and high dynamic
range. This in turn helps the OTA to achieve good SNR at low power supply
voltages. The simulation result of the two-stage OTA achieves a
transconductance of 2.07 ms and open loop DC gain of 85.69 dB.
26
VDD
M3
M4
Vb2
M8
M6
Rz
Vout+
Rz
Cc
Vout-
Cc
V+
M1
M2
V-
Vb1
M9
M5
M7
Figure 2.6 Differential Two Stage Transconductance Amplifier
The design parameters of two-stage OTA are listed in Table 2.1.
Table 2.1 Design Parameters of Two Stage OTA
Parameters
Values
Vdd (V)
3.3
Channel Length ( m)
0.35
RZ (k )
1
CC (pF)
0.1
W1,2
m)
20
W3,4
m)
6
W5
W6,8
m)
4
m)
10
W7,9 ( m)
5
Vb1 (mV)
500
Vb2 (mV)
233.6
27
Since two stages are present, the stability of the OTA is maintained
using a compensation capacitor (Cc) and a resistor (Rz) or a MOSFET during
feedback operation. This reduces the unity gain bandwidth and the speed of
operation. Also, the structure requires two Common Mode Feedback (CMFB)
Circuits vb1, vb2 for the four current branches M3, M4, M5, M7 and M9
present in the circuit. Hence, the power consumption of the OTA increases
with a increase in area. This inhibits the performance of the two stage OTA.
In order to achieve high gain and large bandwidth with less power
consumption, the telescopic topologies are used in building OTA.
2.5
SINGLE ENDED (SE) TELESCOPIC OTA
The Telescopic OTA uses an input differential pair along with
Cascode current mirror and Wilson current mirror. Input transistors M1 and
M2 acts as a voltage to current converters and converts applied input voltage
to output current. The transistors M5, M6, M7 and M8 form a Cascode/
Wilson current mirror (John and Martin 1997) load as shown in Figure 2.7
while a biasing current Ibias is used to bias the transistors M9 and M10, a bias
voltage V1 is used to bias the transistors M3 and M4. (Houda et al 2006).
VDD
VDD
M7
M8
M7
M8
M5
M6
M5
M6
Vout
Vout
IBIAS
IBIAS
CL
M3
CL
M4
M3
M4
V1
V+
V1
M1
M10
M2
V-
M9
VSS
(a) OTA with Cascode Current Load
V+
M1
M10
M2
V-
M9
VSS
(b) OTA with Wilson Current Load
Figure 2.7 Single Ended Telescopic OTA
28
The operation of the circuit requires only two current branches and
thus, the power consumption is improved. The slew rate depends upon the
bias currents and the output load capacitance and is better than the two stage
amplifier. The cascode device in the circuit helps to achieve high gain and
reduces the noise contributed by the bias transistors. The circuit gain is given as
Av = g
where g
and g
[ (g
r ) (g
r )]
(2.13)
is the transconductances of NMOS and PMOS transistors
respectively (Behzad Razavi 2002). The simulation result of single stage
single ended telescopic OTA (SE Telescopic OTA) with Wilson current
mirror load shows that the open loop DC gain is 84.8 dB and the gain
bandwidth is 270 dB MHz. The transconductance, CMRR and PSRR value of
the telescopic OTA are 197.11 S, 128 dB and 84.8 dB respectively.
The Single Ended Telescopic OTA with Cascode Current Mirror
Load has an open loop DC gain of 83.27 dB and unity gain bandwidth of 111
dB MHz. The transconductance of Single Ended Telescopic OTA is obtained
as 197.5 s. The CMRR value is 128.19 dB and the PSRR of OTA is found to
be 84.8 dB. The design parameters of single ended telescopic OTA with
Cascode and Wilson current mirror load are listed in Table 2.2.
Table 2.2 Design Parameters of Single Ended Telescopic OTA
OTA
OTA
Parameters
With Cascode
With Wilson
Current mirror Current mirror
CL (pF)
0.1
0.1
Ibias ( A)
15
30
Vdd/Vss (V)
±2
±2
Channel Length ( m)
1
1
W1,2 m)
35
35
W3,4,9,10 m)
6
6
W5,6,7,8 m)
18
18
V1 (mV)
600
600
29
Although, the single ended Telescopic OTA circuit is a better
candidate to attain a higher gain, a larger bandwidth, a better slew rate, lesser
noise and lower power consumption, the OTA are deprived from being
implemented as a unity gain buffer. This is due to the fact that they have
limited input and output voltage swings.
2.6
FULLY DIFFERENTIAL TELESCOPIC OTA
The fully differential telescopic cascode OTA is quite similar to the
single ended structure but for the addition of the M11 and M12 transistors, as
shown in Figure 2.8. The advantages of fully differential OTA’s over singleended designs are stable input common mode voltage, reduction of harmonic
distortion, doubling of output voltage swing, and suppression of coupled noise
due to substrate and power lines. The slew rate is better than the two stage
amplifier proposed by Shailesh and Khalid (2008).
In the telescopic cascode OTA, the main source of noise is due to
the input transistors M1 and M2 and the bias transistors M6 and M8.
However, the effect of noise is minimized through the cascode devices, since
the devices help the circuit to obtain high gain. There are only two current
branches M11 and M12, (Behzad Razavi 2002) which substantially improve
the power consumption. The main disadvantage of this design is that the
output swing is low and input common mode level has to be set accurately to
match with the output common mode level. When the common mode level
voltages decrease, it affects OTA’s linear range of operation.
30
VDD
M7
M8
M11
M5
M6
M12
Vout-
Vout+
CL
CL
M3
Ibias
M4
Vbias
V+
M10
M1
Ibias
M2
V-
M9
VSS
Figure 2.8 Fully Differential Telescopic OTA
The fully differential Telescopic cascode OTA for ±2V has an
open loop DC gain of 77.01 dB and a unity gain bandwidth of 181 dB MHz.
The transconductance of the fully differential Telescopic cascode OTA is
28.17 S. The CMRR and PSRR of the OTA are found to be 114.7 dB and
97.01 dB respectively. The design parameters of the OTA are listed in
Table 2.3.
31
Table 2.3 Design Parameters of Fully Differential Telescopic OTA
Parameters
Values
CL (pF)
0.1
Ibias ( A)
15
Vdd/Vss (V)
±2
Channel Length ( m)
1
W1,2
35
m)
W3,4,9,10
W5,6,7,8
W11,12
m)
m)
m)
Vbias (mV)
6
18
33.5
600
The fully differential telescopic cascode OTA suffers from several
drawbacks in spite of attaining a higher gain, lesser noise, larger gain
bandwidth product and lesser power consumption. As in the single ended
stage, the output swing is considerably lower as the number of devices at the
output stage is more and the input common mode level has to be set
accurately to match with the output common mode level. This circuit
realization too cannot be implemented as a unity gain buffer because of the
reduction in voltage range. So, in order to alleviate the drawbacks of a
telescopic OTA a folded cascode structure is considered.
2.7
SINGLE ENDED (SE) FOLDED CASCODED OTA
The name “folded cascode” comes from folding down n-channel
cascode active loads of a differential pair and changing the n-channel
MOSFETS to p-channels. This OTA has good PSRR when compared to all
other OTA’s. Since the number of transistors in the output stage is less, the
single ended folded cascoded OTA produces an increased voltage swing when
compared to telescopic structure. The folded cascode OTA based on Wilson
32
mirror has a limited output swing. So, the OTA circuit has been modified to
improve the output swing using a Cascode current mirror. In a folded cascode
OTA using a Wilson current mirror, the maximum output voltage was set to a
value lower than: Vdd+VT+2Vds,sat. Thus, in order to restore this fall to
+2Vds,sat, a cascode current mirror is used. The folded Cascode OTA with
Wilson and Cascode current mirror is shown in Figure 2.9. The folded
cascode OTA has a PMOS differential input stage with transistors M9 and
M10 to charge the Wilson/Cascode current mirror transistors M1-M4.
Transistors M11 and M12 provide the DC bias voltages to M5, M6, M7, M8
transistors (Houda et al 2006).
The open-loop voltage gain is given by the equation
Av = g
{[(g
where g
+g
,g
and g
)r (r llr )] (g
)r r ]}
+g
(2.14)
are the transconductance of transistors M9, M5 and
M3 respectively. The output resistances of transistors (Behzad Razavi 2002)
M1, M3, M5, M7 and M9 are
,
,
,
and
respectively. The
design of the folded cascode OTA amplifier is based on the gm/ID
methodology introduced by Flandre and Silveira 1996.
VDD
VDD
M1
M2
M3
V-
M9
M10
M1
M2
M3
M4
Ibias
Ibias
M4
V+
Vout
Ibias
V-
M9
M10
V+
Vout
CL
M5
M6
M5
M6
M11
M7
Ibias
CL
M8
M11
M7
M8
M12
VSS
(a) OTA with Wilson Current Load
M12
VSS
(b) OTA with Cascode Current Load
Figure 2.9 Single Ended Folded Cascode OTA
33
The specifications of the circuit are as in Table 2.4. The open loop
DC gain of single stage single ended folded cascode OTA with Wilson
current mirror load is 84 dB and unity gain bandwidth is 84.02 dB MHz. A
transconductance of 102.9
s is achieved using folded cascode OTA. The
CMRR and PSRR values found to be 187.5 dB and of 104 dB are achieved
using a Wilson current mirror in the folded cascode OTA.
Table 2.4 Design Parameters of Single Ended Folded Cascode OTA
Parameters
Values
CL (pF)
0.1
Ibias ( A)
30
Vdd/Vss (V)
±2
Channel Length ( m)
1
W1,2,3,4
18
m)
W5,6,7,8,11,12
m)
W9,10 ( m)
6
35
The open loop DC gain of the OTA is 84 dB and unity gain
bandwidth is 107 MHz. The simulated result shows 103.07
S of
transconductance, 110 dB of CMRR and 195 dB of PSRR using the folded
cascode OTA with Cascode current mirror load. The above said two designs
on telescopic and folded cascode OTA are single ended topologies. In order to
improve the performance parameters like output swing, speed and noise,
differential topologies are chosen.
2.8
FULLY DIFFERENTIAL FOLDED CASCODE OTA
The gain of the fully differential operational amplifier is provided
by its input stage. Mobility of NMOS device is always greater than that of
PMOS device and the PMOS input differential pair has a lower
34
transconductance than an NMOS pair. Thus, NMOS transistor has been
chosen as input stage to ensure the required largest gain. Two fully
differential folded cascode OTA structures with NMOS input differential
stage (Folded Cascode OTA 1 and 2) are discussed here.
2.8.1
Folded Cascode OTA 1
The fully differential folded cascode OTA described by Houda et al
(2008a) is shown in Figure 2.10.
VDD
M1
M2
M12
M3
Vout+
M4
Vout-
V1
CL
V+
M9
M10
Ibias
CL
M5
V-
M6
Ibias
V2
M7
M8
M11
VSS
Figure 2.10 Fully Differential Folded Cascode OTA 1
The folded cascode OTA has an input differential stage consisting
of NMOS transistors M9 and M10. Transistors M11 and M12 provide the DC
bias voltages to M1, M2, M7, M8 transistors. Additionally, as input common
mode level and output common mode level need not to be identical, dynamic
35
range is improved. The output capacitors used in the circuit act as
compensation capacitors maintaining the stability in feedback. This also
increases the speed of the circuit. The open loop voltage gain and gain
bandwidth are given by Equation (2.15) and Equation (2.16) below
A =
(
(2.15)
)
GBW =
.
(2.16)
Where, gm4, gm6 and gm9 are the transconductance of transistors M4, M6 and
M9 respectively. ID is the bias current flowing through transistors M9, M4,
and M6 and CL is the output node capacitance.
N
and
P
are the channel
length modulation parameters of NMOS and PMOS devices. The gain
expression is given as shown in Equation (2.17).
A =
.
(
)
(2.17)
The simulation results of single stage fully differential folded
cascode OTA shows that the open loop DC gain of 75.3 dB and unity gain
bandwidth of 873 MHz is achieved. The transconductance of the OTA is
found to be 330 S. The design of the folded cascode OTA amplifier is also
based on the gm/ID methodology introduced by Flandre and Silveira 1996.
The MOSFET sizes are computed as a result of the design flow and are shown
in Table 2.5.
36
Table 2.5 Design Parameters of Folded Cascode OTA 1
Parameters
Values
CL (pF)
0.1
Ibias ( A)
69
Vdd/Vss (V)
±2
Channel Length ( m)
1
W1,2,12
m)
W3,4
m)
W5,6,7,8
m)
10.8
5.4
2
W9,10 ( m)
14
W11
4
m)
V1 = V2 (mV)
318
The CMRR and PSRR values of single stage fully differential
folded cascode OTA 1 are 158.3 dB and 84.4 dB respectively. Due to folding
and cascading, these OTA’s achieve a higher gain and a larger unity gain
bandwidth when compared to the Telescopic OTA’s. As this topology works
in various frequency ranges, choice of operation of transistors can be made
according to the application and their constraints.
2.8.2
Folded Cascode OTA 2
The folded cascode OTA 2 is based on the folded cascode
architecture of Houda et al (2008) and is shown in Figure 2.11.
37
VDD
M1
M2
Ibias1
M15
M3
V+
M9
M10
M4
V-
M16
Vout+
Vout-
CL
M14
M11
M13
M12
M5
M6
M7
M8
CL
Ibias2
VSS
Figure 2.11 Fully Differential Folded Cascode OTA 2
The folded cascode OTA 2 is also designed using gm/ID
methodology introduced by Silveira et al (1996) with ±1.8V supply voltage.
In this circuit, transistors M15 and M16 are used to bias the cascode
transistors M1-M4. Similarly, transistors M11-M14 are used to bias the
cascode transistors M5-M8. This increases the unity gain bandwidth of the
circuit and consumes lesser power when compared to the fully differential
folded cascode OTA 1. The objective function to maximize gain, CMRR and
PSRR can be formulated as follows:
F
A
f
CMRR +
(2.18)
38
where
PSRR +
+
(2.19)
,
where
1…
6
are positive coefficients used for normalization.
The open-loop voltage gain and gain bandwidth product are given
in Equation (2.20) and Equation (2.21) respectively
A =g
(g
r r
g
r (r
r ))
(2.20)
GBW =
(2.21)
where, gm3, gm5 and gm9 are respectively the transconductance of transistors
M3, M5 and M9. The drain to source resistances of transistors M1, M3, M5,
M7 and M9 are r01, r03, r05, r07 and r09 respectively. CL is the capacitance at the
output node.
The power-supply rejection ratio (PSRR) is expressed as:
PSSR =
(
)(
(
=R r g
=r g
(R
)
)
(2.22)
(2.23)
+r )
(2.24)
R
= r
(2.25)
R
=r r g
(2.26)
39
The common mode rejection ratio (CMRR) can be approximated as:
CMRR = 20 log (
(
)
)
(2.27)
The optimal device dimensions of folded cascode OTA 2 is shown
in Table 2.6.
Table 2.6 Design Parameters of Folded Cascode OTA 2
Parameters
Values
CL (pF)
0.1
Ibias1 ( A)
60
Ibias2 ( A)
90
Vdd/Vss (V)
±1.8
Channel Length ( m)
W1,2,15,16
W3,4
m)
34.85
m)
W5,6,7,8, 11,12,13,14
W9,10 ( m)
1
23
m)
47.15
49.9
The simulation result of this OTA is done in CMOS 0.18µm
technology as against CMOS 0.35µm technology given by Houda et al
(2008). The single stage fully differential folded cascode OTA 2 achieves an
open loop DC gain of 79.8 dB and unity gain bandwidth of 946 dB MHz. The
results are shown in Figure 2.12.
40
Figure 2.12 AC Analysis for Open Loop DC Gain
The transconductance of folded cascode OTA 2 is 327.1 us and is
shown in Figure 2.13. The CMRR and PSRR values of this OTA are 127.7 dB
and 119 dB respectively. Simulation results are as provided in Figures 2.14
and 2.15 respectively.
Figure 2.13 AC Analysis for Transconductance
41
Figure 2.14 AC Analysis for CMRR
Figure 2.15 AC Analysis for PSRR
The fully differential Folded Cascode OTA 2 obtains the maximum
gain bandwidth product of 946 dB MHz with the gain around 80dB. The OTA
works with ±1.8V and achieves an average and peak power consumption of
0.27mW and 3.21 mW respectively.
42
2.9
FULL
DIFERENTIAL
FOLDED
CASCODE
GAIN
BOOSTING (FDFCGB) OTA
The fully differential amplifier provides great advantage with a
larger output swing, avoiding mirror pole and without an even order non
harmonics, rejecting the noise generated by substrate when compared to the
single ended amplifier. Thus, in order to achieve a much higher output voltage
swing, the folded cascode structure is utilized in the amplifier. Further, gain
boosting stages are introduced in the design to further increase the gain and
Unity Gain Bandwidth.
Behzad Razavi (2002) studied the gain boosting technique to
improve gain. The amplifier uses a negative feedback loop to set the drain
voltage of transistor M2. The main amplifier gain is almost doubled through
the use of negative feedback loop. In the Figure 2.16, the output impedance of
the circuit is increased when Vx is made equal to Vref . This makes the
variation of the output voltage (Vout) much more negligible when compared to
Vx as given by Sidong Zhang and Lu Huang (2007). This increase in output
impedance makes the DC gain to increase by twofold and the equation is
given by
Atot = g
r (g
r (A
+ 1) + 1) + g
r
(2.28)
The output impedance is given by Equation (2.29).
Rout = g
r (A
+ 1) + 1)r
+r
(2.29)
43
Vx
Figure 2.16 Cascode Gain Stage with Gain Enhancement
The topology used in this OTA is a single stage fully differential
folded cascode structure with two gain boosting stages as shown in Figure
2.17. The input transistors M1 and M2 acts as transconductors and it will
convert applied input voltage to output current. The transistors M3, M4, M5
and M6 act as load for OTA. The NMOS and PMOS boosting stages provided
by Su and Qui (2005) are used to increase the output impedance of OTA.
Vcmfbp and Vcmfbn are bias voltages generated from CMFB circuit to
provide biasing for OTA. The folded cascode design is used because it has a
higher DC gain, a higher UGB, a higher Slew rate and a faster settling with
low power dissipation. Differential structure helps in reducing distortion since
higher order non linear terms are cancelled. Design parameters for FDFCGB
OTA are listed in Table 2.7.
44
Figure 2.17 Fully Differential Folded Cascode Gain Boosted OTA
Table 2.7 Design Parameters of FDFCGB OTA
Parameters
Vdd (V)
Values
3.3
Channel Length ( m)
1
W1,2
m)
600
W3,4
m)
100
W5,6
m)
200
W7,8,11
W9,10
m)
m)
80
40
V1 (m V)
600
Bias (V)
0.8
Vcmfbp (V)
2
Vcmfbn (V)
0.7
Offset
±0.9
45
The AC analysis of FDFCGB OTA shows that it has a DC gain of
100 dB and Unity Gain Bandwidth of 850 MHz. The CMRR calculation is
found to be 110 dB with PSRR of 140 dB. The transconductance of FDFCGB
OTA is 1.7 mS.
2.9.1
Gain Boosting Stages
The gain boosting stage has evolved due to limitations in gain of
single stage structure and difficulties found in using two stage structures at
high speed. The cascode device decreases the output voltage swing. So, the
gain boosting stages are developed to increase the output impedance without
adding more cascode devices. In contrast to two stage OTA where the entire
signal experience the poles associated with each stage, the signal directly
follows through the cascode devices in a gain boosting OTA. So, the extra
stage does not change the original unity gain bandwidth.
In order to increase the gain of the OTA an N-type folded cascode
amplifier has been used to increase the impedance of PMOS part of the main
FDFCGB OTA and a P-type folded cascode stage has been used to increase
the impedance of NMOS part of the main FDFCGB OTA (Zarifi et al 2007).
The schematic diagram of the NMOS and PMOS boosting stage is shown in
Figure 2.18 (a) and (b) respectively. In both the boosting stages, the input
transistors M1 and M2 act as transconductors and convert applied input
voltage to output current. The transistors M3, M4, M5 and M6 act as load for
OTA (Behzad Razavi 2002). BN1/BP1, BN2/BP2, BN3/BP3, BN4/BP4 and
BN5/BP5 provide bias voltages for designing the OTA. Design parameters for
NMOS and PMOS boosting stage are listed in Table 2.8. The simulated
results of the NMOS and PMOS boosting stage are given in Table 2.9.
46
(a) NMOS Boosting Stage
(b) PMOS Boosting Stage
Figure 2.18 Gain Boosting Stages
47
Table 2.8 Design Parameters of NMOS and PMOS Boosting Stage
Parameters for NMOS
Values
Boosting Stage
Parameters for PMOS
Boosting Stage
Vdd (V)
3.3
Vdd (V)
3.3
Channel Length ( m)
0.35
Channel Length ( m)
0.35
W1,2
500
W1,2
m)
800
20
W3,4
m)
40
10
W5,6
m)
60
BN1 (mV)
40
W7,8,9,10
10
BN2 (mV)
600
W11
50
BN3 (mV)
0.8
BP1,BP5 (mV)
2.8
BN4 (mV)
2
BP2 (mV)
2.4
BN5 (mV)
0.7
BP3 (mV)
0.8
BP4 (mV)
0.63
m)
W3,4,5,6,11
m)
W7,8,9,10
m)
Values
Table 2.9 Simulated Parameters of Folded Cascode Gain Boosted OTA
Specification
NMOS
Boosting
PMOS
Boosting
FDFCGB
OTA
DC Gain (dB)
55
61
100
GBW (MHz)
40
60
850
Offset (V)
2.8
2.5
0.9
CMRR (dB)
85
80
110
PSRR (dB)
90
80
140
Transconductance ( S)
295
70
1700
SR (V / s)
0.12
0.05
0.251
THD @fc
0.55%
0.55%
0.85%
HD3 (dB)
-63
-75
-53
Supply Voltage (V)
3.3
3.3
3.3
AVG power (mW)
1.6
1.7
9
(CL =2 pF)
48
The Table 2.9 lists all the performance parameters calculated for
the NMOS and PMOS boosting stages individually along with the folded
cascode gain boosted OTA. The gain boosted OTA has a maximum gain
when compared to all the other OTA’s in literature but with increased power
consumption. As the objective is to design an OTA for low power
applications, gain boosted OTA’s are utilized only for certain unique
application where there is a trade off for power. Hence, fully differential high
performances OTA has been proposed using folded cascode architecture as it
can operate at reduced supply voltage and yields low power with gain
comparable to telescopic structure with large unity gain bandwidth.
2.10
COMMON MODE FEEDBACK CIRCUITS
In a differential architecture, there is a need for common mode
feedback (CMFB) circuit to stabilize the two outputs of the amplifier to a
common voltage. The PMOS and NMOS transistors in the output stage create
a balance in the output common mode voltage. A CMFB provides a negative
feedback and controls the current flowing through the output transistors. This
stabilizes the output to a common voltage. The two approaches to design
CMFB circuits
Continuous Time approach
Switched Capacitor approach
The switched capacitor CMFB is a dynamic configuration and
provides low power dissipation.
2.10.1
Switched Capacitor Common Mode Feedback (SC CMFB)
In fully-differential structures, the applied feedback determines the
differential signal voltages, but does not affect the common mode voltages. It
49
is therefore necessary to add additional circuitry to determine the output
common mode voltage and to control it, to be equal to reference common
mode voltage. Hence, to control the output common mode voltages, CMFB
circuits are used in fully differential structures. Switched capacitor CMFB
circuits discussed by Wongnamkum and Thanachayanont (2004) have good
accuracy in determining the filter’s cut-off frequency and provide stability to
filter. Switched capacitor CMFB circuits are area efficient and do not need an
additional amplifier. The switched capacitor CMFB circuit is shown in
Figure 2.19 and uses capacitive voltage division to control the output common
mode voltage.
Vref
P1
P2
Vout+
MF1
MF2
Cs
Ca
P1
P2
MF3
MF4
P2
P1
MF5
MF6
Vout-
Ca
Vcmfb
VDD
Itune
Cs
P2
P1
MF7
MF8
MF9
VSS
Figure 2.19 Switched Capacitor CMFB
The circuit consists of two capacitors Ca and CS to average the
output voltages and it adds the bias voltage to control the output common
mode voltage. Vout+ and Vout- from the transconductor circuit are given as
inputs to CMFB circuit. If the common mode level of the outputs Vout+ and
Vout- increases, then the Ca capacitor average voltage also increases to
control the output common mode level. P1 and P2 are two non overlapping
50
signals applied to the MOS transistors in the CMFB circuit which act as
switches. By varying the Itune, the tuning range of the OTA is varied to
accommodate a wider frequency range in the filter. The MOSFET design
specifications are given in Table 2.10.
Table 2.10 Design Parameters of SC CMFB
Parameters
CS (pF)
0.01
Ca (pF)
0.1
Itune ( A)
15
Vdd /Vss (V)
±2
Vref (V)
0.65
Channel Length ( m)
0.5
W1,2,3,4
W5,6,7,8,9
2.11
Values
m)
m)
6
6
PROPOSED FULLY DIFFERENTIAL FOLDED CASCODE
OTA
The major part art in the design of OTA lies in the choice of input
transistors as it is the first stage that provides the largest gain. Since, an
NMOS transistor exhibits a higher transconductance than a PMOS transistor,
an NMOS pair is chosen in the input differential pair to provide gain of the
OTA. This is due to the fact that the mobility of NMOS device is larger than a
PMOS device for a comparable device dimensions and bias currents. Here, a
fully differential folded cascode OTA has been proposed with NMOS as the
input differential stage because of its greater mobility and higher
transconductance.
51
2.11.1
Architecture Analysis
The folded cascode OTA has a differential stage consisting of
NMOS transistors M9 and M10. Transistors M11, M12, M13 and M14
provide the DC bias voltages to M8, M2, M4, M6 transistors as shown in
Figure 2.20. Cascode transistors M3, M4, M5, M6 are controlled by
transistors M13 and M14 respectively, which is not present in the
conventional fully differential folded cascode OTA 1. There is symmetric
nature between the transistors M3 and M5.The open-loop voltage gain and
gain bandwidth are given in Equations (2.30) and (2.31) below
A =g
(g
r r
(g
r (r
r ))
(2.30)
GBW =
(2.31)
Where, gm3, gm5 and gm9 are the transconductances of transistors M3, M5 and
M9 and CL is the output node capacitance respectively.
VDD
M1
M2
M12
M3
M4
M13
Vout+
Vout-
CL
V+
M9
M10
M5
M6
Ibias
CL
VM14
Ibias
M7
M8
M11
VSS
Figure 2.20 Proposed Fully Differential Folded Cascode OTA
52
The power-supply rejection ratio (PSRR) is given by Equation (2.32)
(
PSSR =
)
(2.32)
where
= (R
+R
=r g
+r
(R
R r g
)
+r )
(2.33)
(2.34)
R
= r
(2.35)
R
=r r g
(2.36)
Where r01, r03, r05, r07 and r09 are the drain-source resistances of transistors
M1, M3, M5, M7 and M9 respectively. The slew rate (SR) can be written as
SR =
(2.37)
Where, Ibiais is the bias current of the folded cascode OTA.
The settling time tS in terms of SR is given by Equation (2.38)
t =
,
(2.38)
Where, V is the voltage swing.
2.11.2
Sizing Algorithm
In this section, same design procedure introduced by Silveira
(1996) is applied based on the gm/ID methodology. The aim is to determine the
values of the design parameters that optimize an objective feature while
satisfying specific constraints. The top-down design flow methodology for
CMOS OTA architecture is shown in Figure 2.21.
53
Figure 2.21 Design Flow of the Proposed OTA
The following steps help to determine the unknown performance
parameters:
Equation (2.31) directly yields gm9 from the given transition
frequency and capacitive load, while gm9/ID is derived from
the specified DC open-loop gain and the chosen technology.
gm9 and gm9/ID yield the bias current ID and furthermore gm9/ID
gives I', Where I'= ID/(W /L).
W/L is finally given by ID/I'.
The design parameters from the specifications of top-down design
flow is given in Equations (2.39) and (2.40). The fixed specifications are
given in Table 2.11.
w
g
I
I
W
L
(2.39)
54
A
g
I
I
W
L
(2.40)
Table 2.11 Design Parameters of Proposed Folded Cascode OTA
Parameters
Values
CL (pF)
0.1
Ibias ( A)
15
Vdd/Vss (V)
±2
Channel Length ( m)
1
W1,2,12
W3,4
W5,6,7,8
m)
m)
m)
10.8
5.4
2
W9,10 ( m)
14
W11 ( m)
4
The simulation results of proposed single stage fully differential
folded cascode OTA for ±2V and CL=0.1pF is shown in Figure 2.22. The
open loop DC gain is 86.47 dB and unity gain bandwidth is 304 dB MHz.
Figure 2.22 AC Analysis for Open Loop DC Gain
55
The transconductance of proposed single stage fully differential
folded cascode OTA is 105.37 S and is shown in Figure 2.23. The CMRR
and PSRR of the proposed OTA 1are found to be 164.3 dB and 129.7 dB
respectively. The graphs are shown in Figure 2.24 and 2.25 respectively.
Figure 2.23 AC Analysis for Transconductance
Figure 2.24 AC Analysis for CMRR
56
Figure 2.25 AC Analysis for PSRR
In this circuit, biasing is provided through M13 and M14 transistors
when compared to V1 and V2 in the conventional fully differential folded
cascode OTA 1. This increases the DC gain, CMRR and PSRR of the OTA.
Also, the circuit has the output capacitor that acts as a compensation capacitor
and hence, no additional capacitor is required for compensation. This
increases the speed of operation of the circuit and consumes lesser power
when compared to the conventional fully differential folded cascode OTA’s.
The folded cascode transconductance amplifier which works at base band
frequencies is sized. The proposed methodology has the ability to generate
satisfying solutions for fixed constraints. Single stage fully differential folded
cascode OTA’s performs better at reduced supply and scaling of devices. The
performance
parameters
like
output
swing,
power
consumption,
transconductance, CMRR, PSRR etc. of these OTA’s are improved and are
comparable to OTA’s in literature. These OTA’s are less complex in design
and achieves a higher gain. Various OTA’s such as two stage OTA and single
stage OTA’s with single ended output and differential outputs are designed
and simulated. The performance comparison among these OTA’s are
tabulated in Table 2.12.
Table 2.12 Performance Comparison of Different OTA’s Implemented
Specification
(CL = 0.1 pF)
SE Folded
FD Folded
FD
SE Folded
SE Telescopic SE Telescopic
Telescopic
OTA
cascode
OTA Wilson OTA cascode
OTA cascode
OTA
Wilson
OTA 1
Houda et al Houda et al
Houda et al
Razavi et al Houda et al
Houda et al
2006
2006
2006
2002
2006
2008a
FD Folded
cascode
Proposed FD
Folded cascode
OTA 2
OTA
Houda et al
2008
DC Gain (dB)
84.8
83.2
77
84
84
75.3
79.8
86.4
GBW (dB MHz)
270
111
181
160
107
873
946
304
Offset (mV)
0.45
0.63
0.96
0.1
1.0
0.49
4.81
83.3
CMRR (dB)
128
128
114
187
195
158
127
164
PSRR (dB)
84.8
84.8
97
104
110
84.4
119
129
Trans conductance ( S)
197
197
28.1
102
103
330
327
105
SR (V / s)
827
328
26.7
120
101
355
168
78.7
Supply Voltage (V)
±2
±2
±2
±2
±2
±2
±1.8
±2
Bias current ( A)
30
15
15
15
15
60
15
Avg. power (mW)
0.21
0.19
0.04
0.12
0.11
0.49
0.27
0.16
Peak power (mW)
3.24
3.75
1.24
1.00
0.88
8.89
3.21
4.49
69
57
58
The proposed fully differential Folded Cascode OTA is designed
and their performance comparison parameters are tabulated. The simulation
results conclude that the proposed fully differential Folded Cascode OTA
attains the highest gain of 86.4 dB, CMRR of 164 dB, PSRR of 129 dB and
less average and peak power consumption of 0.16 mW and 4.49 mW
respectively. Thus the proposed fully differential Folded Cascode OTA
outperforms the conventional OTA’s in literature which makes it suitable as
the basic building block of a Gm-C filter. A second order Butterworth low
pass filter used in mobile applications is implemented with the proposed fully
differential Folded Cascode OTA which meets the design specifications of
Zig Bee Transceiver.
2.12
SECOND ORDER BUTTERWORTH LOW PASS FILTER
Low-pass filters are an essential part of an analogue baseband
circuit of modern communication receivers, because of the ability to
reconfigure the bandwidth, gain, or linearity in order to fulfill the
requirements of different standards. The main purpose of the analog baseband
filter in any receiver is to select the desired channel and to maximize the
dynamic range of Analog to Digital Converters. To enable this, the base band
filter must attenuate interferers to certain power level and provide wide
dynamic range. In order to have a wide tuning range for the analog filter, an
OTA with a higher gain and unity gain bandwidth is required.
The system specification of GSM and WCDMA requires a fourth
order Butterworth filter in the direct conversion receiver. So, the fourth order
filter is spilt into two second order sections for easy implementation. The two
second order filters are realized with the same structure by varying a single
component. Therefore, a second order butterworth low pass filter is designed
59
and implemented with the single second order section in this chapter, using
the proposed folded cascode OTA. The circuit realization proposed by Uwe et
nd
al (2003) is used for implementation of the 2 order low pass filter because of
its advantages in design and layout. Four OTA blocks are used to develop the
nd
2 order low pass filter, as shown in Figure 2.26. All filter stages operate with
one common bias generating circuit, which improves the matching between
the filter stages over the tuning range.
2C 1
+Vi
+
-
+
gm1
-Vi
-
-
2C 2
+
g m2
+
-
-
+Vo
+
g m3
+
-
2C 1
g m4
+
2C 2
-
+
-Vo
Figure 2.26 Gm - C Realization of 2nd order Low Pass Filter
The transfer function of this Biquad structure is
=
H(s) =
(2.41)
The transfer function of a 2nd order section of a fourth order
Butterworth filter is
H(s) =
.
(2.42)
60
Recognizing the general transfer function of a 2nd order low-pass filter as
H(s) =
(2.43)
Compare Equation (2.41) and Equation (2.43),
=
Here, g
g
=
Where
Q=
(2.44)
g and C = C = C, as in Uwe et al (2003)
Q=
g
=
(2.45)
2K
I
Now the transconductance g
(2.46)
of the 2nd order filter from (2.42) and (2.43)
is
g
= 1.848 g
(2.47)
To get 2nd order Butterworth low pass filter the transconductance of
the gm2 is 1.848 times of the gm. Three of the 4 OTA’s of the 2nd order filter
are identical; other remaining OTA can easily be adapted by just changing the
OTA current. The simulation result of 2nd order Gm- C low pass filter with ±2
V, C1=0.1 pF and C2=12 pF is shown in Figure 2.27.
The parameters
obtained are tabulated in Table 2.13. The filter’s cutoff frequency is found to
be 2.53 MHz with 1 mW of power and -50.7 dB THD.
61
Figure 2.27 Frequency Response of Filter
Table 2.13 Performance Parameter of the Low Pass Filter
Parameters
Performance
Technology
0.35µm
Supply Voltage
±2V
THD @fc=2.5MHz
-50.7dB
Power
1mW
Tuning Range
50KHZ-2.5MHz
The 2nd order Gm- C Bi-quad Low Pass Filter implemented with
the proposed fully differential Folded Cascode OTA exhibits a wide tuning
range from 50 kHz to 2.5 MHz and supports wireless standards like GSM,
UMTS and WCDMA.
62
2.13
CONCLUSION
Different architectures of single and fully differential Operational
Transconductance Amplifiers are designed and simulated in TSMC 0.35 m
CMOS technology using Synopsys EDA tool. The comparison of
performances of various architectures indicates that fully differential folded
cascode structures perform better than the other conventional architectures.
So, a fully differential folded cascode architecture has been proposed which
attains 6.6 dB, 37dB, 10dB and 40.74% improvement in DC gain, CMRR,
PSRR and power respectively compared to folded cascode 2 architecture
besides the tradeoff in GBW and slew rate due to lesser bias current. The peak
power consumption is increased as the switching activity is increased due to
additional bias transistors. As an application, the proposed OTA is used as the
basic amplifier in implementing continuous time filters. A second order GmC Butterworth low pass filter is designed with the proposed OTA, which
attains a Total Harmonic Distortion of 50.7dB with 1mW of power at a cutoff
frequency of 2.5MHz. Hence, the designed second order Gm-C Butterworth
low pass filter is used as a channel selection filter in the RF front end receiver.