Operation of MOS Transistors and
Scaling Issues
Sujay Desai
Electrical Engineering Department
IIT Bombay
Tutor: Prof. N. Dasgupta
15th December 2010
Outline
 MOSFET – Operation
 MOSFET – Fabrication
 Scaling
 Short Channel Effects
 Resolution of Short Channel Effects
 Summary
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Sujay Desai IIT Bombay
MOSFET - Operation
MOSFET Structure
Energy Band diagrams
Sub-Threshold region
Linear Region
Saturation
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MOSFET Operation
MOSFET Structure
Y - Axis
Gate
S/D
S/D
NMOS with Poly-Silicon Gate
X- Axis
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Body or
Substrate
We will be analyzing the
operation of a MOSFET
by taking the example of
n MOSFET. Similar
analysis can be done with
p MOSFET too.
LG : Gate Length
Leff : Effective Channel
Length (LG – lateral
diffusion of S/D)
W : Device width
Tox : Gate Oxide Thickness
Xj : Junction Depth
MOSFET Operation
Energy Band Diagram
Vgs = Vfb (flatband) and Vds = 0 for n - MOSFET
CB
Eg
Band
Gap
Along Y axis
Fermi Level Source  Channel 
VB
Drain
Eg/2
CB
Fermi Level
Ec = Efm
VB
Along X axis
at the oxide channel
interface
VB
Gate oxide
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Ref: [10]
MOSFET Operation
Energy Band Diagram
Vgs -Vfb > 0 and Vds > 0 for n - MOSFET
Along Y axis
Source  Channel 
Drain
Along X axis
at the oxide channel
interface
Near Source
Near Drain
For inversion at D, band bending at drain must be atleast Vds + 2 ϕF;
ϕF given by
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Ref: [10]
MOSFET Operation
Sub-Threshold Region
Vgs < Vt and Vds > 0
 Describes MOSFET switching characteristics.
 Weak inversion. Very few electrons for drift. Diffusion is major
current component due to strong density gradients.
 Subthreshold current ID exponentially dependent on Vgs (till Vgs <
Vt).
 An important parameter is sub-threshold slope S. Limited to a
minimum of 60mV/dec (300K)for MOSFET (Ci = oxide capacitance,
CD = depletion region capacitance)
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Ref: [1], [2]
MOSFET Operation
Linear Region
Vgs > Vt and Vds
0
 Inverted channel. Large number of mobile electrons.
Drift major current component. Linear dependence of
ID on Vgs.
 Rsd ~
for small Vds
 At large Vgs carriers pulled towards interface. Large
scattering due to surface imperfections (dangling Si –
SiO2 bonds, charge traps, etc.). Mobility degrades.
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MOSFET Operation
Saturation
Vgs > Vt and Vds > Vgs - Vt
 ID increases linearly with Vds upto Vds = Vgs –Vt,
beyond which the current saturates to IDsat.
Output I V characteristics of a
MOSFET for different values
of Vgs
Vgs1<Vgs2<Vgs3
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MOSFET Operation
Saturation
Vgs > Vt and Vds > Vgs - Vt
 Saturation can be due to two reasons
 Channel Pinch off : Insufficient band bending for inversion.
Pinch off point moves towards source as Vds . Current
dependent only on vertical electric field at S. Beyond pinch off
point, carriers swept away similar to the current conduction
mechanism in a reverse biased
diode.
 Velocity Saturation : High electric
field at high Vds . Mobility saturates.
Prominent in short channel devices.
 In saturation due to pinch off,
effective channel length reduces
(channel length modulation).
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MOSFET - Fabrication
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MOSFET Fabrication
Long Channel MOSFET
 Basic steps involving MOSFET fabrication are
 Oxidation
 Photolithography and etching
 Diffusion / ion implantation
 Metallization
 Silicon crystals are grown from the melt and
purified to very high percentages using
techniques like zone process.
 Wafers are sliced out of these to give the base
substrate for fabrication.
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Sujay Desai IIT Bombay
MOSFET Fabrication
Long Channel MOSFET
Y- Axis
Y- Axis
Z- Axis
X- Axis
For fabricating an n MOSFET, we start with a p- substrate
(~ 1015/cm3 and <100> oriented polished surface). The left figure
shows the side view, whereas the right one shows the top view
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Ref: [9]
MOSFET Fabrication
Long Channel MOSFET
The substrate, where there will be no transistors is etched out following the
sequence of photoresist application  UV light irradiation (Hg arc lamp)
through mask  removal of exposed photoresist and etching of Si 
removal of unexposed photoresist.
The same procedure is followed wherever structures need to be etched out.
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Ref: [9]
MOSFET Fabrication
Long Channel MOSFET
Oxide is deposited in the trenches and on the top of the substrate.
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MOSFET Fabrication
Long Channel MOSFET
Wafer top is polished to expose the silicon
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MOSFET Fabrication
Long Channel MOSFET
Gate Oxide SiO2
Boron Channel implant
The Si is subjected to channel implant (Boron for p substrate), so as to set the turnon voltage of the transistor to the correct value.
It is then subjected to oxidation, leading to the formation of SiO2
Si + O2  SiO2 (high temperature)
SiO2 is an excellent insulator, forms a good interface with Si and is chemically inert.
These and several other properties make it a natural choice as gate oxide.
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Ref: [9]
MOSFET Fabrication
Long Channel MOSFET
Polysilicon for gate is deposited and etched out. Sometimes sacrificial
silicon nitrides are deposited prior to etching, to protect the active part of
the MOSFET.
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MOSFET Fabrication
Long Channel MOSFET
Source and Drain implanted (Arsenic or Phosphorous). Diffusion self
aligns to the edges of the gate. There is however a little lateral diffusion
too, thus Leff <Lg
The self aligned process helps to keep Cgs and Cgd due to oxide overlap
at a minimum.
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MOSFET Fabrication
Long Channel MOSFET
Polysilicon coated with metal to reduce resistance
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MOSFET Fabrication
Long Channel MOSFET
First process in metallization is depositing dielectric
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MOSFET Fabrication
Long Channel MOSFET
Etch metal trenches
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Sujay Desai IIT Bombay
MOSFET Fabrication
Long Channel MOSFET
Etch via trench to reach the source and drain contacts
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MOSFET Fabrication
Long Channel MOSFET
Deposit metal
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MOSFET Fabrication
Long Channel MOSFET
Polish surface back
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Scaling
Constant Field
Constant Voltage
General scaling
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Scaling
Constant Field
 Scale keeping vertical and horizontal electric fields
constant.
Parameters: (Scaling factor : k>1)
Dimensions (L, Tox, W, Xj) : 1/k
Doping level (Na) : k
Supply Voltage (Vdd) : 1/k
 Problems:
 Designers don’t wish to scale Vdd as aggressively, so as
to have a larger drain current, shrink delay time, and
have faster circuits. Tradeoff is higher electric field.
 Tradeoff between Vt and Ioff causes Ioff to increase, thus
more static power dissipation.
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Scaling
Constant Field
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Device Parameter
Scaling factor
Electric Field
1
Carrier velocity
1
Depletion layer width
1/k
Capacitance
1/k
Inversion Charge Density
1
Drift Current (on - state per W)
1
Diffusion Current (off - state per W)
k
Threshold Voltage ~ (√Na)/Cox
1/√k
Sujay Desai IIT Bombay
Ref: [8], [11]
Scaling
Constant Field
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Circuit Parameter
Scaling factor
Delay time (C*V/I)
1/k
Power Dissipation (V*I)
1/k2
Power – Delay product (switching
energy)
Circuit Density (1/Area)
1/k3
Power Density (P/Area)
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k2
Ref: [8], [11]
Scaling
Constant Voltage
 Scale all device dimensions but not Vdd
Parameters: (Scaling factor : k>1)
Dimensions (L, Tox, W, Xj) : 1/k
Doping level (Na) : k
Supply Voltage (Vdd) : 1
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Scaling
Constant Voltage
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Parameter
Scaling factor
Capacitance
1/k
Power Dissipation (V*I)
k
Power – Delay product (switching
energy)
Power Density (P/Area)
1/k
Threshold Voltage ~ (√Na)/Cox
1/√k
Drift Current - Id
k
Delay time (C*V/I)
1/k2
Sujay Desai IIT Bombay
Ref: [8], [11]
k3
Scaling
Constant Voltage
 Performance better as switching time reduces.
 Doesn’t take care of increasing Ioff problem.
 Vertical Electric field increases, E ~ (Vdd/Tox) ~ k
 Horizontal Electric field increases, E ~ (Vds/L) ~ k
 Reliability issues and lower operational life.
 Power density and hence system power
increases. Cooling problems.
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Scaling
General Scaling
 Larger increase in doping
 Smaller decrease in supply voltage
Parameters: (Scaling factor : k>m>1)
Dimensions (L, Tox, W, Xj) : 1/k
Doping level (Na) : k*m
Supply Voltage (Vdd) : m/k
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Sujay Desai IIT Bombay
Scaling
General Scaling
Device Parameter
Scaling factor
Electric Field
m
Carrier velocity
m (1 if velocity saturated)
Depletion layer width
1/k
Capacitance
1/k
Inversion Charge Density
m
Drift Current (on - state per W)
m2 (m if velocity satn)
Diffusion Current (off - state per W) m*k
Threshold Voltage ~ (√Na)/Cox
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√m/√k
Ref: [8], [11]
Scaling
General Scaling
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Circuit Parameter
Scaling
factor
Velocity
Saturation
Delay time (C*V/I)
1/mk
1/k
Power Dissipation (V*I)
m3/k2
m2/k2
Power – Delay product
(switching energy)
m2/k3
Circuit Density (1/Area)
k2
Power Density (P/Area)
m3
Sujay Desai IIT Bombay
Ref: [8], [11]
m2
Scaling
General Scaling
 General problems with scaling
 Increase in off current due to channel sub-threshold
leakage and gate leakage (tunneling due to band
bending and higher transverse field).
 Larger electric fields, cause reliability issues and
decreased mobility. Can also lead to velocity saturation.
 Larger non linearities affect use in analog applications.
 Short channel Effects degrade the performance of the
MOSFET as we go smaller. Need to study and
resolve them.
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Short Channel Effects
Vth roll off
DIBL
GIDL
Punch Through
RSCE
Velocity Saturation
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Short Channel Effects
Short Channel Effects
Electrostatic Potential contours for
channel length 2.5 um
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Electrostatic Potential contours for
channel length 0.5 um
Ref: [13]
Short Channel Effects
Short Channel Effects
 Effects of source-body and drain-body junctions on electrostatic
potential in channel of a short channel MOSFET are significant.
 Strong interaction between lateral and
transverse fields. Gradual channel
approximation (Ex >> Ey) in channel
invalid, hence long channel MOSFET
model fails. Need to model considering
2D field.
 Charge sharing model used to explain
short channel effects.
 Quantum effects start coming forth as
we move to very small channel lengths.
Bulk properties very different from those
at these scales.
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Sujay Desai IIT Bombay
Ref: [12], [13]
Short Channel Effects
Vth roll off
 Charge in channel near source and drain is
supported by both, gate voltage and the S/D
depletion regions.
 Charge sharing by S/D  lesser gate voltage
needed for channel inversion  Vth reduces (roll
off). Significant in short channel devices.
 Vth roll off is also due to another short channel
effect called DIBL.
Charge sharing by S & D
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Sujay Desai IIT Bombay
Short Channel Effects
Drain Induced Barrier Lowering (DIBL)
In short channel devices, VDS causes barrier lowering at source. Gate voltage
needed to overcome barrier and create inversion channel is lower. Vth reduces.
Vth(Saturation) is lower than Vth(linear). DIBL dependent on VDS. More pronounced
at larger VDS and hence in saturation.
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Short Channel Effects
DIBL
 VD↑  D-B depletion region grows with more
reverse bias. Lateral electric fields in D induced
depletion region lowers S-channel barrier,
allowing more carriers to diffuse from S to
channel.
 Typical DIBL values:∆Vth= –0.12V for ∆ Vd=1.2V
in 90nm
Vth roll off
due to DIBL
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Short Channel Effects
Gate Induced Drain Leakage (GIDL)
 Major drain leakage phenomena in off state




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MOSFETs . Observed at low Vg and high Vd.
Independent of channel length.
Observed in thin gate oxide MOSFETs at drain
voltages much lower than the junction breakdown
voltage.
Band to Band Tunnelling (BTBT) occurs in the
deep-depletion layer in the gate to drain overlap
region.
Sets constraint for the Vdd and Tox in VLSI
MOSFET scaling.
Sujay Desai IIT Bombay
Short Channel Effects
GIDL
 Thinner the gate oxide,
more is GIDL at given
Vgd.
 GIDL independent of
temperature.
 Variations in Eg with
temperature cause the
slight deviation seen in
region I.
Region I: GIDL
Region II: GIDL + impact
ionization
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Ref: [3]
Short Channel Effects
GIDL
 High vertical field. Depletion region deep into drain. Lateral field
sweeps holes towards substrate and electrons towards D.
 Thus Idb set up due to Gate induced field.
 BTBT constitutes the remaining current (band bending > Eg)
T ↑ implies Eg ↓ implies BTBT and GIDL ↑
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Ref: [3]
Short Channel Effects
 There are other short channel effects observed,




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mostly due to the high electric fields.
Velocity saturation.
Punch through: For short Lg at high Vds, S & D
depletion layers can touch each other (away from
interface). Direct flow of carriers from S to D with no
control of G. Sub surface phenomenon
Hot electrons: At high lateral fields, the high energy
carriers can enter oxide and get trapped. These
trapped charges cause Vth to change. These charges
can also cause impact ionization.
RSCE (Reverse short channel effect): Due to doping
techniques (halo implants, etc.) Vth roll off or roll on
observed.
Sujay Desai IIT Bombay
Resolution of Short Channel
Effects
Source/Drain Extensions
Halo Doping
Strained silicon
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Resolution of Short Channel Effects
Source/Drain (S/D) extensions
 The extension of S/D is a 2 step process. Effective
channel length < Gate length
 SDE is a shallow implant. Shallow implants (Xj) are
necessary while MOSFET scaling.
 The shallow implants result in lower S/D charge
sharing because of the depletion layer, hence
lowering DIBL, punch-through, Vth roll off and other
such effects. At the same time, it achieves the need to
scale Xj .
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Sujay Desai IIT Bombay
Ref: [4]
Resolution of Short Channel Effects
Halo/Pocket Implants
 Short channel effects can be reduced by employing





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lateral channel engineering.
Halo/pocket implants of high doping density are
implanted near the S/D.
These help to control RSCE, and the Vt roll off or roll
on.
Besides this, retrograde doping of the channel
lower/away from the surface also helps to improve Vt
roll off.
Excessive doping at D, reduces GIDL, by reduction of
tunneling due to lesser band bending.
Graded Gate oxide (GGO) increases oxide thickness
in overlap region. Less vertical electric field. Less
GIDL.
Sujay Desai IIT Bombay
Resolution of Short Channel Effects
Halo/Pocket Implants
 Pocket implants introduce a Vth roll on which counters the
general roll off due to other SCE.
 The dependence of Vth is approximately (Np)0.25 * Lp where
Np is doping density of implant and Lp is length of implant.
Graded Gate Oxide (GGO)
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Ref: [5]
Resolution of Short Channel Effects
Strained silicon
 Strained structures have different material properties
compared to bulk material, which can be used to
counter SCE.
 Strained silicon on insulator.
 Appropriate kind of stress can change energy bands
and improve carrier transport.
 Biaxial tensile stress improves electron transport
 Biaxial tensile or compressive stress improves hole
transport
 Variety of methods of introducing stress:




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Shallow trench isolation induced stress (during process)
Apply stressors to the device (after front-end process)
Bend the wafer/chip
Stress from epitaxial growth of Si on a relaxed SiGe
‘substrate’
Sujay Desai IIT Bombay
Ref: [6]
Resolution of Short Channel Effects
Strained silicon
 Strained Si grown on Si-Ge layer
 Electron and hole mobilities increase with strain in
silicon.
 Peak mobility ratios achieved for around 30% Ge
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Ref: [6]
Resolution of Short Channel Effects
Strained silicon
Problems: More heating, as Si-Ge has low (15 x) thermal conductivity
Channel hot carrier effects and surface roughness
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Ref: [6]
A modern MOSFET has most of
these structural modifications
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Summary
Summary
 MOSFET scaling will soon reach a dead end, with
quantum and short channel effects, severely
altering performance and affecting reliability.
 Physical limitation of sub-threshold slope to
60mv/decade. Severe constraint on speed of
circuits. Need to look for alternate structures like
tunnel FETs, Fin FETs, etc
 New materials like Hf oxides are being used as
high-k dielectrics replacing SiO2 . However
problems of poor interface, flicker noise,
scattering, etc increase. Need to research new
materials.
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Summary
 Non classical structures like Multi gate FETs
being researched.
 Future…
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Sujay Desai IIT Bombay
Ref: [7]
References
1.
2.
3.
4.
5.
6.
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Physics of Semiconductor Devices; 2nd Edition; S.
M. Sze, John Wiley and sons Inc.; 1981
Fundamentals of modern VLSI devices; Taur and
Ning; Cambridge University Press; 1998
The impact of Gate Induced Drain Leakage Current
on MOSFETs; C. Hu et. al. 718 – IEDM 87
MOSFETs Fabrication; E. F. Schubert; Rensselaer,
Polytechnic Institute, 2003
Short-Channel Effect Improved by Lateral ChannelEngineering in Deep-Submicron meter MOSFET’s;
IEEE Transactions on electron devices, vol.44, no.4,
April 97
Reliability Challenges for Strained Si CMOS; Judy
L. Hoyt; MIT; Oct 2002
Sujay Desai IIT Bombay
References
7.
8.
9.
10.
11.
12.
13.
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International Technology Roadmap for Semiconductors, (ITRS)
2005
Jesús del Alamo, course materials for 6.720J Integrated
Microelectronic Devices, Spring 2007. MIT OpenCourseWare
(http://ocw.mit.edu/), Massachusetts Institute of Technology
Fundamentals of semiconductor fabrication; S. M. Sze; John
Wiley and sons Inc.; 2005
Electronic Devices and Circuits course notes IIT Bombay –
Prof. Souvik Mahapatra, Autumn 2009
Semiconductor Physics and Devices; Donald Neamen; 3rd
Edition; Tata McGraw Hill; 2007
Analysis and design of MOSFETs; JJ Liou; Springer; 1998
http://www.stanford.edu/class/ee316/MOSFET_Handout5.pdf
Sujay Desai IIT Bombay
Thank You for your attention
I would like to thank Prof. Dasgupta for her guidance and
mentoring.
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BACKUP SLIDES
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MOSFET Operation
Energy Band Diagram
Vgs -Vfb > 0 and Vds = 0 for n - MOSFET
Along Y axis
Source  Channel 
Drain
Along X axis
at the oxide channel
interface
Gate Voltage results in lowering of the barrier at S/D junctions. The
applied gate voltage causes a depletion region to be formed in the
channel, as can be seen in the above figure. With higher gate voltages
the channel undergoes inversion.
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Sujay Desai IIT Bombay
MOSFET Operation
Sub-Threshold Region
Vgs < Vt and Vds > 0
 Sub-threshold slope for MOSFET can be
minimum of {(kT/q)*ln(10)}which is approximately
60mV/decade at 300K.
 Maximum switching speed of a MOSFET is
physically limited
 Need to look for alternate devices like Tunnel
FETs, operating on principle of quantum
tunneling, where sub-threshold slopes of as low
as 30mV/decade can be achieved.
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Sujay Desai IIT Bombay
Sub-Threshold Region
Vgs < Vt and Vds > 0
 Sub-threshold current given by
where
 Another important parameter is sub-threshold
slope S
 Here W = width, L = length, Ci = Cox = oxide
capacitance, Cd = depletion region capacitance.
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Sujay Desai IIT Bombay
Ref: Physics of Semiconductor Devices; 2nd Edn., S.M. Sze
:Taur and Ning
Scaling
Need for scaling
 Higher density circuits
 SSI, MSI, LSI, VLSI, ULSI, …..
Short Channel
 Higher Performance
L↓
Id ↑
τswitch ↓
 Low power consumption
L↓
Vdd ↓
 Simple L scaling compromises
Long Channel
electrostatic integrity &
leads to punch through
(discussed later).
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Ref: MIT Open Course ware; Integrated Microelectronic Devices;
Spring’07
Scaling
Constant Field
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Short Channel Effects
Punch Through
 For short Lg at high Vds, S & D depletion layers
can touch each other (away from interface).
Direct flow of carriers from S to D with no control
of G. Sub surface phenomenon
Long channel
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Short Channel. Punch
Through.
No gate control
Short Channel Effects
Velocity Saturation
 For short Lg, lateral electric field close to D
junction becomes very high as Vds is increased.
 Electron velocity saturates with lateral electric
field (when channel is not pinched off). No further
effect of Vds.
 IDsat increases linearly with overdrive voltage.
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Resolution of Short Channel Effects
Silicon on Insulator (SOI)
 Thin active Si layer on top of oxide viz. SiO2
 n+ S/D implants all the way upto oxide
 Reduced junction capacitances
 Higher speed.
 Substrate voltage is however floating.
 No current and heat path to substrate due to
Buried Oxide (BOX).
 Temperature increase degrades mobility
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