IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 12, DECEMBER 2011
4241
Asymmetrically Doped FinFETs for
Low-Power Robust SRAMs
Farshad Moradi, Member, IEEE, Sumeet Kumar Gupta, Student Member, IEEE,
Georgios Panagopoulos, Student Member, IEEE, Dag T. Wisland, Member, IEEE,
Hamid Mahmoodi, Member, IEEE, and Kaushik Roy, Fellow, IEEE
Abstract—We propose FinFETs with unequal source and drain
doping concentrations [asymmetrically doped (AD) FinFETs] for
low-power robust SRAMs. The effect of asymmetric source/drain
doping on the device characteristics is extensively analyzed, and
the key differences between conventional and AD FinFETs are
clearly shown. We show that asymmetry in the device structure
leads to unequal currents for positive and negative drain biases,
which is exploited to achieve mitigation of read–write conflict in
6T SRAMs. The proposed device exhibits superior short-channel
characteristics compared to a conventional FinFET due to reduced
electric fields from the terminal that has a lower doping. This
results in significantly lower cell leakage in AD-FinFET-based
6T SRAM. Compared to the conventional FinFET-based 6T
SRAM, AD-FinFET SRAM shows 5.2%–8.3% improvement in
read static noise margin (SNM), 4.1%–10.2% higher write margin, 4.1%–8.8% lower write time, 1.3%–3.5% higher hold SNM,
and 2.1–2.5× lower cell leakage at the cost of 20%–23% higher
access time. There is no area penalty associated with the proposed
technique.
Index Terms—Asymmetric doping, FinFET, SRAM.
I. I NTRODUCTION
A
GGRESSIVE device scaling has led to statistical variability in device parameters and increased short-channel
effects (SCEs) [1], [2]. Thinner gate oxide helps to improve
the SCEs. However, thinner gate oxide leads to exponentially
higher gate leakage. Thus, to overcome SCE, different candidate transistor structures have been investigated to replace the
bulk MOSFETs [3]–[10]. Among them, FinFETs are considered to be a promising candidate for scaled CMOS devices in
scaled technology nodes. FinFETs show increased immunity to
SCE due to improved channel control by the gate voltage [11].
Furthermore, threshold voltage (VTH ) can be easily controlled
Manuscript received March 1, 2011; revised August 21, 2011; accepted
September 14, 2011. Date of publication October 19, 2011; date of current
version November 23, 2011. The review of this paper was arranged by Editor
H. S. Momose.
F. Moradi is with the Integrated Circuit and Electronics Laboratory, Aarhus
School of Engineering, Aarhus University, 8000 Aarhus, Denmark (e-mail:
famo@ase.au.dk).
S. K. Gupta, G. Panagopoulos, and K. Roy are with the School of Electrical
and Computer Engineering, Purdue University, West Lafayette, IN 47907 USA
(e-mail: guptask@purdue.edu; gpanagop@purdue.edu; Kaushik@purdue.edu).
D. T. Wisland is with Novelda AS, 0319 Oslo, Norway, and also with
the Nanoelectronics Research Group, University of Oslo, 0316 Oslo, Norway
(e-mail: dagwis@ifi.uio.no).
H. Mahmoodi is with the School of Engineering, San Francisco State
University, San Francisco, CA 94132 USA (e-mail: Mahmoodi@sfsu.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2011.2169678
by engineering the metal gate work function. Moreover, VTH
variations due to random dopant fluctuation in the channel
region are reduced due to almost intrinsic channel doping
[12], [13].
Since memories take up 80% of the die area in highperformance processors, there is a need for high-performance,
low-leakage, and highly robust SRAMs [14]. Unfortunately
in scaled technologies, particularly under scaled supply voltages, the read and write stabilities of SRAMs are affected by
process variations. Due to a large number of small geometry
transistors in a memory array, process variations have a significant impact—leading to possible read, write, and access
failures, particularly at lower supply voltages. Furthermore,
in conventional 6T SRAMs, the conflict between read and
write stabilities is an unavoidable design constraint [15] and
aggravates the effect of process variations on SRAM stability
and performance.
One option to improve the conflicting read and write requirements is to decouple the read/write operations, for which
researchers have considered new bit cells such as 8T and 10T
[16], [17]. However, such cells come with an increased area.
Several other techniques have been proposed to improve the
6T SRAM stability, performance, and/or leakage by introducing optimized devices [18]–[28]. Although these techniques
improve device characteristics, the tradeoffs are not clearly addressed, and improvement in conflicting read and write margins
is marginal.
An interesting design option to achieve mitigation of
read–write conflict is to introduce asymmetry in the access
transistor such that unequal currents flow for positive and negative VDS ’s. One such technique uses asymmetric halo in bulk
MOSFETs [27]. However, this leads to aggravation of SCEs
and an increase in leakage of the device. For FinFETs, another
technique has been proposed in [28] in which asymmetric drain
underlap is introduced in the device (by employing asymmetric
spacers). In this technique, the drain-induced barrier lowering
(DIBL), subthreshold swing (SS), and subthreshold leakage
current are improved. However, asymmetric spacer FinFETs
may lead to increased variations in such devices.
In this paper, we propose to achieve asymmetry in the device
by unequally doping the drain and source terminals of FinFETs
[asymmetrically doped (AD) FinFETs]. Depending on the device biasing, the proposed modification to the device structure
leads to different currents from the source and the drain sides,
respectively. Based on that, we design a FinFET SRAM bit cell
to simultaneously improve read and write margins in scaled
0018-9383/$26.00 © 2011 IEEE
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and NDopS ], AD FinFETs exhibit asymmetry in the device
characteristics for positive and negative drain-to-source biases
(VDS ). In the rest of this paper, the polarity of VDS and the
dopant concentrations in the source/drain will be defined by
considering the terminal with lower doping as the drain and the
other terminal as the source. Therefore, VDS > 0 implies that
a higher bias is applied at the terminal with lower doping and
drain current (ID ) flows from the terminal with lower doping
to that with higher doping. Similarly, VDS < 0 implies that a
higher bias is applied at the terminal with higher doping and ID
flows from the terminal with higher doping to that with lower
doping. Furthermore, lower dopant concentration is represented
as NDopD , i.e., NDopD < NDopS for AD FinFETs.
In order to understand the effect of asymmetric source/drain
doping on the device characteristics, we now present a physicsbased discussion on the device electrostatics, drain current, gate
leakage, and capacitance of AD FinFETs. Two-dimensional
simulations are performed on AD and SD FinFETs using
Taurus [29] to analyze the effect of asymmetric source/drain
doping. The device parameters are shown in Table I. For
SD FinFETs, NDopD = NDopS = 1020 cm−3 is used. For the
discussion in this section, AD FinFETs are simulated with
NDopS = 1020 cm−3 and NDopD = 1019 cm−3 . We present the
discussion for n-type FinFETs only. This discussion can be
extended for p-type FinFETs as well.
A. Electrostatics of AD FinFETs
Fig. 1. (a) Device structure of AD FinFET. (b) Circuit symbols for n-type and
p-type AD FinFETs (the thicker line indicates the terminal with lower doping).
(c) Doping profile for asymmetric FinFET device.
technologies, thus mitigating the read–write conflict. In addition, AD FinFETs exhibit improved short-channel characteristics (lower DIBL, SS, and subthreshold current), which results
in significant reduction in leakage of AD-FinFET SRAM cell.
AD-FinFET SRAMs also show improvement in hold stability
and write time at the cost of increase in access time with no
area penalty.
The remainder of this paper is organized as follows. In
Section II, we present the proposed asymmetric FinFET, explaining the benefits compared to the conventional symmetric
FinFET. AD-FinFET SRAM is introduced in Section III and
compared with the conventional FinFET SRAM cell in terms
of cell stability, performance, leakage, and area. Finally, the
conclusions are drawn in Section IV.
II. AD FinFETs
Fig. 1 shows the structure and circuit symbols of the proposed AD FinFET. The device structure is similar to a conventional FinFET except for the doping concentrations in the
source and drain regions. In a conventional FinFET, the source
and drain regions are doped symmetrically. [Henceforth, conventional FinFET is referred to as symmetrically doped (SD)
FinFET.] On the other hand, the source and drain regions of AD
FinFETs are doped differently, such that one of the terminals
(defined as drain in Fig. 1) has a lower dopant concentration
than the other terminal (source in Fig. 1). Due to unequal
dopant concentrations in the two terminals [Fig. 1(c)NDopD
Fig. 2 shows the conduction band profiles for n-type AD and
SD FinFETs at gate voltage (VG ) = 0 V and VDS = 0, 0.9, and
−0.9 V. For VDS = 0 V, AD FinFETs show the conduction
band edge in the drain region (ECD ) at a higher energy than
that in the source region (ECS ). This is due to the fact that
NDopD < NDopS , which implies that (EF − ECD ) < (EF −
ECS ). (Here, EF is the Fermi level in the source and drain
regions at VDS = 0 V). Fig. 2 also shows a wider depletion
region on the drain side. At VDS = 0.9 V, a significant improvement in DIBL can be observed for AD FinFETs compared
to SD FinFETs. This is due to reduced electric fields from the
drain terminal due to the wider depletion region. Even at VDS =
−0.9 V (i.e., VD = 0 and VS = 0.9 V), DIBL improvement
can be observed. However, the improvement is less compared
to VDS = 0.9 V since the drain bias is applied at the terminal
with a higher dopant concentration. (Note that DIBL is defined
as the lowering of the barrier on the side of the terminal with
the lower bias induced by the terminal at the higher bias. For
VDS > 0, DIBL is induced by the terminal with lower doping,
defined as drain in Fig. 1, while for VDS < 0, DIBL is induced
by the terminal with higher doping, defined as source in Fig. 1.)
Fig. 2(a) also shows that the barrier height for AD FinFETs
is more compared to SD FinFETs, which implies lower OFF
current, which we shall discuss in the next section. It may be
mentioned that improvement in SCEs in AD FinFETs is not
due to the asymmetry in the device but because of lower electric
fields from the terminal with lower doping.
Fig. 3 shows the conduction band profiles for AD and SD
n-type FinFETs at VG = 0.9 V for positive and negative VDS ’s.
While SD FinFETs exhibit symmetric conduction band profiles
MORADI et al.: ASYMMETRICALLY DOPED FinFETs FOR LOW-POWER ROBUST SRAMs
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TABLE I
D EVICE PARAMETERS
Fig. 3. Conduction band profiles of SD and AD FinFETs for positive and
negative VDS ’s at VG = 0.9 V (SD: NDopS = NDopD = 1020 cm−3 ; AD:
NDopS = 1020 cm−3 and NDopD = 1019 cm−3 ).
Fig. 2. Conduction band profiles of SD and AD FinFETs for (a) positive and
(b) negative VDS ’s at VG = 0 V (SD: NDopS = NDopD = 1020 cm−3 ; AD:
NDopS = 1020 cm−3 and NDopD = 1019 cm−3 ).
for VDS = 0.9 and −0.9 V, asymmetry in the conduction band
profiles for AD FinFETs can be observed. The effect of increase
in the drain resistance due to lower doping is manifested in
the conduction band profile by more gradual (less sharp) band
bending in the drain region. The asymmetry in the conduction
band profiles shown in Fig. 3 results in asymmetry in the drain
and gate currents at positive and negative VDS ’s, which we
discuss next.
B. Current–Voltage Characteristics of AD FinFETs
Fig. 4 shows the drain current (ID ) versus VG characteristics
of n-type AD and SD FinFETs. For VDS > 0, AD FinFETs
exhibit 10× reduction in subthreshold current (ISUB ), 2.5×
reduction in DIBL, and 14% reduction in SS compared to
SD FinFETs. Improvement in short-channel characteristics is
obtained due to lower drain doping and, hence, reduced electric
field lines from the drain terminal affecting the source barrier.
Lower ISUB is due to higher source barrier, as is evident
from Fig. 2. For VDS < 0 (i.e., VD = 0 and VS = −VDS ), 3.5×
reduction in ISUB , 1.7× reduction in DIBL, and 4% reduction
in SS are achieved compared to SD FinFETs. Improvement in
subthreshold characteristics of AD FinFETs comes at the cost
of ON current (ION ), which can also be seen in Fig. 5. AD
FinFETs show 7% and 36% degradations in ION with respect to
SD FinFETs for VDS > 0 and VDS < 0, respectively. Reduction
in ION for VDS > 0 can be attributed to the increase in drain
resistance due to lower NDopD . For VDS < 0, degradation in
ION is higher because the terminal which acts as the source
for the carriers (electrons, in this case) has a lower doping
and lower carrier concentration in its vicinity which leads
to reduction in current. The asymmetry in ID for positive
and negative VDS ’s is evident in Fig. 5, and this property of
AD FinFETs is exploited to achieve mitigation in read–write
conflict in SRAMs, as will be discussed in the next section.
The differences in current–voltage characteristics of AD and
SD FinFETs are summarized in Fig. 6.
C. Gate Leakage in AD FinFETs
Gate current (IG ) characteristics of AD and SD FinFETs
are shown in Fig. 7. IG has two components—direct tunneling
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Fig. 6. Comparison of device characteristics of AD and SD FinFETs (SD:
NDopS = NDopD = 1020 cm−3 ; AD: NDopS = 1020 cm−3 and NDopD =
1019 cm−3 ).
Fig. 4. Transfer characteristics of AD and SD FinFETs for (a) positive
VDS and (b) negative VDS ’s (SD: NDopS = NDopD = 1020 cm−3 ; AD:
NDopS = 1020 cm−3 and NDopD = 1019 cm−3 ).
Fig. 7. (a) IG –VG and (b) IG –VDS for AD and SD FinFETs (SD:
NDopS = NDopD = 1020 cm−3 ; AD: NDopS = 1020 cm−3 and NDopD =
1019 cm−3 ).
channel. On the other hand, IET is dominant for VGS < VTH .
Let us discuss each of these cases one by one.
For high VGS , AD FinFETs show higher IG at VDS = 0.9 V
[Fig. 7(a)]. This can be explained by considering the following
relationship between gate voltage and surface potential (ψS ):
VGS = ψS + EOX ∗ tOX .
Fig. 5. Output characteristics of AD and SD FinFETs for (a) positive VDS and
(b) negative VDS ’s (SD: NDopS = NDopD = 1020 cm−3 ; AD: NDopS =
1020 cm−3 and NDopD = 1019 cm−3 ).
current (IDT ) and edge tunneling current (IET ). For VGS >
VTH (VTH is the transistor threshold voltage), IDT is the dominant component of IG due to high carrier concentration in the
(1)
Here, EOX is the electric field in the gate dielectric and tOX
is the oxide thickness. From Fig. 3, it can be observed that
the conduction band edge in the channel for AD FinFET is
higher than that for SD FinFET at VDS = 0.9 V. This implies
lower ψS in the channel region (which is negative of conduction
band in electronvolts) and, hence, higher EOX , as suggested
by (1). Higher EOX leads to larger IDT and higher IG . At
VDS = −0.9 V, the conduction band edge for AD FinFET is
MORADI et al.: ASYMMETRICALLY DOPED FinFETs FOR LOW-POWER ROBUST SRAMs
Fig. 8.
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Variation of ION −IOFF ratio with (a) tSi (b) tOX , and (c) LG for AD and SD FinFETs.
lower, which implies higher ψS , lower EOX , and lower IG , as
can be observed in Fig. 7(a) at high VG . At VDS = 0 V, ψS for
SD and AD FinFETs are similar, which results in similar IG .
Fig. 7(b) shows that, as |VDS | increases, the difference between
IG ’s for AD and SD FinFETs increases.
For low VGS , AD FinFETs exhibit lower IG for VDS = 0.9 V
[Fig. 7(a)]. This is because the dominant component IET flows
between gate and drain (terminal at a higher bias), and since
drain has a lower doping and a reduced carrier concentration,
reduction in IET and IG is achieved. For VDS < 0 (VD = 0 and
VS = −VDS ), IET flows between the gate and the terminal with
higher doping (which is the same as in SD FinFETs). Hence,
AD and SD FinFETs show similar IET and IG for VDS < 0.
D. Effect of Parameter Variations on Device Characteristics
In this section, we investigate the impact of variations in
device parameters like silicon body thickness (tSi ), gate oxide
thickness (tOX ), and gate length (LG ) on the characteristics of
AD and SD FinFETs. We vary the device parameters around its
nominal value (listed in Table I) and evaluate the degradation of
ION − IOFF ratio with respect to each parameter. (Note that the
OFF current IOFF is the sum of subthreshold current ISUB and
gate current (IG ) at VG = 0 V and |VDS | = 0.9 V). In order to
quantify the increase in ION −IOFF ratio over its nominal value
due to variation in device parameter (x—where x is tSi , tOX ,
and LG ), we define degradation in ION −IOFF ratio (D) as
ION ION ION nom IOF
/nom IOF
F − min IOF F
F
D=
.
(2)
|ext(x) − min(x)| /nom(x)
Here, max, ext, and nom refer to maximum, extreme, and
nominal values of their arguments. Note that the extreme value
is the maximum or minimum value of the parameter which
results in minimum ION −IOFF ratio. D, as defined in (2),
indicates the percent degradation in ION −IOFF ratio for 1%
change in the device parameter with respect to its nominal
value.
Fig. 8 shows the plot of ION −IOFF ratio versus the device parameters. It can be observed that AD FinFETs exhibit
consistently higher ION −IOFF ratio compared to SD FinFETs
for VDS > 0 and comparable ION −IOFF ratio for VDS < 0
for a range of tSi , tOX , and LG due to superior short-channel
characteristics of AD FinFETs. Also note that, as tSi and tOX
decrease or LG increases, ION −IOFF ratio for AD FinFETs
with VDS < 0 approaches that of SD FinFETs. This is because,
as tSi and tOX decrease or LG increases, ISUB starts to decrease
exponentially while IG is either relatively insensitive (e.g., with
respect to tSi and LG ) or increases exponentially (e.g., with
respect to tOX ). As a result, for small tSi , small tOX , and
large LG , IG starts to dominate IOFF . Recall that the IG at
VG = 0 and |VDS | = 0.9 V is similar for SD and AD FinFETs
when VDS < 0, while ION is relatively lower for AD FinFETs.
Hence, ION −IOFF ratio for AD FinFETs (VDS < 0) starts to
approach that of SD FinFETs for small tSi , small tOX , and large
LG . On the other hand, for VDS > 0, AD FinFETs have lower
IG at VG = 0 and |VDS | = 0.9 V compared to SD FinFETs and
hence show higher ION −IOFF ratio across the entire range of
parameters. Let us now compare the degradation in ION −IOFF
ratio of AD and SD FinFETs due to the variation in the device
parameters. Fig. 8 shows the degradation of ION −IOFF ratio
with increasing tSi , increasing tOX , and decreasing LG due to
degradation of SCEs. Since AD FinFETs exhibit superior shortchannel characteristics compared to SD FinFETs, the effect of
variation in device parameters is reduced. SD FinFETs show
3.87%, 3.74%, and 3.98% degradations in ION −IOFF ratio
for 1% tSi , tOX , and LG variations, respectively. AD FinFETs
show 3.63%, 3.44%, and 3.88% degradations in ION −IOFF
ratio for VDS > 0 and 3.47%, 5.4%, and 3.92% degradations
in ION −IOFF ratio for VDS < 0 for 1% variations in tSi , tOX ,
and LG , respectively. Higher variation with respect to tOX in
AD FinFETs at VDS < 0 compared to SD FinFETs is due to
the effect of the gate current, as described previously in this
section.
Fig. 8(c) shows another important advantage of AD FinFETs.
As LG is scaled, larger improvement in ION −IOFF ratio of
AD FinFETs with respect to SD FinFETs is observed. Hence,
the proposed technique provides an alternate method to control
SCEs in scaled technology nodes, at which other device design
techniques like scaling of fin thickness and oxide thickness may
be challenging due to quantum mechanical effects and increase
in gate leakage, respectively.
E. Comparison With Previously Proposed
Asymmetric MOSFETs
In this section, we compare AD FinFETs with the MOSFETs
with asymmetric halo proposed in [27] and FinFETs with asymmetric drain underlap proposed in [28]. In [27], MOSFETs with
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Fig. 9. Schematic of AD-FinFET-based 6T SRAM showing voltages at different nodes during (a) read operation and (b) write operation and (c) thin-cell layout
of AD-FinFET-based SRAM.
asymmetric halo suffer from increased SCEs compared to the
conventional MOSFETs. On the other hand, AD FinFETs show
significant improvement in SCEs compared to SD FinFETs.
The asymmetric FinFETs proposed in [28] show improvement
in SCEs like AD FinFETs compared to conventional FinFETs.
However, introducing asymmetric underlap in FinFETs is much
more challenging from the point of view of fabrication than
doping the source and drain terminals with different dopant
concentrations. Although both AD FinFETs and the FinFETs
proposed in [28] require an extra mask, AD FinFETs are much
simpler to fabricate.
With the understanding of the device characteristics of
AD FinFETs discussed in this section, let us now present
AD-FinFET-based 6T SRAMs and evaluate their benefits over
conventional FinFET 6T SRAMs.
III. AD-FinFET-BASED 6T SRAM
Fig. 9 shows the schematic of the proposed AD-FinFETbased 6T SRAM (during read and write operations) along with
the thin-cell layout. The thick line on the transistors indicates
the terminal with lower doping. Note that, for the pull-down
(NL and NR) and access transistors (AXL and AXR), the terminals with lower doping are connected to the same nodes (the
storage nodes). Hence, the contacts of access transistors can be
shared with those of the corresponding pull-down transistors
[Fig. 9(c)], as in conventional FinFET SRAMs. Thus, there is
no area penalty associated with the proposed technique. Let us
now discuss the operation of AD-FinFET SRAM and explain
the mitigation of read–write conflict achieved by exploiting the
asymmetry.
A. Cell Operation
During the read operation, bitlines BL and BLB are
precharged to the power supply voltage (VDD ). Let us assume
(without any loss of generality) that node “Q” stores “0” and
“QB” stores “1.” On asserting the wordline, the voltage at node
“Q” (VQ ) rises to a positive voltage VREAD , which depends on
the resistive divider action of AXL and NL. Read failure may
occur if VREAD becomes greater than the trip point (VM ) of
the inverter formed by AXR, NR, and PR. Hence, for higher
read stability, low strength of the access transistors is desired.
During the write operation, BL is precharged to VDD , and BLB
is discharged to GN D. On asserting the wordline, the voltage at
QB (VQB ) is discharged to a voltage VWRITE depending on the
resistive divider action of PR and AXR. If VWRITE is less than
VM of the inverter formed by PL and NL, write operation occurs
successfully. For superior write ability, high strength of AXR is
desired. Note the conflicting requirements for the strength of
the access transistor in a conventional FinFET SRAM for high
read and write stabilities.
In AD-FinFET-based SRAM, mitigation of the aforementioned read–write conflict is achieved. During the read operation of AD-FinFET SRAM [Fig. 9(a)], the terminal of AXL
with the lower doping (indicated by the thick lines) is at a lower
voltage than the other terminal (i.e., VDS < 0 for AXL; recall in
Section II that the terminal with the lower doping was defined as
the drain). Hence, the strength of AXL is reduced (see Figs. 5
and 6), which lowers VREAD and increases the read stability.
During the write operation of AD-FinFET SRAM [Fig. 9(b)],
the terminal of AXR with a lower doping concentration (drain)
is at a higher voltage than the other terminal (source), i.e.,
VDS > 0. Therefore, the strength of AXR is larger (see Figs. 5
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Fig. 10. (a) Read SNM and write margin. (b) Hold SNM and cell leakage. (c) Cell write time and access time versus drain doping (NDopD ). NDopD =
1020 cm−3 corresponds to SD FinFET SRAM. The rest of the points on the x-axis are for AD-FinFET SRAMs with different values of drain doping.
Fig. 11. (a) Read SNM, (b) write margin, (c) hold SNM, (d) cell access time, (e) cell write time, and (f) cell leakage versus VDD . (SD FinFET SRAM:
NDopS = NDopD = 1020 cm−3 ; AD-FinFET SRAM: NDopS = 1020 cm−3 and NDopD = 2 × 1019 cm−3 ).
and 6), which results in higher write ability. The mitigation of
read–write conflict in AD-FinFET SRAMs comes at the cost
of larger access time due to weak access transistors during the
read operation.
Let us now quantify the stability, performance, and leakage
of an AD-FinFET SRAM and compare it with a conventional (SD) FinFET SRAM. We simulate AD-FinFET SRAMs
with different drain dopant concentrations (NDopD ) less than
the source doping (NDopS = 1020 cm−3 ). For SD FinFET,
NDopD = NDopS = 1020 cm−3 .
B. Comparison of AD and SD FinFET SRAMs
Fig. 10(a) shows the read static noise margin (SNM) versus
NDopD . An increase ranging from 2.1%–7.3% in read SNM can
be observed for AD-FinFET SRAM compared with SD FinFET
SRAM (corresponding to NDopD = 1020 cm−3 ). At the same
time, 2.9%–23% improvement in write margin [30] is achieved
for AD FinFETs [Fig. 10(a)], thus resulting in the mitigation of
read–write conflict. In addition, due to superior short-channel
characteristics of AD FinFETs, 0.5%–1.3% increase in hold
SNM and 1.3–2.8× reduction in cell leakage can be observed
[Fig. 10(b)]. Improvement in cell write time ranging from
3%–12% is also achieved [Fig. 10(c)] due to lower NDopD and,
hence, lower capacitance at the storage nodes in AD-FinFET
SRAM compared to SD FinFET SRAM. Fig. 10(c) also shows
the 6%–42% higher cell access time, which is due to weaker
access transistor during read.
To sum up, AD-FinFET SRAM shows simultaneous improvement in the read stability, write ability, cell write time,
hold stability, and cell leakage at the cost of increase in the
access time. There is no area penalty associated with the
proposed technique [Fig. 9(c)].
C. Analysis Across a Range of VDD ’s
In this section, we compare SD FinFET SRAM (NDopD =
NDopS = 1020 cm−3 ) with AD-FinFET SRAM (NDopD =
2 × 1019 cm−3 and NDopS = 1020 cm−3 ) across a range of
supply voltages (0.6–0.9 V). Fig. 11 shows the comparison
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of read SNM, write margin, hold SNM, cell leakage, cell
access time, and cell write time for different VDD ’s. Compared with SD FinFET SRAM, AD-FinFET SRAM shows
5.2%–8.3% higher read SNM, 4.1%–10.2% higher write margin. 1.3%–3.5% improved hold SNM, 2.1–2.5× lower cell
leakage, and 4.1%–8.8% lower cell write time at the cost of
20%–23% larger cell access time. The benefits of AD-FinFET
SRAM in terms low power and high cell stability are evident
across a range of VDD ’s.
IV. C ONCLUSION
We have proposed AD FinFETs in which the source and
drain regions are doped with different dopant concentrations.
Asymmetry in the device structure results in unequal currents
for positive and negative drain biases, which is exploited
to achieve mitigation of read–write conflict in 6T SRAMs.
AD FinFETs also show superior short-channel characteristics,
viz., lower DIBL, reduced SS, and lower subthreshold current.
As a result, AD-FinFET SRAMs show significant reduction
in cell leakage and increase in hold stability. Simultaneous
improvement in read stability, write ability, cell write time, hold
stability, and cell leakage is achieved for AD-FinFET SRAMs
compared to conventional SD FinFET SRAMs, at the cost of
increase in cell access time. There is no increase in the cell area
of AD-FinFET SRAMs compared to SD FinFET SRAMs.
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Farshad Moradi (S’09–M’11) received the B.S.
degree in electrical engineering from Isfahan University of Technology, Isfahan, Iran, in 2001, the
M.S. degree in electrical engineering from Ferdowsi
University of Mashhad, Mashahd, Iran, in 2005, and
the Ph.D. degree from the University of Oslo, Oslo,
Norway, in 2011.
From 2005 to 2008, he was a Senior Lecturer
with Ilam University, Ilam, Iran. From 2009 to 2010,
he visited the Nanoelectronic Laboratory, Purdue
University, West Lafayette, IN. He is currently an
Assistant Professor with the Integrated Circuit and Electronics Laboratory,
Aarhus School of Engineering, Aarhus University, Aarhus, Denmark. His
current research interests include ultralow-power digital/memory circuit/device
design for low-power applications.
MORADI et al.: ASYMMETRICALLY DOPED FinFETs FOR LOW-POWER ROBUST SRAMs
Sumeet Kumar Gupta (S’05) received the B.Tech
degree in electrical engineering from the Indian Institute of Technology, Delhi, India, in 2006 and the
M.S. degree in electrical and computer engineering
from Purdue University, West Lafayette, IN, in 2008,
where he is currently working toward the Ph.D.
degree in the School of Electrical and Computer
Engineering.
In 2007, he was an intern with Advanced Micro
Devices Inc. In 2010, he was a summer intern with
Intel Corporation, Hillsboro, OR. His research interests include nanoscale device modeling and low-power digital circuit design.
Mr. Gupta was the recipient of the Magoon Award and the Outstanding
Teaching Assistant Award from Purdue University in 2007 and the Intel Ph.D.
Fellowship Award in 2009.
Georgios Panagopoulos (S’05) received the
Diploma degree (with honors) in computer and
communication engineering from the University of
Thessaly, Volos, Greece, in 2006. Since 2007, he has
been working toward the Ph.D. degree in electrical
and computer engineering in the School of Electrical
and Computer Engineering, Purdue University, West
Lafayette, IN.
From 2006 to 2007, he was a Research Assistant
with the University of Thessaly, Greece, where he
designed analog circuits. He was a summer intern
with Intel Corporation in 2011. His current research interests include very large
scale integration device/circuit codesign for nanoscaled silicon and nonsilicon
technologies for reliable and low-power applications.
Mr. Panagopoulos has received Academic Excellence Awards and several
scholarships during his studies.
Dag T. Wisland (M’00) received the M.Sc. and
Dr.Sc. degrees in electrical engineering from the
University of Oslo, Oslo, Norway, in 1996 and 2003,
respectively.
He is a Cofounder and currently the CEO of the
fabless semiconductor company Novelda AS, Oslo,
and is also a part-time Associate Professor with the
Nanoelectronics Group, University of Oslo. From
2004 to 2008, he was heading the Nanoelectronics
Research Group, University of Oslo. His current
research interests include low-power analog/mixedsignal CMOS design, ultrawideband radio, and design of ADC/DAC with a
particular focus on delta–sigma data converters. In his research, he has focused
on conceptually new methods and topologies combined with low-power design.
Dr. Wisland is a TC member of the IEEE CAS Society Analog Signal
Processing and Biomedical Circuits and Systems technical committees.
4249
Hamid Mahmoodi (S’00–M’05) received the B.S.
degree in electrical engineering from Iran University
of Science and Technology, Tehran, Iran, in 1998, the
M.S. degree in electrical and computer engineering
from the University of Tehran, Tehran, in 2000, and
the Ph.D. degree in electrical and computer engineering from Purdue University, West Lafayette, IN,
in 2005.
He is currently an Associate Professor of electrical and computer engineering with the School
of Engineering, San Francisco State University,
San Francisco, CA. His research interest includes low-power, reliable, and
high-performance circuit design for nanoscale technologies. He has many
publications in journals and conferences and is the holder of five U.S. patents.
Dr. Mahmoodi was a recipient of the 2008 SRC Inventor Recognition Award,
the 2006 IEEE Circuits and Systems Society VLSI Transactions Best Paper
Award, the 2005 SRC Technical Excellence Award, and the Best Paper Award
of the 2004 International Conference on Computer Design. He is a technical
program committee member of the International Symposium on Low Power
Electronics Design and the International Symposium on Quality Electronics
Design.
Kaushik Roy (F’02) received the B.Tech. degree in
electronics and electrical communications engineering from the Indian Institute of Technology (IIT),
Kharagpur, India, and the Ph.D. degree from the
Electrical and Computer Engineering Department,
University of Illinois, Urbana, in 1990.
He was with the Semiconductor Process and Design Center, Texas Instruments, Dallas, where he
worked on FPGA architecture development and lowpower circuit design. He was a Research Visionary
Board Member of Motorola Laboratories (in 2002)
and held the M. K. Gandhi Distinguished Visiting Faculty at IIT, Bombay,
India. Since 1993, he has been with the School of Electrical and Computer
Engineering, Purdue University, West Lafayette, IN, where he is currently a
Professor and holds the Roscoe H. George Chair of Electrical and Computer
Engineering. He is Purdue University Faculty Scholar. He has published
more than 500 papers in refereed journals and conferences, is the holder of
15 patents, has graduated 51 Ph.D. students, and is the coauthor of two books
on Low Power CMOS VLSI Design (John Wiley and McGraw Hill). His
research interests include spintronics, VLSI design/CAD for nanoscale silicon
and nonsilicon technologies, low-power electronics for portable computing and
wireless communications, VLSI testing and verification, and reconfigurable
computing.
Dr. Roy has been in the editorial board of the IEEE D ESIGN AND T EST,
IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS, and IEEE T RANSAC TIONS ON VLSI S YSTEMS . He was a Guest Editor for the Special Issue on
Low-Power VLSI in the IEEE D ESIGN AND T EST (in 1994), IEEE T RANSAC TIONS ON VLSI S YSTEMS (in June 2000), and IEE Proceedings—Computers
and Digital Techniques (in July 2002). He was a recipient of the National
Science Foundation Career Development Award in 1995, IBM Faculty Partnership Award, ATT/Lucent Foundation Award, the 2005 SRC Technical
Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, the 2010 IEEE
Circuits and Systems Society Technical Achievement Award, Distinguished
Alumnus Award from IIT, Kharagpur, the 2005 IEEE Circuits and System
Society Outstanding Young Author Award (with Chris Kim), the 2006 IEEE
T RANSACTIONS ON VLSI S YSTEMS Best Paper Award, and the Best Paper
Awards at the 1997 International Test Conference, the 2000 IEEE International
Symposium on Quality of IC Design, the 2003 IEEE Latin American Test
Workshop, the 2003 IEEE NANO, the 2004 IEEE International Conference on
Computer Design, and the 2006 IEEE/ACM International Symposium on Low
Power Electronics and Design.