IETE Mumbai Centre
NateHCA-07
25nm Triple-Gate FinFETs with Raised Source/Drain:
A 3D Simulation Study
D Mitra and C K Maiti
Department of Electronics and ECE, IIT Kharagpur, Kharagpur – 721302, India
Abstract: This paper targets to show feasibility of a three-dimensional process simulation flow in the
context of optimization of the device design. Technology CAD (TCAD) simulation tools are used for the
development of SOI-based 65 nm node triple-gate raised source/drain FinFET devices. The aim of this
work is to implement a complete FinFET process flow in a commercially available 3D process simulation
environment and then analyzing the DC and RF behavior of the resulting device.
Keywords: Triple gate FinFET, Raised source/drain, ITRS.
series resistance are raised S/D and self-aligned
silicided S/D (salicide). Raised S/D (RSD) through
selective Ge, and SiGe growth and CoSi2 on S/D has
earlier been implemented in FinFETs [8-10].
Selective Si epitaxy was used in this process flow to
increase the fin thickness in regions outside the
spacer. The thickened source/drain regions help to
decrease the overall parasitic resistance.
Introduction
Over the last few years, it has been widely accepted
that silicon-on-insulator (SOI)-based multiple gate
MOS devices would be required for extending the
Moore’s law towards the end of the International
Technology Roadmap of Semiconductors (ITRS) [1].
The Fin field effect transistor (FinFETs) is a SOI
based multiple gate structure, which is recently
emerging as a leading structure to continue the scaling
of CMOS technology into the nanometer regime. This
promising multiple gate structure has not only the
advantage of reducing short channel effects but also
of being compatible with the conventional planar
CMOS technology. The two most important FinFET
structures are the triple-gate (TG) and double-gate
(DG) SOI MOSFETs, owing to their inherent
capability for suppression of short channel effects
(SCEs), reduced drain-induced barrier lowering and
excellent scalability.
In this work, 3D process and device simulations have
been carried out on raised source/drain triple-gate
FinFETs having (100) sidewall with <100> current
flow direction to satisfy ITRS specifications for the
65 nm node high performance (HP) logic generation.
Device figure of merits such as intrinsic delay (τ = Cgg
Vdd/Ion), off-current (Ioff) and (Ion/Ioff) ratio for TG
FinFETs have been calculated.
.
Process Simulation
As the 3D structures of FinFETs are complex and
also, beyond 50 nm gate length, the channel profile
needs critical adjustment for setting the threshold
voltage, conventional 1D and/or 2D TCAD
simulations (i.e., process and device simulation) are
not suitable from the point of view of accuracy and
predictability. In this work, a complete FinFET
process flow has been implemented in TAURUS
process and device simulators [7] from Synopsys due
to its 3D simulation capability. The process flow
suggested in [12] has been followed. The critical
process steps are listed below:
1) Si on 100 nm BOX
2) 60 nm TEOS deposition
3) Patterning of fin, dry etching
4) Implantation of channel by boron (such that fin
doping is 1015 cm-3)
5) Sacrificial oxidation
6) Gate oxide 1.3nm (according to ITRS
Recently, 3D numerical simulations have shown that
the triple-gate FinFET is beneficial than double gate
FinFET since on current is enhanced in TG FinFET
(due to positive influence of the corner effect) and the
leakage current is suppressed [2-4] . Recently, it has
also been proposed that the electrical isolation of the
top gate electrode results in more parasitic gate
capacitance for double-gate FinFETs, which results in
severe degradation in the intrinsic delay [5]. For 65
nm technology node and below, the choice of triplegate FinFETs is therefore advantageous, since it has
been found to provide better design flexibility along
with minimum intrinsic delay and better RF
performance [6] than double-gate FinFETs.
In a FinFET, the source/drain resistance may be a
significant component of parasitic series resistance.
Two common methods of reducing this component of
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thin gate oxide. As has been shown in [10], the effect
of the GIFBE on the measurements of Gm is
successfully suppressed at frequencies above 100
kHz.
requirement)
Gate-poly-Si of 50 nm height
Patterning of gate
Nitride-spacer, 25 nm
Selective Si-epitaxy for S/D regions, 60 nm
(Raised source/drain)
11) S/D-implantation by Arsenic
12) Junction Anneal
7)
8)
9)
10)
Three different TG FinFETs with aspect ratios (=
Hfin/Tfin) < 5 were simulated with varying height and
thickness of the silicon fin, i.e., TG1: Hfin = 45nm, Tfin
= 10 nm, TG2: Hfin = 42.5 nm, Tfin = 15 nm and TG3:
Hfin = 40 nm, Tfin = 20 nm. The width (= 2 Hfin + Tfin,
i.e., the total active silicon area under the gate) has
been kept constant by varying Hfin and Tfin values
appropriately in the normalization. This was done to
ensure that all devices can be considered to have the
same effective width.
All the FinFETs have (100) sidewall channel with
<100> current flow direction. This has been achieved
on a standard (100) Si starting substrate with <110>
notch by rotating the fin layout orientation by 45º.
The simpler but reasonably good equilibrium
diffusion model (PD Fermi, equilibrium point defect
concentrations) and the dual Pearson implantation
models were used in the process simulation using
default model parameters. Only quarter of the device
was used in the process simulation. The device was
then reflected twice at the end of the process flow to
get the complete device for device simulation.
As the tall vertical structure of the FinFET device
presents significant challenges to device fabrication,
the aspect ratio is technologically limited to 5. Supply
voltage of 1.1 V was used in all the simulations
according to ITRS requirements. Gate work function
of 4.4-4.7 eV, the lateral source/drain doping gradient
(d) of ≈5 nm/dec, defined by its gradient at the gate
edge, and the source/drain doping roll off width (s) of
Lg were used for all the devices as these parameters
represent a relatively optimal profile for source/drain
extension (SDE) region design. Fig. 1 shows the
variation of source/drain doping gradient (d) along the
channel for the fixed spacer width of Lg:
Device Simulation
Device simulations have been performed using the
drift-diffusion model with a modified expression of
saturation velocity. Quantum confinement effects for
sub 0.1 micron devices have been taken into account
by including the modified local density approximation
(MLDA) model. Also the bandgap narrowing effects,
low field (doping and temperature dependent) and
high field mobility models (Caughey-Thomas model)
and the Lombardi surface scattering mobility model
have been included. Because of the ultra-short
channel (25 nm) of FinFETs, quasi-ballistic effects
were included in the device simulation using a gate
length dependent velocity saturation model, valid in
the high-field region of the device operation. The gate
length dependent saturation velocity [5] (in units of
107 cm s−1) is given by
vsat (Lg) = 2.0 + (19.2/Lg 1.43)
(1)
provides a reasonable estimation of on current and
was used in the present work. Other physical effects
such as, SRH and Auger recombination mechanisms
were also included in the device simulation.
AC analysis has been done at a frequency of 1 MHz
to eliminate the problem associated with the gateinduced floating-body effect (GIFBE), which is
unavoidably present in advanced silicon-on-insulator
(SOI) MOSFETs due to direct tunneling through the
Fig. 1: Variation of doping along silicon fin for raised
source/drain TG FinFETs
The transfer characteristics for the three TG FinFETs
at a gate work function of 4.5 eV are shown in Fig. 2
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for two different drain voltages-
As is evident from the above table, FinFETs with thin
silicon fins exhibit enhanced short channel immunity,
due to better control of the channel by the gates,
leading to relatively low values of the off-current (Ioff)
and higher(Ion/Ioff )values. With an increase in Hfin, the
top gate loses control over the channel and the two
side gates mainly govern current conduction. This
results in a degradation of SCEs—lowering of Vth and
increase in DIBL and S-slope. Therefore, as far as
controlling SCEs is concerned, TG FinFET devices
should be designed with lower aspect ratios. From the
table, it is seen that the TG1 device is able to achieve
the ITRS HP 65nm node target corresponding to
(Ion/Ioff) =2.16x104.
As the TG FinFETs analyzed in the present work are
undoped devices, a reduction in the fin thickness is
needed to reduce SCEs. This is because the
subthreshold current flows through the entire volume
of an undoped device and corner effects, which
reduce short channel effects in a highly doped device,
are significantly minimized.
Fig. 2: Transfer characteristics of raised source/drain TG FinFETs
(a) 0-TG1 (b) *-TG2 (c) x-TG3
Fig. 3 shows the cut-off frequency (fT), for different
TG FinFETs as a function of drain current. The three
different TG devices achieve nearly the same fT at
higher drain currents, whereas at lower Ids values,
TG1 performs better due to its excellent short channel
immunity because of a thinner fin thickness. The cutoff frequency values obtained by simulation
reasonably fit the trends of reported experimental
data, although available experimental data for fT are
somewhat limited.
As is evident from Fig. 2, TG3 devices exhibit larger
values of drain current because of lower threshold
voltage due to SCEs. TG1 devices exhibit the lowest
value of drain current.
Table 1 shows the dc figures of merit for the TG
FinFETs for a gate work function of 4.5 eV. The
threshold voltage (Vth) was defined as the gate bias
when the drain current reaches 400 nA × (Wg/Lg) =
1.6 µA for all the devices. Ioff was defined at Vgs=0 V
and Vds = 1.1 V. Similarly, Ion was defined at Vgs = 1.1
V, Vds = 1.1 V. DIBL was defined as Vth (at
Vds=1.1V)-Vth (at Vds=0.05V).
As the cut-off frequency (fT) is defined as fT =
gm/(2πCgg), the ability of device architecture to
achieve higher fT values depends on achieving a
higher gm along with a reduced value of Cgg. Fig. 4(a)
shows the values of gm for various devices in
saturation. All FinFET devices achieve almost the
same gm. Fig. 4 (b) shows the variation of the total
gate capacitance (Cgg = Cgs + Cgd + Cgb, where Cgs, Cgd
and Cgb are the gate-source, gate-drain and gatesubstrate capacitances, respectively) for TG FinFETs
as a function of the applied gate bias. At lower gate
bias, when the aspect ratio is increased, the
contribution of the top gate to the total parasitic
capacitance becomes negligible and the parasitic
capacitance gradually decreases resulting in increased
fT as in the case of TG1 device at lower values of
drain current. It has been shown [6] that this parasitic
capacitance associated with the complex threedimensional fin architecture is larger than the parasitic
Table 1
DC figures of merit for various FinFETs simulated
Device parameters: Lg=25nm, EOT=1.3nm, Φm=4.5eV
S-slope
(mV/dec.)
DIBL
(mV/V)
TG1
Vth (V)
@Vds=
Vdd
0.194
65.3
39
(Ion/Ioff)
@Vds=
Vdd
6.01x104
TG2
0.128
73
61
3.3x103
TG3
0.059
88
110
3.8x102
Devices
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capacitance in planar MOSFETs and is extremely
difficult to minimize and thus limits the RF
performance of FinFETs.
Fig. 4 (b): Cgg as a function of gate voltage for raised source/drain
TG FinFETs (a) 0-TG1 (b) *-TG2 (c) x-TG3
Intrinsic delay (τ) and off-current (Ioff)
In order to compare various FinFET structures, we
have calculated the intrinsic delay (τ = Cgg Vdd/Ion),
where Cgg is the total gate capacitance, instead of
examining the normalized drain current (mAmm−1).
This is because τ is a better figure of merit [5] of a
device as it includes the capacitance associated with a
structure (extremely important in a nonplanar
multiple-gate device) as well as current drivability
(Ion). Further, τ provides an unambiguous figure of
merit for a given device architecture, irrespective of
the different possible ways of defining the ‘effective
gate width for a non-planar device. Fig. 5 shows the
τ–Ioff characteristics for the TG FinFETs along with
the ITRS requirements (dashed rectangle). For each
graph, the lower points correspond to TG1 devices,
and the topmost point is for TG3 devices. The result
shows that TG1 devices having gate work functions in
the immediate neighborhood of 4.5 eV are capable of
meeting ITRS 65 nm HP logic requirements (τ = 0.64
ps, Ioff=70 nA/µm). Gate material such as NiSi can be
used to achieve the desired performance.
Fig. 3: Cut-off frequency vs. drain current of raised source/drain
TG FinFETs (a) 0-TG1 (b) *-TG2 (c) x-TG3
Fig. 4 (a): Gm as a function of gate voltage for raised source/drain
TG FinFETs (a) 0-TG1 (b) *-TG2 (c) x-TG3
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that 3D TCAD simulations can provide an essential
contribution to find the optimal configuration of a
device.
References
[1]
International Technology Roadmap for Semiconductor, 2003 edition (http://public.itrs.net)
[2] J T Park, J P Colinge and C H Diaz, Pi-Gate SOI
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[3] A Burenkov and J Lorenz, Corner effect in double
and
triple gate FinFETs, Proc. ESSDERC 2003,
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[4] A Burenkov and J Lorenz, on the role of corner
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[11] D Lederer, D Flandre, and J P Raskin, AC behavior
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Fig. 5: Ioff-τ for TG devices with varying gate work function
values
Conclusion
Based on 3D process and device simulations, we
report on the performance assessment of raised
source/drain TG FinFETs for HP logic technology for
the 65 nm technology node. It is shown that TG
FinFETs with gate work function ~ 4.5 eV are more
likely to meet ITRS targets for 65 nm node HP
technology. New channel materials, such as, strained
silicon (with higher channel mobility) or
manufacturable multi-bridge channel architectures
need to be explored to improve the Ioff–τ trade-offs
and enhance the design space for TG FinFETs.
However, reduction of source/drain resistance, while
minimizing the parasitic capacitance in FinFETs, is
still a technological challenge. Our results suggest
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