University of Illinois at Urbana Champaign
Department of Electrical and Computer Engineering
c Robert Pilawa-Podgurski, 2016
Copyright ECE 598RPP - Advanced Power Electronics, Spring 2016
Issued: February 15th
Problem Set 2 - Compensation and Control
Due: Thursday, February 25th
Recommended Reading: Assigned manuscripts. Erickson and Maksimovic, Chapters 11 and 12.
Problem 2.1 - Compensation Galore
Pulse Width Modulator
Power Stage
Power Stage
Input Voltage
Figure 1: Schematic drawing of buck converter and control implementation.
Gvs (s)
Pulse Width Modulator
∆ Vos c
Sensor Gain
H (s)
Output Voltage
Figure 2: Block diagram of control.
In this problem, you have been tasked with designing and implement the control for a buck converter, as shown in
the figures above. You may assume that the switches, inductor, and capacitors are ideal components. The nominal
input voltage is 5 V, the output voltage is 1 V, and the desired output power is 5 W. The operating frequency
is 1 MHz, and you desire the inductor peak-to-peak ripple to be 8 A at an output power of 5 W. You want the
peak-to-peak output voltage ripple to be below 50 mV.
a) Chose L, C, and nominal duty cycle D to achieve the design objectives.
b) Plot the loop transfer function bode plot in MATLAB, including both gain and phase. You may assume that VM
in the PWM generator is 3 V.
c) Using the k-factor method outlined in your assigned reading, design a Type-III compensator with a phase margin
of 60 degrees, and the highest possible cross-over frequency. The highest recorded cross-over frequency that meets
the phase margin will be awarded exclusive bragging rights for the remainder of the spring 2014 semester. Plot the
bode plot of your compensated system, and clearly label the phase margin and cross-over frequency.
d) Implement your control solution in LTspice, and simulate the performance of your full closed-loop converter.
Provide plots of the response of your system (in terms of output voltage) to 1) a load step from 5 W to 2.5 W that
occurs as a linear transition in 10 ns. 2) An instantaneous change in input voltage from 5 to 4.5 V, for a 5 W constant
Problem 2.2 - Light Load
Figure 3 shows a synchronous buck converter, which we will analyze in this problem. The buck converter has an
input voltage of 12 V, and an output voltage of 3 V. The switching frequency is 500 kHz, and the inductor has value
12 µH, and the output capacitor is 500 µF. The switches have an on-state resistance of 10 mΩ, and the inductor DC
resistance is 20 mΩ. You may also assume that the switches have a linear fall and rise-time of 20 ns. See for example
q(t) q’(t)
Figure 3: Synchronous buck converter
Fig. 13.16 in Krein’s book. Using this notation, tturn−on = tturn−of f = 20 ns
a) Find an expression for the switch conduction losses as a function of the output power.
b) Find an expression for the inductor conduction loss as a function of the output power.
c) Find an expression for the switching losses of the two switches as a function of the output power.
d) Find an expression for the total converter losses (the sum of the three results you obtained above). You may
vs Pout , as well as
thus ignore capacitor loss and any core loss in this analysis. Plot Ploss vs Pout . Also plot PPloss
converter efficiency vs Pout .
e) Using LTSPICE (or your preferred simulation tool), simulate PFM operation, as discussed in lecture. Assume
that the output load is 200 mW, and that you are operating with a fixed number of pulses (3). You do not have to
implement a closed-loop regulator, but may find the modulation frequency empirically, and run your converter open
loop. Be sure to turn in plots that illustrate the PFM operation.
f) For the same 200 mW load, simulate the converter using regular forced CCM operation. Compare the inductor
RMS current between the light control technique and forced CCM. Note that LTSpice lets you evaluate RMS values
directly on the graph.
Problem 2.3 - Current Mode Control
Consider a continuous conduction mode buck converter to be operated under peak current mode control. The
converter parameters are fsw = 500 kHz, L = 16 µH, C = 800 µF, and Vout,ref = 24 V. What is the smallest
magnitude of compensating ramp that will yield stable dynamics for the ripple instability over an input voltage
range of 36 V < Vin < 72 V?