36
CHAPTER 3
IMPLEMENTATION OF TELECOM SMR
3.1
INTRODUCTION
The converter for Telecom application must have the following
features
High Input power factor (close to unity).
Low Harmonic distortion of input current.
Galvanic isolation between input and output.
High efficiency.
High power density, smaller size and weight.
Low conducted and radiated emissions.
Parallel operation with Load sharing.
Modular and Hot Swappable
In this chapter the design procedure of the benchmarked boost
converter, implemented as a PFC is discussed in detail. A novel technique is
used to maintain low line distortion and stability at light output loads.
Half bridge ZVS resonant converter is selected for DC/DC
converter for the following reasons.
1.
High efficiency, since no switching loss
2.
No additional devices are used to achieve ZVS as inherent
leakage inductance of transformer and switch capacitance can
be utilized
37
3.
Low conducted and radiated emissions
4.
Input voltage is regulated (output of PFC) and hence it can be
optimized.
This SMR/converter is implemented in 5 KW modules for use in
Modular Power Supply system. The three-phase module consists of three
single-phase modules one for each phase with a common monitoring circuit
and enclosure as shown in Figure 3.1. Each single phase module consists of a
power factor correction (PFC) front-end converter stage and a DC/DC
converter to regulate the 48 V DC (54V float voltage for VRLA battery)
distributed power bus and a novel active current sharing circuit for load
sharing as shown in Figure 3.2. This current sharing circuit requires only a
single wire for communication between the modules. In addition to the above,
each module incorporates a module controller based on an 8-bit
microcontroller to monitor all the input and output parameters for fail-safe
operation of the power supply. Description of RFI/EMI filter, its design
procedure and the source of generation and suppression of electromagnetic
noise are also discussed.
R
S IN G LE
P H A SE
M O D U LE
Y
S IN G LE
P H A SE
M O D U LE
B
N
+
–
S IN G LE
P H A SE
M O D U LE
CS bus
Figure 3.1 Block diagram of Proposed Three-Phase Module
38
400V
DC
LINK
+
CURRENT
SENSING
RESISTOR
-
ACTIVE
LOAD
SHARING
CURRENT
CIRCUIT
CS bus
Figure 3.2 Block diagram of individual Single-Phase Module
3.2
SPECIFICATION OF THE POWER SUPPLY
An abstract of the specification of telecom power supply laid down
by Department of telecommunication is given below. Our objective is to
develop a power supply to meet all the given requirements.
Input
Output
Voltage: 320 – 480 V (400 V nominal) Voltage: -54V (-48 to -56) in float
Voltage unbalance: 10%
mode & -55.2V in charge mode
Frequency: 48-52 Hz (50 Hz nominal) Current: 100A
Power factor: better than 0.98
Voltage regulation: +/- 1%
Line current THD : <10%
Current regulation: +/-1% (in
charge mode)
Efficiency: >90%
Ripple: <300 mV P-P and 4 mV
psophometric
Transient response: +/-5%
Load sharing: within 10%
39
Climatic Tests
Cold
0o C
o
Dry heat
50o C
(-5 C
o
(55 C
Temperature
Damp
cycling
Heat
0o C and 50o C,
35o C @
4 cycles
95% RH +/-6 mm
operational) operational)
Vibration
5 to 350 Hz,
displacement or
15 m/s2 acc., 3 axes
Electromagnetic Compatibility
Conducted Emission limits
Frequency
Quasi peak limit
Average limit
(MHz)
dB
dB
0.15 – 0.5
79 dB
66 dB
0.5 – 30.0
73 dB
60 dB
Radiated Emission limits
Frequency
Distance (meters)
Quasi peak limit dB
30 – 230
10 m
40 dB
230 – 1000
10 m
47 dB
(MHz)
Conducted susceptibility limits
Voltage (Damped):
250 V to 2.5 KV, 75 nS +/-20% rise, 100 KHZ and
1 MHZ +/-10%, 2s
40
Repetition rate
:
at least 40/s for 100 KHZ and 400/s for 1MHZ
Decaying
:
50% of the peak value between 3rd & 6 th periods
Radiated radio-freq Electromagnetic field immunity limits
Freq. Range: 80 MHz to 1000 MHz
Level
Test field strength V/m
3
10
Electrostatic Discharge immunity limits: As per IEC 61000- 4-2
Electrical Fast Transient/ Burst immunity limits: As per IEC 61000-4-4.
Surge immunity limits: As per IEC 61000- 4-5
Lightening/surge 6 KV as per IEEE C62.41-1991
Radio
freq.
conducted
susceptibility
immunity
limits:
As
per
IEC 61000- 4-6.
3.3
POWER FACTOR CORRECTOR
3.3.1
Introduction
A simple boost converter used for the power factor correction
circuit is shown in Figure 3.3. The controller uses fixed frequency current
averaging, without the need for slope compensation and achieves far lower
line current distortion both in continuous and discontinuous modes. It uses a
multiplier that has a square gain function from the voltage amplifier to reduce
AC gain at light loads and thus maintains low line current distortion and high
system stability.
41
3.3.2
Circuit Description
This converter is designed to operate from 184 V to 277 V AC and
the output voltage of PFC is 400 V DC. The main components of the Boost
converter of PFC are boost inductor, MOSFET switch, blocking diode,
storage electrolytic capacitor and a controller. In the absence of gate pulse to
the MOSFET the converter draws a discontinuous current from the input
supply. It can be made continuous by applying gate pulses to the MOSFET.
During ON state of the MOSFET, current in the inductor ramps up and the
energy is stored in the inductor. During OFF state the energy stored in the
inductor is transferred to the capacitor through the diode. On both the states
current flows from the mains and hence continuous current is drawn. To make
it draw sinusoidal current, the pulse width should be modulated in accordance
with the input sinusoidal voltage waveform. To maintain the output voltage
constant, feedback from the output voltage is compared with a reference and
the difference is applied to a PI controller to generate a voltage error. This
error is squared and multiplied with the rectified input voltage. This value is
sinusoidal in shape and reflects the output voltage error and acts as current
reference for the inner current loop difference amplifier cum PI controller.
This controller gets the current feedback from a shunt resister provided on the
return path. The output of this controller is compared with a 50 KHz ramp
signal to produce the necessary PWM gate signal.
42
35A/1000V
IXYS3006A
(30A/600V)
+
RFI/
U
1M
EMI
FILTER
VIN
IRFP450X4
(14A/500V)
VOUT
18K
_
DRIVER
100PF
20K
FILP
FLOP
B
1M
1nf
U
CURRENT
ERROR
330K
+
_
R
Q
2
KA B
_
COMP
OSC
S
CURRENT
Ref
A
20K
+
_
V
Ref
VOLTAGE
ERROR
Figure 3.3 Power Factor Correction Circuit
3.3.3
Component Design and Selection
3.3.3.1
Inductor
The Inductor determines the high frequency ripple current at the
input and its value is chosen such a way that the peak ripple current ( I) is
within 20% of the peak input current.
I line =
and
P
Vin (min)
I line ( pk ) =
2P
Vin (min)
where
P - max input power and
Vin (min)
-min RMS input voltage
(3.1)
(3.2)
43
Total Output power = 5000 W
Since the power is shared between three single-phase modules,
Power per single-phase module = 5000/3=1666.66W
Assume Efficiency = 90%. (includes DC/DC Conversion Stage also)
Input power = Output power/ Efficiency
= 1666.66/ 0.9 = 1852 W
Substituting in Eqn (3.2)
2 1852W
= 14.2A
184V
I line ( pk ) =
The value of the Inductor is selected from the peak current at the
top of the half sine wave at low input voltage, the Duty factor D at that input
voltage and the switching frequency.
V
L
L V
di
dt
L
(3.3)
T
I
(3.4)
Duty Ratio D
Here
I
T
TON
T
(3.5)
T = TON and T is the period.
Therefore
T
DT
D
fS
(3.6)
Substituting (3.6) in Eqn (3.4)
L
Vin
fS
D
I
(3.7)
44
For a boost converter
1
Vin min( pk )
1 D max
VO
VO (1 D max) Vin min( pk )
VO
VO D max
VO D max
VO
VO
(3.8)
(3.9)
Vin min( pk )
(3.10)
Vin min( pk )
(3.11)
Vin min( pk )
VO
and
D max
where
VO - output DC voltage
(3.12)
Vin min( pk ) -peak input voltage at low line
f S -switching frequency
D max
L
3.3.3.2
400 261
400
0.346
261 0.346
50 10 3 (2 1.42)
636 H
Mosfet and diode
The MOSFET switch must have a current rating at least equal to
the maximum peak current of the inductor and a voltage rating at least equal
to the output voltage. The same is true for the blocking diode. Four numbers
of IRFP450 MOSFETs are used as switch. A soft recovery diode is used as
blocking diode.
45
Higher operating frequencies allow for smaller filter components
both at the output and input. This reduces cost and increases packaging
density. The fundamental limitations on the operating frequency of the CCM
boost converter are the reverse recovery current associated with the blocking
diode and the switching losses associated with the MOSFET output
capacitance. At frequencies above 100 kHz these losses become excessive.
When a normal fast recovery diode is used, at higher power levels, its
associated reverse recovery current creates high switching losses in diode as
well as in the MOSFET. This also creates radiated interference that might
affect the controller’s operation and may result in failure of the circuit.
The above problem can be overcome by either or combination of
the following.
(i)
Use of soft recovery diode.
(ii) Slow turn-on of the MOSFET.
(iii) Use of silicon carbide diode (SIC).
3.3.3.3
Output capacitor
The factors involved in the selection of the output capacitor are the
switching frequency ripple current, the second harmonic ripple current, the
DC output voltage, the output ripple voltage and the hold up time. The total
current through the output capacitor is the RMS value of the switching
frequency ripple current and the second harmonic of the line current.
CO
2 Pout
t
2
2
VO VO (min)
(3.13)
46
CO is the output capacitor, P is the load power
out
where
t is the hold up time, V is output voltage and
0
V0(min) is minimum voltage the load will operate at.
CO
3.3.4
2 (1667 / 0.95) 10 10
400 2 350 2
3
936 F
Practical Circuit Waveforms
Waveforms measured across PFC MOSFET and diode using 10:1
probe is shown in Figures 3.4-3.6. Discontinuous conduction is noticed near
zero crossing, which is responsible for distortion near zero crossing.
Figure 3.4 PFC MOSFET Drain to Source Voltage waveform
47
Figure 3.5
PFC
Diode
Anode
to
Cathode
Voltage
waveform
(Measured near Zero Crossing)
Figure 3.6 PFC Diode Anode to Cathode Voltage waveform
48
3.3.5
Simulation
Simulations of the PFC circuit has been carried out on MATLAB as
shown in Figure 3.7 and the input current waveforms with and without
squaring the voltage error are provided for comparison in Figures 3.8 to 3.11.
The current waveform of the PFC without square function has a small deadzone near zero-crossing whereas the one with the square function has a
smooth zero-crossing. Near zero-crossing of the sine voltage waveform, the
error between the voltage reference and the output voltage feedback is higher.
A square function on this error results in more conduction near zero-crossing
resulting in a smooth input current waveform.
49
50
Single-Phase PFC
w/o Filter
Single-Phase PFC
with Filter
Figure 3.8
Simulation result for PFC without Square function
(input current with and without filter)
51
Figure 3.9
Simulation result for PFC without Square function
(input voltage vs current)
52
Single-Phase PFC with Sq Fn
w/o Filter
Single-Phase PFC with Sq Fn
with Filter
Figure 3.10 Simulation
result
for
PFC
with
(input current with and without filter)
square
function
53
Figure 3.11 Simulation
result
for
PFC
with
Square
function
(input voltage vs current)
3.4
DC-DC CONVERTER
3.4.1
Introduction
This forms the second stage of the power supply and provides
isolation between input and output. It operates in variable frequency resonant
mode zero voltage switching. It converts the 400 V DC output of the PFC
section into 54 V DC.
3.4.2
Circuit Description
A half bridge converter circuit is used in ZVS configuration. When
building a zero voltage switch circuit, the objective is to wave shape the
54
power transistors voltage waveform so that the voltage across the transistor is
zero when the device is turned on, still maintaining regulation. This is
accomplished by maintaining a fixed dead time and by varying the frequency.
Thus the effective duty cycle is changed. The primary function of the
controller is to provide a fixed off-time to the gates of the power MOSFET’s.
The controller has a variable frequency oscillator, a one-shot timer, a pulse
steering flip-flop, a pair of power MOSFET drivers and a wide bandwidth
error amplifier along with peripheral support functions including a voltage
reference, under voltage lock out, soft start circuit and a fault detector as
shown in Figure 3.12. The output pulse width and repetition rate are regulated
through the interaction of the variable frequency oscillator, one-shot timer and
error amplifier. The oscillator triggers the one-shot, which generates a pulse
that is alternately steered to a pair of totem pole output drivers by a toggle
flip-flop. The error amplifier monitors the output of the converter and
modulates the frequency of the oscillator.
The half bridge topology used in this circuit clamps the switch peak
voltages to the DC input rails, reducing the switch voltage stress whereas
single ended converters operating in resonant mode zero voltage switching
have high off-state voltage. This clamping alters the duration of the off
segment of the resonant interval, since the opposite switch must be operated
long before the resonant cycle is completed. In fact, the opposite switch
should be turned on immediately after their voltage is clamped to the rails,
when their drain to source voltage equals zero. If not, the resonant tank will
continue to ring and return the switch voltage to its starting point, the opposite
rails. Additionally, this off period varies with line and load changes. The
resonant tank in this topology is not used to deliver energy to the output, as is
the case with zero current topologies. When the power transistor is enabled
the voltage across it should already be zero, yielding minimal switching loss.
55
+
MUR3020PT X2
CR/2
IFRP450 X4
1nf/1KV
10K
100E/2W
400V
DC
1nf/1KV
48V
DC
5.2K
_
CR /2
1nf/1KV
_
VARIABLE
FREQ
OSC
STEERING
FLIP
FLOP
DRIVER
DRIVER
ONE SHOT
1nf
100PF
330K
+
_
VREF
Figure 3.12 ZVS DC-DC Converter
The resonance circuit employs the primary leakage inductance of
the transformer (LL) and the average output capacitance (Coss) of the power
MOSFET switch. The resonant frequency (fr) is given by
fr
and
1
2
CR
(3.14)
LL C R
2(C OSS
(3.15)
CE )
COSS = 250picoF/mosfet x 4 = 1000picoF
CR
fr
2(1000x10
12
1000x10
1
2
40 x10 6 x 4 x10
9
12
-9
) = 4 x 10
= 398 KHz
56
Coss of the MOSFET changes with the drain voltage. Since the DC rail voltage
is fixed at 400 V DC, the value of Coss can be chosen at 400 V DC. Additional
capacitor CE is added across the drain and source of the MOSFET to achieve
the required resonant frequency. The practical circuit utilizes four IRFP450
MOSFETs in parallel in half bridge configuration. The transformer is
designed to have a leakage inductance of 40 micro Henrys. In addition to Coss
of the four parallel MOSFETs additional capacitors are used across drainsource to achieve required resonant frequency. The secondary voltage of the
transformer is rectified by two diodes in centre-tapped full wave
configuration.
3.4.3
Selection of filter components
Output filter has an inductor chosen for a current ripple of 12% and
electrolytic capacitors for voltage ripple of 100 mV. While selecting
electrolytic capacitors, equivalent series resistance (ESR) and equivalent
series inductance (ESL) should be taken into account. Normally electrolytic
capacitors are associated with ESR and ESL usually of the order of few
nano-henries. Its reactance is denoted in XL. The impedance of the capacitor Z
is given by
Z
ESR 2
(X L
X C )2
(3.16)
The impedance is dominated by capacitive reactance XC at low frequencies.
At the series resonant frequency the inductive reactance is equal to capacitive
reactance and so the impedance
Z
ESR
(3.17)
57
Above the series resonant frequency the inductive reactance overtakes the
capacitive reactance and the capacitor behaves like an inductor.
Dissipation factor (tan ) also called the loss angle tangent and
ripple current rating should also be considered while selecting electrolytic
capacitors.
Dissipation factor (tan ) is given by
ESR
XC
tan
and
X=
Therefore
tan
1
2
(3.18)
(3.19)
(3.20)
Dissipation factor increases with frequency whereas the ripple
current rating of the capacitor increases with increasing frequency. The ripple
current is limited by the internal temperature rise within the capacitor as
follows.
2
Power dissipated P = I rip
(ESR)
and P = TS
where
(3.21)
(3.22)
T is the difference between ambient temperature and capacitors
surface temperature, S is the capacitor surface (cm2) and
factor or thermal gradient (watt/cm2/deg.C).
is the dissipation
58
Therefore
I rip
TS
ESR
(3.23)
Electrolytic capacitors should be selected based on the above and at high
frequencies the ESR and ESL offers higher impedance resulting in poor
filtering. Hence multiple capacitors are recommended instead of single
capacitor.
Similarly inductors used for power supply filtering have interwinding capacitance, which allows a free path for switching frequency ripple
and noise. Hence it is complemented with a high frequency filter comprising
of an air core inductor and film foil capacitor along with electrolytic
capacitor. This filter reduces switching frequency ripple and differential-mode
noise. To suppress common-mode noise generated during switching a
common-mode filter comprising of common mode inductor and capacitors are
used.
3.4.4
Psophometric Noise
For telecom applications, it is important to limit the output noise
voltage to avoid disturbance pickup in voice channels. Power supply
manufacturers usually specify psophometric noise for telecom applications.
There are several factors that affect the noise performance of rectifiers, such
as the voltage regulation bandwidth and the impedances of installation and
battery string. The ability of the converter to fast regulate the output voltage is
an important feature that helps to limit the noise amplitude in the frequency
range of interest. In a two-stage approach, the fast output voltage regulation of
the DC/DC converter guarantees that the noise generated in the frequency
59
range of interest (100 Hz to 5 kHz) is filtered out in order to limit the
psophometric noise in the output voltage. The magnitude of the psophometric
noise can be determined according to the following relationship:
( E n wn ) 2
dB
20 log
n
24.5 * 10
6
(3.24)
where En is the RMS value of the noise voltage component
wn is the weighing factor at the component frequency fn of interest and
reference impedance.
Therefore, the contributing factors to the noise are the voltage level
of the frequency components and the weighting factor at these frequencies.
The psophometric noise weighing factor is an experimentally determined
relationship between the noise frequency and its disturbance effect on human
hearing and is shown in Figure 3.13.
As can be expected, the voltage control bandwidth of single-stage
converters plays an important role in limiting the psophometric noise.
Increasing the voltage control bandwidth certainly helps to limit the output
noise. In a two-stage approach, the voltage loop bandwidth of the DC/DC
converter can be increased as much as possible to tightly regulate the output
voltage, eliminating the problem of the psophometric noise in the output
voltage.
60
Figure 3.13 Psophometric Weighing factor
3.4.5
Practical Circuit Waveforms
Waveforms measured on various components of DC-DC converter
is shown in Figures 3.14-3.19. Current measurement is made using a CT
150:1 with a burden of 10 Ohms and 10:1 probe is used for Drain-Source/
Anode-Cathode voltage measurements and 1:1 probe for gate waveforms
measurements.
61
Figure 3.14 Transformer Primary Current @ 10%
Figure 3.15 Transformer Primary Current @ 100% Load
62
Figure 3.16 ZVS wave form @ 10% Load (Ch1-VDS, Ch2-VGS)
Figure 3.17 ZVS wave form @ 100% Load (Ch1-VDS, Ch2-VGS)
63
Figure 3.18 MOSFET Drain to Source voltage waveform
Figure 3.19 Diode Cathode to Anode voltage waveform
64
3.5
ACTIVE CURRENT SHARING
A simple, low cost and robust “active current sharing” circuit is
used. The circuit maintains good current sharing among the modules based on
the difference between the average current of the paralleled modules and the
current of the individual modules. The current feedback signals of the
individual modules are interconnected through a resistance to the Current
Share (CS) bus. This CS bus provides the average current value. This value is
compared with the individual currents using a comparator whose output alters
the voltage feedback through an RC network resulting in increase of the
output voltage to compensate the difference in current. Figure 3.20 shows two
power supplies 1 and 2 connected in parallel. RL represents the load, RS1 and
RS2 are the current sensing resistors. The voltages across R S1 and RS2 are
proportional to the current delivered by Power supply1 and 2. These voltages
are amplified by amplifiers to VS1 and VS2. The voltages VS1 and VS2 of the
individual modules are compared with the CS bus voltage VCS and the
comparator output appropriately adjusts the output voltages of the modules so
that the difference between voltages VS1, VS2 and VCS are decreased to the
desired level. The output voltages are adjusted by modifying the voltages
across capacitors C1 and C2, which effectively modifies the feedback voltage
according to the duty cycle of the comparator output voltages VCOM1 and
VCOM2.
VS1 and VS2 are proportional to the corresponding load currents and
hence,
VCS
(VS1 VS 2 ) 2
KRS ( I O1
IO2 ) 2
(3.25)
65
where
K - gain of the amplifier
RS - Current sensing resistor RS1, RS2.
i.e., it is proportional to the average of the output currents of the individual
modules. Hence the current share circuit tries to maintain the output currents
of the individual modules equal to the average current. This can be
generalized to any number of modules.
Figure 3.20 Active Current Sharing Circuit
The average capacitor voltage VC, a function of duty cycle of the
comparator output can be calculated as
VC
VR
(1 DCS )
VF
R3
R2
1
(1 DCS )
(1 DCS )
R3
R2
(3.26)
where DCS - duty cycle of the comparator output voltage
VF
- forward voltage drop of the diode.
66
Output voltage of the module is dependent on the average capacitor
voltage and can be derived as
VO
1
R5
VR
R4
R5
(VR VC )
R3
3.6
RFI/EMI SUPPRESSION
3.6.1
Introduction
(3.27)
The two major aspects Electromagnetic Interference (EMI),
otherwise referred to as Radio Frequency Interference (RFI) are Radiated and
Conducted interference
Radiated interference is normally minimized by a good layout and
wiring practices required to reduce leakage and stray inductances. Typically
the high frequency current loops have to be short, and twisted pair used
wherever possible. Transformers and chokes with air gaps have to be screened
to reduce radiated magnetic fields. Normally the heat sinks used for switching
devices are a potential source of radiated energy, as noise is coupled to the
heat sink due to the switching action of the devices. An electrically isolated
copper sheet (Faraday screen) can be used in between the switching device
and heat sink, so that the noise is coupled to the Faraday screen which can be
returned to the input circuit, while the heat sink can be grounded to reduce the
generation of RFI at source.
The two major aspects of Conducted interference are differential
mode and common mode noises. Differential mode noise exists between any
two supply or output lines whereas common mode interference exists between
any or all supply or output lines with respect to common ground plane
(chassis, box or ground wire). An input LC smoothing filter is generally
67
required in off-line switching regulators to prevent excessive noise from being
conducted from the power supplies to AC line. High power switch mode
power supplies employ a second order common mode filter and a differential
mode filter. A common mode filter is essentially two identical differential
filters, one for each of the two polarity lines with the inductor of each side
coupled by a single core. For a differential input current the net magnetic flux
coupled between the two coils is zero. When the filter encounters an identical
signal of the same polarity referred to the ground (common mode signal), the
two coils contribute a net, non-zero flux in the shared core. First order filter
has only one reactive component, an inductor (attenuation 6dB per octave)
and the second order filter has another reactive component, a capacitor added
one or greater and a cut-off frequency within about an octave of the calculated
ideal value should provide suitable filtering.
VCM OUT ( s )
VCM IN (s )
1
1 L RL s
LCs 2
(3.28)
1
2
1 LC
j ( L RL )
(3.29)
1
1
n
j2
1
n
(
n
)2
LC
(3.30)
(3.31)
L
and
2 RL LC
where RL is the noise load & = radian frequency
(3.32)
68
3.6.2
Common-Mode Noise Assessment
It is important to understand the mechanisms under which the
common-mode noise is generated and propagated through various paths. The
identification of the disturbance sources and the propagation paths are
essential steps towards understanding differential and common-mode noises
in power electronics systems. In this section, the common-mode noise
generated in the benchmarked circuit, the single-phase CCM boost rectifier is
analyzed.
3.6.2.1
Parasitic capacitance
The parasitic capacitance that connects the disturbance/noise source
to the ground constitutes the major propagation path for the common-mode
noise. The parasitic capacitance to ground depends heavily upon the circuit
layout and how the power devices are mounted in the system. The assumption
taken in this part of the analysis is that the power devices are mounted on the
heat sink, which is connected to the ground. To simplify the comparison, it is
also assumed that all switches and diodes are packaged using the TO-247
standard package. Moreover, the devices are electrically isolated with a layer
of mica. The parasitic capacitance between the base plate of the device and
the heat sink can be determined by using the following expression:
CP
where
O
O
r
A
(3.33)
d
is the permittivity of the air (8.85415 x 10-12 F / m),
r
is the relative
permittivity of the mica (4.5), A is the area of contact, and d is the thickness
of the mica layer (0.25 mm). From the data above, the equivalent capacitance
from the base plate of each device to the ground using the TO-247 package is
44 pF.
69
3.6.2.2
Noise propagation paths
The disturbance source is the voltage across the power switches.
The dv/dt of these voltages is responsible for generating common-mode
currents that flow through the parasitic capacitance. Figure 3.21 shows the
equivalent circuit of the single-phase CCM boost rectifier, including the
parasitic capacitance of the boost inductor and the parasitic capacitance from
the base plate of the MOSFET to the ground of the system. Every point
oscillating at high frequency with respect to the ground is a potential
propagation path for the common-mode noise current, which flows through
the parasitic capacitance of the power MOSFET to the ground.
Figure 3.21 Parasitic components
3.6.3
Filter Design
The procedure for designing a common mode filter is
Identify the required cut-off frequency: Suppose if the SMPS
is 24dB noisier at 60 KHz than the permissible vaue, for the
70
second order filter (12dB per octave) the desired corner
frequency would be 15 KHz.
Identify the load resistance at the cut-off frequency:
Assume RL = 50 ohms
Choose the desired damping factor: Choose a minimum of
0.707, which will provide 3dB attenuation at the corner
frequency while providing favorable control over filter
ringing.
Calculate the required component values:
n
2 fn
94248 rad / sec
0 .707
L
L
750 H
C
1 L
2
n
n
2RL
0 .15 F
Similarly a second order differential mode filter can be designed
using L&C. This along with common mode filter forms an effective filter for
conducted noise as shown in Figure 3.22. Metal-oxide varistors are used in
combination with the filter to provide surge suppression for protection against
lightning. Maximum discharge surge current for these device is 6.5 kA.
L1
P
L2
C4
V1
C1
C2
V3
G
V2
C3
C5
N
Figure 3.22 RFI-EMI Filter
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3.6.4
Effect of Lightning and Protection
Lightning is one of the major causes of failure in Telecom power
supplies. Transient surge voltages arise as a result of lightning discharge.
Metal-oxide varistors (MOV) used in the above RFI/EMI filter may not be
sufficient to protect the power supply from lightning in many installations.
Without proper protective measures, even the sturdily built low voltage power
supply fail as the power involved in lightning discharge is very high. The
surge voltages occur only for a small period in the range of a millionth of a
second but are capable of destroying electronic circuits or the insulation
between tracks in the printed circuit boards.
The coupling of surge voltages from one system to another can be
galvanic, inductive or capacitive. The measures required to protect the power
supply systems are divided into two or three stages depending on the arresters
chosen and the environmental influences to be expected. Figure 3.23 shows a
typical two stage protection for power supply application in TT configuration.
The first protection stage (CLASS I) is a Lightning Current Arrester (LCA)
with arc chopping spark gap installed directly after the main distribution panel
as the most powerful protective device limiting surge voltages to
spark gap is capable of reliably quenching the arc after every lightning strike
to limit the follow-through currents and reduces the load on the fuses. The
second stage of protection (CLASS II) is the Surge Voltage Arrester (SVA)
provided close to the power supply unit, which normally consists of a high
capacity varistor with thermal disconnect device, producing surge currents as
high as 40
10 m conductor length is necessary between the two stages. In installations
where both are mounted together a decoupling inductor becomes necessary
for commutation between LCA and SVA. During the arresting process, the
72
discharge current flowing through the SVA and the inductance causes a
voltage drop. The sum of all the voltages over the SVA and the inductance
equals the response voltage of the LCA. The third level of protection is built
into the power supply itself by MOV’s which finally limits surges to an
acceptable level of 700 V.
CLASS I
CLASS II
T
o
L1
L2
P
o
w
e
r
L3
N
S
u
p
p
l
y
PE
Figure 3.23 Lightning protection
3.6.5
Photographic View of the SMR
Photographs of the SMR are shown below. Figure 3.24 is the top
view of the SMR. The top section accommodates two similar printed circuit
assemblies (PCA), one for each phase. The third PCA is located in the bottom
section as shown in the bottom view photograph Figure 3.25. Each PCA is
capable of delivering 33.33 A at 54 V. The bottom section also holds a RFI
filter PCA and an auxiliary power supply for powering the main PCA’s, in
addition to the transformers for voltage sensing. Monitoring circuit could be
seen mounted on one side of the SMR. Figure 3.26 is the front view and
circuit breakers, fuse and fans for forced cooling could be seen in Figure 3.27,
the back view. Figure 3.28 shows a 19” rack holding four 100 A SMR
modules working in parallel providing 400 A output.
73
..
Figure 3.24 Top View of the SMR module
Figure 3.25 Bottom View of the SMR module
74
Figure 3.26 Front View of the SMR module
Figure 3.27 Back View of the SMR module
75
Figure 3.28 Parallel operation (Four modules in a 19” Rack)