A Σ∆ Fractional-N Closed-Loop Modulator
for DECT
Dan D.S. Hermansen1,2 , Emil F. Buskgaard1,2 , Poul Olesen1 , Finn Andreasen1 , and Torben Larsen2
RTX Telecom1 and RISC division2 , Center for TeleInFrastructure (CTIF), Aalborg University, Denmark
E-mail: {ddh,efb,pol,fa}@rtx.dk, tl@kom.aau.dk
Abstract
Traditionally, modulators for DECT are implemented using
open-loop modulation. However, open-loop modulators are
too slow for 100% slot utilization. This causes the well
known DECT blind-slot problem. One solution to this is to
employ closed-loop modulation in stead. This paper presents
a closed-loop modulator solution for DECT. The modulator is based on a combination of Σ∆-techniques and use of
a fractional-N PLL. The technique allows for digital phase
and frequency modulation without use of mixers or D/A converters in the modulation path. Simulation results show a
working modulator that is superior to state-of-the-art DECT
transmitters using open-loop modulation. An internal reference frequency of 10 − 30 MHz gives an output PSD that
meets DECT specification requirements on unwanted emissions due to modulation. The RMS phase error for a reference frequency of 31.104 MHz is as low as 1.06◦ and the
peak phase error is 2.90◦ . The blind-slot problem is solved
using the closed-loop modulator as the lock time is 1 − 3 µs
which, compared to the guard space requirements of below
50 µs, gives a large room for implementation imperfections.
1. Introduction
The Digital Enhanced Cordless Telecommunications (DECT)
system is an open standard for cordless telecommunications
in private homes and office environments [1]. From an RF
perspective the key specifications for DECT are as listed in
Table 1.
Table 1: Key DECT parameters.
Modulation
GMSK
Data rate
1152
[kbps]
Frequency band
1880–1900 [MHz]
Bandwidth
1.152
[MHz]
No. of channels
10
Access scheme
TDMA
Channel spacing
1.728
[MHz]
Nominal TX Power (NTP)
24
[dBm]
For DECT, the bill of materials (BoM) is a paramount business parameter. To remain competitive industry is therefore
continuously trying to decrease their BoM. For the RF part,
modulators have traditionally been implemented using openloop modulation, as illustrated in Figure 1, as a means to
reduce component cost. However, due to design tradeoffs
related to the division ratios, open-loop modulators are generally too slow for 100% slot utilization.
Input
data
f ref
:R
PD
Gaussian
filter
Loop
filter
f rf
:N
Figure 1: Traditional open-loop modulator.
To solve this, every second slot is skipped to allow for the
slow PLL to settle. This causes the well known blind-slot
problem experienced in DECT. For use in private homes the
blind-slot issue poses no practical limitation but for use in
larger office environments it is a problem. One solution
to this is to employ closed-loop modulation. This paper
presents a closed-loop modulator solution that combines the
use of Σ∆ techniques with the use of a fractional-N PLL.
The modulator topology, illustrated in Figure 2, is based on
a fractional-N PLL where the divider ratio is controlled by
the output from a Σ∆-modulator [2].
f ref
PD
Loop
filter
f rf
8-bit
divider
Input
data
N
Gaussian
filter
SD
modulator
Figure 2: The architectural structure of the closed-loop Σ∆
Fractional-N modulator [2].
In traditional fractional-N based modulators the data directly
controls the division ratio. This results in periodicy in the
dithering pattern which produces spurious outputs as well
as low frequency phase noise. Through the use of a Σ∆modulator this periodicy is mitigated and the resulting noise
performance is improved [2].
For DECT there is no requirement on phase error but if a
comparison to GSM is made an RMS phase error below 5◦
is required. The aim of most GSM designers is values below
2◦ to reach competitive performance levels. Based on these
numbers the design aim for the presented modulator is an
RMS phase error below 3◦ and a peak phase error below
10◦ .
2. Modulator Functionality
The input data to the modulator is a ±1 bit stream with
a bit rate of 1152 kbps. To increase resolution this input
data stream needs to be oversampled. Since the phase detector reference signal already is available this is used as
sampling frequency as Figure 2 illustrates. This means that
for a 20.763 MHz reference frequency each bit consists of
18 samples. In a practical implementation it is preferable
to have the reference frequency as low as possible as this
lowers the calculation requirements in the digital components. This lowers the power consumption and allows for
cheaper implementations. After oversampling the bit sequence passes through a filter with a Gaussian shaped impulse response. The filter shapes each bit and introduces
controlled inter-symbol interference. The resulting samples
are represented as floating-point numbers between -1 and 1.
The divider is chosen as the input to the loop for the modulated bit stream. For this to work the modulated signal needs
to be adapted. For the modulator to reach the wanted RF
channel and the nominal peak frequency deviation of 288
kHz the modulated signal is offset-scaled. If the modulator
is to transmit on channel 9 (1880 MHz) the average input
to the Σ∆-modulator needs to be 1880 MHz divided by the
reference frequency. For a 20.736 MHz reference frequency
this equals 90.664 [-]. The peak deviation is ±1 at the output of the shaping filter. This span also needs to be scaled
to a frequency deviation of ±288 kHz. Again, for a 20.736
MHz reference frequency the output of the filter has to be
scaled to 288 kHz divided by 20.736 MHz which equals
±0.00139 [-]. The divider can only divide by integer values
and the floating point division values therefore needs to be
converted to integers. This conversion introduces noise but
by using a Σ∆-modulator as converter the resulting noise
is shaped. By this relocation to higher frequencies the Σ∆modulation enables the loop filter to attenuate the conversion
noise. Furthermore, due to the randomness of the output signal the Σ∆-modulation removes the fractional spurs seen in
traditional fractional-N synthesis. Inside the loop the PLL is
assumed to be in lock and stable. This idea of modulating the
signal inside the loop by altering the division ratios according to the bit sequence is the key point of the architecture in
Figure 2.
The divider counts the number of clock cycles from the VCO
and sends an output pulse when the count reaches the division ratio. At the same time the divider picks a new division ratio from the Σ∆-modulator for the next up count.
This way the output phase of the divider is a ‘division rate’
times slower than the VCO output phase. The phase detector (PD) output is a measure of the phase difference (or
phase error) between the divider output phase and the reference clock phase. Due to the digital nature of the modulator
topology the phase error changes in steps. The PD output
is subsequently lowpass filtered in the loop filter to attenuate all but the corresponding slowly varying DC-value. For
the topology in Figure 2 to function the modulation has to
pass through the loop and a certain minimum bandwidth is
obviously required. This forms a trade-off between attenuating loop noise and creating sufficient modulation bandwidth.
The LF signal at the output of the loop filter is used to control the VCO. The VCO has a free running center frequency
from which it can deviate up or down according to its positive input DC value. So when a phase error is detected the
DC value changes and the VCO reacts by increasing or decreasing the output frequency. The phase information from
the VCO is looped back to the divider.
3. Simulation Method and Environment
To verify and analyze the performance of the modulator a
number of simulations are conducted using M ATLAB . To
be able to include non-ideal effects in the different system
blocks a modular structure strictly following the block diagram of Figure 2 is chosen. Implementing a basic linear
VCO model is straight-forward but the model is also fairly
inaccurate. To increase the accuracy of the simulation results the VCO model is refined based on measurements of
VCO I/O linearity. The divider is implemented as a simple
counter while the Σ∆-modulator is implemented as a 4th order MASH-type converter [3]. The Σ∆-modulator converts
the floating-point division ratios from the shaping filter to 8bit integers. The implemented PD model is based on a phase
frequency detector (PFD) [3]. Unlike a basic phase detector the PFD can not only lock onto the phase of a signal but
also the frequency. The loop filter is modeled by a standard
M ATLAB generated Butterworth filter with adjustable order
and bandwidth.
The simulation sampling rate is 10 to 15 times the reference frequency. To avoid loss of high frequency information
in the PFD the principle of area conservation is used [4].
Further, to make the process of simulating the modulator as
easy as possible a simulation tool is developed. The simulation tool contains an interface for altering reference frequency, loop filter order and bandwidth, loop gain and many
other system parameters. Furthermore, simulation parameters such as sample rate and time duration of the simulation
can be set. An evaluation tool is also included. This allows
for a noise performance analysis using the PSD of the signal.
It is also possible to analyze the phase error and to inspect
the curve shape of the time, phase and frequency representations of both input and output signals. All of these signals
are presented as graphs and RMS and peak phase error are
written in numbers as well.
4. Results
Based on the developed simulation environment and set-up
a number of simulations are conducted. To evaluate the
performance of the modulator two key parameters are considered. These performance metrics are the resulting RMS
phase error and the adjacent-channel emission spectra. The
simulations have been conducted using all possible combinations of reference frequency (10.368 MHz, 20.736 MHz,
31.104 MHz), loop filter cut-off frequency (1000 kHz, 1200
kHz, 1600 kHz), and loop filter order (2nd , 3rd , 4th ). To
evaluate the modulators performance over the entire DECT
bandwidth the simulations are repeated for each channel.
Figures 3 to 5 show the average RMS phase noise performance for all channels while Figures 6 to 8 show the worstcase emission performance for all channels.
meet the phase noise design target with the best performance
resulting from a third-order filter with a cut-off frequency of
1600 kHz.
10
1000 kHz
1200 kHz
1600 kHz
9
13
12
11
RMS phase error [deg]
RMS phase error [deg]
8
1000 kHz
1200 kHz
1600 kHz
10
9
6
5
4
8
3
7
2
6
1
5
4
2
3
Loop filter order [−]
4
Figure 3: Mean phase error versus filter order for various
filter bandwidths for a reference frequency of 10.368 MHz.
From Figure 3 it is found that the combination of a low filter order and a high cut-off frequency results in the worst
noise performance. Increasing the filter order improves on
the noise performance in all cases but for the lowest cut-off
frequency. In all cases the phase noise performance fails to
meet the target value below 3◦ . This result indicates that a
reference frequency of 10.368 MHz does not provide sufficient room for noise shaping of the dither signal.
7
1000 kHz
1200 kHz
1600 kHz
6
RMS phase error [deg]
7
5
4
3
2
1
2
3
Loop filter order [−]
4
Figure 4: Mean phase error versus filter order for various
filter bandwidths for a reference frequency of 20.736 MHz.
Comparing Figures 3 and 4 it appears that the tendency from
Figure 3 is reversed for a 20.736 MHz reference frequency.
Here the best noise performance is achieved for low filter
orders. This indicates that the noise shaping is better and
that signal degradation results from loop filter group-delay
distortion. The increased noise level for the second-order,
1600 kHz cut-off filter shows that the noise from the Σ∆modulator still has some impact. Six of the combinations
2
3
Loop filter order [−]
4
Figure 5: Mean phase error versus filter order for various
filter bandwidths for a reference frequency of 31.104 MHz.
For a 31.104 MHz reference frequency the noise from the
Σ∆-modulator is insignificant as Figure 5 illustrates. In this
case the group-delay distortion from the loop filter is the
most significant source to signal degradation. The tendency
is clearly that an increased filter order and a reduced cut-off
frequency degrades phase noise performance of the modulator. From Figures 3 to 5 it is found that there exists a tradeoff between the reference frequency and the sharpness of the
loop filter. At a low reference frequency the noise from the
Σ∆-modulator is dominant and sharp filtering increases performance. At higher reference frequencies the noise from
the Σ∆-modulator becomes less significant and loop filter
group-delay effects become more important. At the highest
reference frequency group-delay is dominant and relaxed filtering provides for best performance in this case.
The last performance parameter to evaluate is the adjacentchannel emission. When this performance metric is considered the performance of the modulator is found to depend
slightly on the RF channel setting. To simplify result-graphs
only worst-case performance is presented. For the low reference frequency the emission results are presented in Figure 6
together with the emission envelope requirement. From this
it is clearly seen that for a second-order loop filter the modulator is not able to comply with emission requirements. The
third-order filter also fails for a cut-off frequency of 1600
kHz.
With the reference frequency increased to 20.736 MHz, as
illustrated in Figure 7, the emission performance is seen to
increase for almost all filter combinations. Only a single
combination, the second-order 1600 kHz cut-off filter, fails
to meet requirements. For the second-order, 1200 kHz cutoff filter the performance surplus is very small and there is
almost no room for implementation margin. When the reference frequency is increased to 31.104 MHz only the secondorder, 1600 kHz cut-off filter fails to meet requirements with
sufficient margin. For all remaining combinations more than
10dB of margin is achieved.
40
Adjacent channel emmisions [dBm]
20
0
−20
−40
40
Adjacent channel emmisions [dBm]
1000 kHz, 2nd order
1200 kHz, 2nd order
1600 kHz, 2nd order
1000 kHz, 3rd order
1200 kHz, 3rd order
1600 kHz, 3rd order
1000 kHz, 4th order
1200 kHz, 4th order
1600 kHz, 4th order
20
0
−20
−40
−60
−60
−80
−80
1
It is clear that the best emission performance is achieved for
high-order filters with a low cut-off frequency. Since the
loop filter effectively serves as an output filter for the RF
channel this result comes as no surprise.
40
1000 kHz, 2nd order
1200 kHz, 2nd order
1600 kHz, 2nd order
1000 kHz, 3rd order
1200 kHz, 3rd order
1600 kHz, 3rd order
1000 kHz, 4th order
1200 kHz, 4th order
1600 kHz, 4th order
20
0
1
2
3
4
Adjacent channel number [−]
Figure 6: Worst-case emission levels for a 10.368 MHz reference frequency. NTP is 24 dBm, channel bandwidth is
1.152 MHz, and channel spacing is 1.728 MHz.
Adjacent channel emmisions [dBm]
1000 kHz, 2nd order
1200 kHz, 2nd order
1600 kHz, 2nd order
1000 kHz, 3rd order
1200 kHz, 3rd order
1600 kHz, 3rd order
1000 kHz, 4th order
1200 kHz, 4th order
1600 kHz, 4th order
−20
2
3
4
Adjacent channel number [−]
Figure 8: Worst-case emission levels for a 31.104 MHz reference frequency. NTP is 24 dBm, channel bandwidth is
1.152 MHz, and channel spacing is 1.728 MHz.
frequency of 31.104 MHz. However, for cost and power
consumption reasons a low sampling frequency is wanted.
Unfortunately, at low sampling frequencies the conversion
noise from the Σ∆-modulator becomes significant and phase
noise performance is degrade. Furthermore, at the lower reference frequencies the Σ∆ noise shaping is insufficient and
adjacent-channel emission performance is also degrade. A
third-order loop filter with a 1600 kHz bandwidth operated
in conjunction with a 20.736 MHz reference frequency is
found to be a suitable tradeoff. The best channel RMS phase
error for this combination is 1.60◦ and a peak phase error
of 4.62◦. For this set-up the lowest margin on the emission
due to modulation is 8 dB which leaves sufficient room for
implementation margin. With lock-times of around 1 − 3 µs
the modulator topology is found to be well suited for implementing DECT transmitters.
−40
6. References
−60
−80
1
2
3
4
Adjacent channel number [−]
[1] ETSI, Digital Enhanced Cordless Telecommunications
(DECT); Common Interface (CI); Part 2: Physical
Layer (PHL), ch. 4-6.
ETSI, etsi en 300 175-2
v1.7.1 ed., 2003-07.
Figure 7: Worst-case emission levels for a 20.736 MHz reference frequency. NTP is 24 dBm, channel bandwidth is
1.152 MHz, and channel spacing is 1.728 MHz.
[2] M. H. Perrott, Techniques for High Data Rate Modulation and Low Power Operation of Fractional-N Frequency Synthesizers, ch. 2,8,9,11. Massachusetts Institute of Technology, 1997-09.
5. Conclusions
[3] M. Kozak, Oversampled delta-sigma modulators : analysis, applications, and novel topologies, ch. 2,3,5.
Boston, Massachusets : Kluwer Academic Publishers,
2003.
A closed-loop modulator based on Σ∆ noise shaping is presented. Based on simulations it is found that a large loop
filter bandwidth and a low filter order results in low phase
error. Further, it is found that a low bandwidth and a high order reduces spurious emissions. The best phase noise performance, 1.06◦ RMS and 2.9◦ peak, is obtained for a reference
[4] M. H. Perrott, Fast and Accurate Behavioral Simulation of Fractional-N Frequency Synthesizers and other
PLL/DLL Circuits. MIT/DAC, 2002-06.