Logic Circuits II
Physics116B, rev. 2/28/11
D. Pellett
Outline
•
•
Emitter-Coupled Logic (ECL) example from Bobrow, Ch. 7
Logic family comparisons
•
•
•
Interconnections, “dos and don’ts”
More recent developments
Transmission Lines and Fast Logic Including ECL
•
•
•
•
•
Short pulses and transmission lines - quick overview
High bandwidth Oscilloscope Probes
Using ECL to drive transmission lines
High bandwidth oscilloscope probes
ECL and Nuclear Instrumentation Module (NIM) logic
Emitter Coupled Logic (ECL)
•
ECL circuits are fast (1 ns delays typical) because they avoid
saturation
•
•
Can drive low impedance loads such as 50 Ω coaxial cables
•
Because BJTs remain in active region, power dissipation
significantly higher than TTL, low packing density on chip
•
Circuit based on differential amplifier with non-inverting input
connected to reference voltage, one BJT cut off and the other
in active region
•
•
Supply voltage and logic levels typically <0.
May have complimentary outputs to drive pairs of lines
differentially (strip lines, twisted pairs, etc.)
Emitter follower outputs
•
May have “open emitter” output
Basic ECL Inverter Concept
Differential Amplifier
(Vref)
Inverting
Input
Non-Inverting
Input
(VEE)
•
Design so Q1 active, Q2 off when Vin high,
•
•
opposite w/ Vin low
Determine logic levels next
NOTE: Circuit based on
Fig. 7.43 in Bobrow
Commercial circuits differ in
Vref,VEE and BJT VBE(active)
so actual ECL levels are
different.
Find Output V in High State
≈ 0V
Off
Low
< -1.2 V
(VB1 < VE + 0.5 V)
•
Active
High -0.7 V
-1.7 V
Assume Vin low so Q1 off and Q2 in active region
•
•
VBE2 = 0.7 V so VE = -1.7 V
•
Voltage drop across R1 is negligible: IE3 = (5-0.7)V/1.2 kΩ
= 3.6 mA → IB3 ≈ 36 µA, IB3 R1 = 10 mV.
Since Q1 off, VC1 ≈ 0 V, so V0 = -0.7 V (high logic state).
Note Q3 is in active region with VBE3 = 0.7 V and VC = 0 V:
VCE3 = 0.7 V (> 0.2 V)
Find Low State Output Voltage
-0.82 V
Active Off
Low -1.52 V
High -0.7 V
-1.4 V
•
Assume Vin high and Q1 in active region
•
•
•
VBE1 = 0.7 V so VE = -1.4 V. → VBE2 = 0.4 V so Q2 off
IE = IE1 = (-1.4 -(-5))V/1.2 kΩ = 3.0 mA
VC1 = VB3 ≈ -(3.0 mA)(275 Ω) = -0.82 V → VO = -1.52 V
(low state output voltage, < -1.2 so low OK at input)
Make into OR/NOR
•
Adding Q0 in parallel with Q1 produces a NOR function at Q3
emitter.
•
Adding an emitter follower connected to collector of Q2
produces the complement of the function, an OR.
Symbol
IE
Characteristic
Power Supply Current
Min
Max
Min
Max
Min
Max
Unit
–
29
–
26
–
29
mA
µA
IinH
IinL
Input Current High
–
425
–
265
–
265
Input Current Low
0.5
–
0.5
–
0.3
–
µA
VOH
VOL
High Output Voltage
–1.02
–0.84
–0.98
–0.81
–0.92
–0.735
Vdc
Low Output Voltage
–1.95
–1.63
–1.95
–1.63
–1.95
–1.60
Vdc
VIH
VIL
High Input Voltage
–1.17
–0.84
–1.13
–0.81
–1.07
–0.735
Vdc
Low Input Voltage
–1.95
–1.48
–1.95
–1.48
–1.95
–1.45
Vdc
Propagation Delay
0.4
1.25
0.4
1.25
0.4
1.4
ns
Rise Time
0.5
1.5
0.5
1.6
0.55
1.7
ns
Actual MECL 10K ECL OR/NOR
AC PARAMETERS
tpd
tr
tf
Fall Time
0.5
1.5
0.5
1.6
0.55
1.7
ns
1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm is
maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.
From MECL Handbook, 4th ed.
•
! SCILLC, 2000
http://onsemi.com
Previous
Edition !1980, 1988
2 Reserved”
“All Right
Date of this Printing: Aug–2000
BJT VBE = 0.8 - 0.9 V for active region,VBB = -1.35 V, VEE = -5.2 V
•
•
Logic levels are -0.9 V and -1.75 V (nominal)
Note open emitter outputs
Quad 2-Input NOR
The MC10H102 is a quad 2–input NOR gate. The MC10H102
provides one gate with OR/NOR outputs. This MECL 10H part is a
functional/pinout duplication of the standard MECL 10K family part,
with 100% improvement in propagation delay, and no increases in
power– supply current.
• Propagation Delay, 1.0 ns Typical
• Power Dissipation 25 mW/Gate (same as MECL 10K)
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
DIP
PIN ASSIGNMENT
6
10
CDIP–16
L SUFFIX
CASE 620
12
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
PDIP–16
P SUFFIX
CASE 648
1
16
BOUT
3
14
AIN
4
13
AIN
5
12
BIN
6
11
7
10
8
9
MC10H102L
BIN
AWLYYWW
VEE
MC10H102P
AWLYYWW
Pin assignment is for Dual–in–Li
1 pin assignment, see the Pin Conve
For PLCC
1
of the ON
Semiconductor MECL Data
PLCC–20
FN SUFFIX
CASE 775
A
WL
YY
WW
DIP
PIN ASSIGNMENT
VCC1
15
16
15
9
13
2
1
14
11
AOUT
16
3
7
16
MARKING
DIAGRAMS
2
5
1
http://onsemi.com
LOGIC DIAGRAM
4
VCC1
10H102
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
! Semiconductor Components Industries, LLC, 2000
March,
2000
– Rev. 6
ORDERING
INFORMATION
VCC2
Device
Package
Shipping
10
11
MECL NOR Specifications
12
13
MC10H102
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
MAXIMUM RATINGS
Symbol
Characteristic
Rating
Unit
VEE
VI
Power Supply (VCC = 0)
–8.0 to 0
Vdc
Input Voltage (VCC = 0)
0 to VEE
Vdc
Iout
Output Current – Continuous
– Surge
50
100
mA
TA
Tstg
Operating Temperature Range
Storage Temperature Range – Plastic
– Ceramic
0 to +75
V°C
CC1
1
16
V
–55 to +150
–55 to +165
A°C
OUT
2
15
D
BOUT
3
14
C
AIN
4
13
D
AIN
5
12
D
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)
0°
Symbol
25°
75°
Min
Max
Min
Max
Min
Max
Unit
Power Supply Current
–
29
–
26
–
29
mA
IinH
IinL
Input Current High
–
425
–
265
–
265
BIN
µA
6
11
C
Input Current Low
0.5
–
0.5
–
0.3
–
µA
B
7
10
C
VOH
VOL
High Output Voltage
–1.02
–0.84
–0.98
–0.81
–0.92
–0.735
IN
Vdc
Low Output Voltage
–1.95
–1.63
–1.95
–1.63
–1.95
–1.60
EE
Vdc
8
9
D
VIH
VIL
High Input Voltage
–1.17
–0.84
–1.13
–0.81
–1.07
–0.735
Vdc
Low Input Voltage
–1.95
–1.48
–1.95
–1.48
–1.95
Propagation Delay
0.4
1.25
0.4
1.25
0.4
–1.45
Vdcassignment is for Dual–in–Line
Pin
For PLCC pin assignment, see the Pin Convers
of the ON Semiconductor MECL Data B
1.4
ns
Rise Time
0.5
1.5
0.5
1.6
0.55
IE
Characteristic
DIP
PIN ASSIGNMENT
AC PARAMETERS
tpd
tr
1.7
V
ns
tf
Fall Time
0.5
1.5
0.5
1.6
0.55
1.7
ns
1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm is
maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.
! Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 6
Logic Family Comparisons
•
See Tables 12.5 and 12.6 in Bobrow, Tables 9.1 and 9.2 in
Horowitz and Hill
•
Important families: TTL, STTL, LSTTL, CMOS, HC, HCT, ECL
•
•
Important parameters: pulse delay, power per gate, logic
level ranges, supply voltages, fanout
•
Incompatibilities of CMOS and HC with TTL high output
See also later slides from the Texas Instruments Logic
Selection Guide (2005)
Logic Family Comparisons
•
The slide shown in class is available on SmartSite
Some Precautions
•
•
TTL –
•
Inputs normally float “high” but if you desire high state
connect to VCC for noise immunity
•
Bypass VCC to ground frequently near or at the chips with
0.01 µF – 0.1 µF capacitors to prevent glitches due to
switching spikes on the supply lines.
CMOS –
•
Note that TTL outputs are not high enough for normal
CMOS inputs in high state – can remedy with pull-up
resistor to VCC.
•
Connect all CMOS inputs to definite logic levels.
Otherwise input can float to a voltage where pMOS and
nMOS FETs are conducting leading to short between VSS
and VDD.
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Pulses and Transmission Lines
Transmission Line Circuit Model
(Ideal, lossless)
Typical Characteristic Impedance Values
Other Transmission Line Advantages
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)
0°
Symbol
Characteristic
Min
25°
Max
Min
Lots of Useful Information on Fast Pulse
Techniques in MECL Handbook
75°
Max
Min
Max
IE
IinH
IinL
Power Supply Current
–
29
–
26
–
29
Input Current High
–
425
–
265
–
265
0.5
–
0.5
–
0.3
–
VOH
VOL
High Output Voltage
–1.02
–0.84
–0.98
–0.81
–0.92
–0.735
Low Output Voltage
–1.95
–1.63
–1.95
–1.63
–1.95
–1.60
VIH
VIL
High Input Voltage
–1.17
–0.84
–1.13
–0.81
–1.07
–0.735
Low Input Voltage
–1.95
–1.48
–1.95
–1.48
–1.95
–1.45
Propagation Delay
0.4
1.25
0.4
1.25
0.4
1.4
Rise Time
0.5
1.5
0.5
1.6
0.55
1.7
Input Current Low
AC PARAMETERS
tpd
tr
tf
Fall Time
0.5
1.5
0.5
1.6
0.55
1.7
1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilib
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500
maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.
From MECL Handbook, 4th ed.
! SCILLC, 2000
http://onsemi.com
Previous
Edition !1980, 1988
2 Reserved”
“All Right
Date of this Printing: Aug–2000
•
Web link to download MECL Handbook (pdf):
http://www.onsemi.com/pub/Collateral/HB205-D.PDF
MAXIMUM RATINGS
Symbol
Rating
Unit
VEE
VI
Power Supply (VCC = 0)
Characteristic
–8.0 to 0
Vdc
Input Voltage (VCC = 0)
0 to VEE
Vdc
Iout
Output Current – Continuous
– Surge
TA
Tstg
Operating Temperature Range
Pulse Response on “Open Wire”
Storage Temperature Range – Plastic
– Ceramic
50
100
mA
0 to +75
°C
–55 to +150
–55 to +165
°C
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)
0°
Symbol
75°
Min
Max
Min
Max
Min
Max
Unit
Power Supply Current
–
29
–
26
–
29
mA
IinH
IinL
Input Current High
–
425
–
265
–
265
µA
Input Current Low
0.5
–
0.5
–
0.3
–
µA
VOH
VOL
High Output Voltage
–1.02
–0.84
–0.98
–0.81
–0.92
–0.735
Vdc
Low Output Voltage
–1.95
–1.63
–1.95
–1.63
–1.95
–1.60
Vdc
VIH
VIL
High Input Voltage
–1.17
–0.84
–1.13
–0.81
–1.07
–0.735
Vdc
Low Input Voltage
–1.95
–1.48
–1.95
–1.48
–1.95
–1.45
Vdc
Propagation Delay
0.4
1.25
0.4
1.25
0.4
1.4
ns
Rise Time
0.5
1.5
0.5
1.6
0.55
1.7
ns
IE
Characteristic
25°
AC PARAMETERS
tpd
tr
MECL System
Design Handbook
Fourth Edition
Author: William R. Blood, Jr.
tf
Fall Time
0.5
1.5
0.5
1.6
0.55
1.7
ns
1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm is
maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.
HB205/D
Rev. 1A, May–1988
From MECL Handbook, 4th ed.
! SCILLC, 2000
http://onsemi.com
Previous
Edition !1980, 1988
2
“All Right Reserved”
Date of this Printing: Aug–2000
MAXIMUM RATINGS
Symbol
Characteristic
VEE
VI
Power Supply (VCC = 0)
Iout
Output Current – Continuous
– Surge
TA
Tstg
Operating Temperature Range
Rating
Unit
–8.0 to 0
Vdc
ECL Driving 50 Ω Coaxial Cable
Input Voltage (VCC = 0)
Storage Temperature Range – Plastic
– Ceramic
0 to VEE
Vdc
50
100
mA
0 to +75
°C
–55 to +150
–55 to +165
°C
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)
0°
Symbol
Characteristic
Min
25°
Max
Min
75°
Max
Min
Max
Unit
IE
IinH
IinL
Power Supply Current
–
29
–
26
–
29
mA
Input Current High
–
425
–
265
–
265
µA
Input Current Low
0.5
–
0.5
–
0.3
–
µA
VOH
VOL
High Output Voltage
–1.02
–0.84
–0.98
–0.81
–0.92
–0.735
Vdc
Low Output Voltage
–1.95
–1.63
–1.95
–1.63
–1.95
–1.60
Vdc
VIH
VIL
High Input Voltage
–1.17
–0.84
–1.13
–0.81
–1.07
–0.735
Vdc
Low Input Voltage
–1.95
–1.48
–1.95
–1.48
–1.95
–1.45
Vdc
Propagation Delay
0.4
1.25
0.4
1.25
0.4
1.4
ns
Rise Time
0.5
1.5
0.5
1.6
0.55
1.7
ns
AC PARAMETERS
tpd
tr
tf
Fall Time
0.5
1.5
0.5
1.6
0.55
1.7
ns
1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm is
maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.
From MECL Handbook, 4th ed.
! SCILLC, 2000
http://onsemi.com
Previous
Edition !1980, 1988
2 Reserved”
“All Right
Date of this Printing: Aug–2000
Much
Better!
Des
MC10H102
MAXIMUM RATINGS
Symbol
Rating
Unit
VEE
VI
Power Supply (VCC = 0)
Characteristic
–8.0 to 0
Vdc
Input Voltage (VCC = 0)
0 to VEE
Vdc
Iout
Output Current – Continuous
– Surge
50
100
mA
TA
Tstg
Operating Temperature Range
0 to +75
°C
–55 to +150
–55 to +165
°C
°C
ECL Differential Line Driver and Receiver
Storage Temperature Range – Plastic
– Ceramic
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)
0°
Symbol
75°
Min
Max
Min
Max
Min
Max
Unit
Power Supply Current
–
29
–
26
–
29
mA
IinH
IinL
Input Current High
–
425
–
265
–
265
µA
0.5
–
0.5
–
0.3
–
µA
VOH
VOL
High Output Voltage
–1.02
–0.84
–0.98
–0.81
–0.92
–0.735
Vdc
Low Output Voltage
–1.95
–1.63
–1.95
–1.63
–1.95
–1.60
Vdc
VIH
VIL
High Input Voltage
–1.17
–0.84
–1.13
–0.81
–1.07
–0.735
Vdc
Low Input Voltage
–1.95
–1.48
–1.95
–1.48
–1.95
–1.45
Vdc
Propagation Delay
0.4
1.25
0.4
1.25
0.4
1.4
ns
Rise Time
0.5
1.5
0.5
1.6
0.55
1.7
ns
IE
Characteristic
25°
Input Current Low
AC PARAMETERS
tpd
tr
tf
Fall Time
0.5
1.5
0.5
1.6
0.55
1.7
ns
1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has be
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm
maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.
From MECL Handbook, 4th ed.
! SCILLC, 2000
http://onsemi.com
Previous
Edition !1980, 1988
2
“All Right Reserved”
Date of this Printing: Aug–2000
IL
IOS§
ICCH
CC
VCC = MAX
I
−40
−100
−40
−100
Oscilloscope Probes for Fast Signals in Action
ICCL
Leading edge trigger circuit
from Lab 13
VCC = MAX,
VCC = MAX,
VI = 0 V
VI = 4.5 V
mA
15
24
15
24
mA
30
54
30
54
mA
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
74LS04 Hex Inverter
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
RL = 280 Ω,
CL = 15 pF
tPLH
tPHL
A
Y
RL = 280 Ω,
CL = 50 pF
PARAMETER
SN54S04
SN74S04
TEST CONDITIONS
MIN
UNIT
TYP
MAX
3
4.5
3
5
4.5
5
ns
ns
Clock
POST OFFICE BOX 655303
F
• DALLAS, TEXAS 75265
9 ns pulse width FWHM is in good
agreement with 74LS04 specs
7
How Can Oscilloscope Probe Avoid
Reflections In Transmitting Pulse?
•
The “x10” probe has a parallel R and C compensated voltage divider
network to reduce the capacitance seen by the external circuit
•
This decreases the rise time for a given source resistance (see
Problem 1 on 2011 midterm)
•
But with fast rise time pulses, one also needs to prevent reflections due
to the unterminated transmission line
•
This is crucial when the rise time is comparable to the length of time it
takes for a pulse to traverse the cable
•
Resistive wire in cable (‘lossy transmission line”) and other features are
provided in high bandwidth probes to absorb the energy which would
otherwise be reflected, distorting the signal
•
A nice article on this subject is here:
Secret world of oscilloscope probes
(http://esvc000124.wic048u.server-web.com/links/THE%20SECRET%20WORLD%20OF%20PROBES%20OCt09.pdf)
NIM Electronics
AN INTRODUCTION TO NIM (From Fermilab web site)
The NIM standard (DOE/ER-0457), originally an acronym for Nuclear Instrumentation Methods, was established in 1964 for the
nuclear and high energy physics communities. The goal of NIM was to promote a system that allows for interchangeability of
modules. Even today experimenters use NIM modules to assemble a system which meets the specific requirements of their
experiment.
Standard NIM modules are required to have a height of 8.75", and must have a width which is a multiple of 1.35". Modules with a
width of 1.35" are referred to as single width modules and modules with a width of 2.7" are double width modules, etc. The NIM
crate, or NIM bin, is designed for mounting in EIA 19" racks, providing slots for 12 single-width modules. The power supply,
which is in general, detachable from the NIM bin, is required to deliver voltages of +6 V, -6 V, +12 V, -12 V, +24 V, and -24 V.
The standard NIM power connectors and pinouts are shown the Bin Connector Diagram, Module Connector Diagram and Pin/
Function Table. The LeCroy NIM bin and power supply, Model 1403, adhere to all NIM specifications.
The NIM standard also specifies three sets of logic levels. In fast-negative logic, usually referred to as NIM logic, logic levels are
defined by current ranges. Since the standard also requires 50 W input/out impedances, these current ranges correspond to
voltages of 0 V and -0.8 V for logic 0 and 1 respectively. Fast-negative logic circuitry can provide NIM signal with rise times of
order 1 nsec. Slow-positive logic, is rarely used in fast-pulse electronics due to the slow rise times involved, and is not
implemented in LeCroy modules. Specifications for ECL (emitter-coupled logic) voltage levels and interconnections have been
added to the NIM standard at the request of LeCroy. The logic levels, header sizes, cable terminations, etc., is specified in the
standard. The TTL logic system may be used in NIM modules, but is not specified in the NIM standard. LeCroy provides the
Model 688AL and the Model 4616 for NIM/TTL and ECL/NIM/ECL level translations. LeCroy also provides the Model 4501A
adaptor, which allows a NIM modules to be used in a CAMAC crate.
(From http://www-esd.fnal.gov/esd/catalog/intro/intronim.htm)
•
ECL can be made to interoperate directly with NIM logic
levels with suitable choice of offset ECL power supply
voltages
Collider Detector at Fermilab (CDF)
Control Room – Lots of fast pulses!
•
Collecting data from high energy proton-antiproton
collisions. But not all chips are microchips in this experiment
(see foreground).
•
Note NIM electronics bin in rack near back corner
Some CDF Control Room Electronics
•
•
NIM Bin
•
Much custom electronics
in use elsewhere in
experiment, some
“standard” (e.g.VME),
some not
•
Similar equipment is also in
use in the Physics122 lab
next door in Roessler
Some of the other bins are
CAMAC bins
