DEVICES & CIRCUITS – Emitter Coupled Logic
Course DEVICES & CIRCUITS
Chapter: Emitter Coupled Logic
Michael E. Auer
Source of figures:
Jaeger/Blalock: Microelectronic Circuit Design,
McGraw-Hill
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
Course Content
Introduction and Milestones in Microelectronics
Solid-state Electronics
Solid-state Diodes and Diode Circuits
Field-effect Transistors (FET)
Bipolar Junction Transistors (BJT)
Introduction to Digital Microelectronics
NMOS Logic Circuits
Complemetary MOS Logic (CMOS)
Bipolar Logic Circuits (TTL)
Bipolar Logic Circuits (ECL)
Semiconductor Memories
Application Specific Integrated Circuits (ASIC)
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
Chapter Content
The Current Switch / Der Stromschalter
Emitter-Coupled Logic (ECL) / Emittergekoppelte Logik
ECL OR-NOR Gate / ECL OR-NOR Gatter
Power-Delay Characteristics / Geschwindigkeits-Leistungsprodukt
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
Chapter Content
The Current Switch / Der Stromschalter
Emitter-Coupled Logic (ECL) / Emittergekoppelte Logik
ECL OR-NOR Gate / ECL OR-NOR Gatter
Power-Delay Characteristics / Geschwindigkeits-Leistungsprodukt
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
The Current Switch (1)
Ground!
•
Michael E.Auer
09.10.2013
The building block of
emitter-coupled logic
(ECL) is the current switch
circuit.
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
The Current Switch (2)
•
Michael E.Auer
Depending on how much higher or lower the input voltage
vI is compared to VREF, the reference current will switch to
one of the legs creating a voltage vC1or vC2 .
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
The Current Switch Analysis for vI > VREF
•
For the circuit shown under the given bias conditions (vI is
300 mV larger than VREF), the majority of current will
flow in the left-hand leg
iE1 ≅ IEE
iE 2 ≅ 0
vC1 = −iC1RC ≅ −α F iE1RC ≅ −α F IEE RC
vC 2 = −iC 2 RC ≅ −α F iE 2 RC ≅ 0
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
The Current Switch Analysis for vI < VREF
•
For the circuit shown under the given bias conditions (vI is
300 mV less than VREF), the majority of current will flow
in the right-hand leg
iE1 ≅ 0
iE 2 ≅ IEE
vC1 = −iC1RC ≅ −α F iE1RC ≅ 0
vC 2 = −iC 2 RC ≅ −α F iE 2 RC ≅ −α F IEE RC
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
Chapter Content
The Current Switch / Der Stromschalter
Emitter-Coupled Logic (ECL) / Emittergekoppelte Logik
ECL OR-NOR Gate / ECL OR-NOR Gatter
Power-Delay Characteristics / Geschwindigkeits-Leistungsprodukt
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
The Emitter-Coupled Logic (ECL) Gate
•
•
•
The outputs of the previous current switch have the value of either 0 V
or –0.6 V
The difference of the input and output of the current switch is one
base-emitter voltage drop (0.7 V)
For a complete ECL gate, the voltages are shifted by a base-emitter
drop as shown in the figure
to avoid saturation!
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
ECL Gate Summary
vI
vO1
vO2
IIN
VREF + 0.3V = -0.7V
-1.3V -0.7V
+14.3µA
VREF - 0.3V = -1.3V
-0.7V -1.3V
0
iEE
iIN = iB1 =
βF + 1
iIN = 0
V + VL
VREF = H
2
Michael E.Auer
09.10.2013
for
v I = −0.7 V
for
v I = −1.3 V
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
ECL Gate Benefits
•
ECL gates produce both true and complemented outputs
•
ECL gates are fast since the BJTs are always in the
forward-active mode, and it only takes a few tenths of a
volt to get the output to change states, hence reducing the
dynamic power
•
ECL gates provide nearly constant power supply current
for all states thereby creating less noise to the other circuits
connected to the supply
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
Current Source Implementation
•
Instead of using actual current sources for the biasing in an ECL gate,
resistors can be used as shown below
Note that the currents in the
emitter-follower legs will not
be equal since the output
voltages will be different.
The current will instead be
looked at as an average
value between the two legs.
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
ECL Gate Design Example (1)
Design an ECL gate with the circuit configuration shown on the
previous slide to operate at a power supply of –3.3 V given the
following information:
V H = −0.7 V
VL = −1.3 V
∆V = 0.6 V
VREF = −1.0 V
IE 2 = 0.3 mA
Use a mean emitter-follower
current of 0.1 mA.
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
ECL Gate Design Example (2)
For vI = –1.3 V, Q1 will be off and Q2 will be on causing the
emitter node voltage to be –1.7 V. REE can now be calculated
by the following:
REE
−1.7 − (−3.3) V
=
= 5.33 kΩ
0.3
mA
And RC2 is:
RC 2 =
Michael E.Auer
∆V
∆V
∆V 0.6 V
=
≅
=
= 2.0 kΩ
IC 2 + IB 4 IC 2 + IB 2 + (IB 4 − IB 2 ) IE 2 0.3 mA
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
ECL Gate Design Example (3)
For vI = –0.7 V, Q2 will be off and Q1 will be on causing the
emitter node voltage to be –1.4 V. IE1 can now be calculated
by the following:
−1.4 − (−3.3) V
IE1 =
= 357 µA
2
kΩ
Now RC1 can be found as:
0.6V
∆V
∆V
RC1 =
= 1.68 kΩ
=
≅
IC1 + IB 3 IE1 0.357mA
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
ECL Gate Design Example (4)
Finally, R can be calculated by using
the mean output voltage and current
levels
V H + VL
− (−VEE ) −1+ 3.3 V
2
R=
≅
= 23 kΩ
IE 3
0.1 mA
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
The Emitter Follower
•
•
Michael E.Auer
The main purpose of the emitter follower in ECL gates is to create a
level shift in the output
The figure shows both the circuit and its transport model for the
forward-active region
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
VTC of the Emitter Follower
•
Michael E.Auer
09.10.2013
The emitter follower is
so named since the
voltage at the emitter
follows the voltage at
the base, but at an
offset of one diode
drop which can be
seen in the ideal VTC.
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
The Emitter Follower with Resistor Bias
•
•
As previously shown, the current source can be replaced with a resistor
bias scheme
This technique will cause a small change in vBE due to the variation of
iE as vO changes, but this change is minimal.
vO = vI – 0.7V
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
Design of Reference Voltage Circuits
•
•
Michael E.Auer
So far the implementation of the VREF signal has not been discussed, but it can
be created with a simple resistor voltage divider as seen below.
The Thévenin equivalent circuit is used to show that the voltage at the base of
Q2 will not be exactly 1V as designed, due to the fact that there will be a
voltage drop across the Thévenin resistance induced by iB2.
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
Reference Voltage Temperature Compensation
•
•
Michael E.Auer
Since the vBE of the BJT changes by approximately –1.8 mV/K, it is obvious
that when REE is used to replace the current switch current source, that iE2will
vary with temperature.
Two techniques are shown below that temperature compensate (track) the
variation.
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
Chapter Content
The Current Switch / Der Stromschalter
Emitter-Coupled Logic (ECL) / Emittergekoppelte Logik
ECL OR-NOR Gate / ECL OR-NOR Gatter
Power-Delay Characteristics / Geschwindigkeits-Leistungsprodukt
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
The ECL OR-NOR Gate
Three variations of a 3input ECL OR-NOR Gate
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
Emitter Dotting
Michael E.Auer
09.10.2013
•
The circuit shown in the
figure represents two
emitter followers in parallel
with a common output
•
For the bias condition
shown, Q2 is cutoff and Q1
has to handle 2IEE
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
Wired-OR Logic Function
Michael E.Auer
09.10.2013
•
The parallel emitter on the
previous slide can be used
to implement an OR
function as shown in the
figure, also called the
Wired-OR
•
This is distinct to ECL
logic since in most logic
families, outputs cannot be
tied together
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
Chapter Content
The Current Switch / Der Stromschalter
Emitter-Coupled Logic (ECL) / Emittergekoppelte Logik
ECL OR-NOR Gate / ECL OR-NOR Gatter
Power-Delay Characteristics / Geschwindigkeits-Leistungsprodukt
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
ECL Power Dissipation
•
The average static power of an ECL inverter can be found
from the following expression:
P = -VEE (IEE + I3 + I4)
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
Power Reduction (1)
•
Approximately 40% of the power is dissipated by the
emitter-follower stages
•
One technique to reduce this current is to bias the emitterfollower resistors from a less negative supply thereby
reducing the current. However this requires an additional
power supply.
•
Another technique is to share the current in the manner
shown on the next slide (similar to the wired-OR).
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
Power Reduction (2)
Changing the power supply
Repartitioned ECL gate
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
Gate Delay (1)
ECL inverter with
capacitors shown
Simplified ECL gate model
for dynamic response
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
Gate Delay (2)
•
The gate delays and voltages can be calculated
with following expressions:
IEE RC
vC 2 (τ PHL ) = vC 2 (τ PLH ) = −
2
τ PLH = τ PHL = 0.69RC CL
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
Power-Delay Product
Michael E.Auer
09.10.2013
BST11
DEVICES & CIRCUITS – Emitter Coupled Logic
Summary
•
•
•
•
•
•
•
•
Michael E.Auer
The ECL gate introduced two circuit techniques: the current switch and the emitter-follower
circuit. The current switch consists of of two matched BJTs and a current source. This circuit
switches the bias current back and forth between the two transistors, based on a
comparison of the logic input signal with a reference voltage.
In the ECL gate, the transistors actually switch between two points in the forward-active
region, which is one reason why ECL is the highest speed form of bipolar logic.
A second factor is the relatively small logic swing, typically in the range of 0.4 to 0.8V.
ECL is typically designed to operate from a single negative power supply, historically -5.2V
and now often -3.3V. Therefore VOH and VOL are negative voltages.
ECL logic gates generate both true and complement outputs, and the basic ECL gate
provides the OR-NOR logic functions.
In the emitter-follower circuit the output signal replicates the input signal except for a fix
offset equal to one base-emitter diode voltage (0.7V). The fixed voltage level offset is used
to provide the level-shifting function needed to avoid the transistors to be saturated.
The emitter followers permit additional logic power through the use of the “wired OR”
technique.
Temperature compensated reference circuits are used to provide the reference voltage
required in the ECL gate.
09.10.2013
BST11