LOW COST PWM CONTROLLER
AN99-5
January 13, 2000
APPLICATION NOTE FOR SC1101/03
INTRODUCTION
DESCRIPTION
FEATURES
The SC1101/03 is a versatile, low-cost,
voltage-mode PWM controller designed for
use in single ended DC/DC power supply applications. A simple, fixed-voltage buck regulator can be implemented using the
SC1101/03 with a minimum of external components. Internal level shift and drive circuitry
eliminates the need for an expensive pchannel, high-side switch. The small device
footprint allows for compact circuit design.
•
•
•
•
•
•
SC1101/03 features include a temperature
compensated voltage reference, triangle
wave oscillator, current limit comparator, frequency shift over-current protection, and an
internally compensated error amplifier. Pulse
by pulse current limiting is implemented by
sensing the differential voltage across an external resistor, or an appropriately sized PC
board trace.
BLOCK DIAGRAM
Low cost / small size
Switch mode efficiency (90%)
1% reference voltage accuracy
Over current protection
500mA output drive
5V to 12V Input power source
The SC1101/03 operates at a fixed frequency
of 200kHz, providing an optimum compromise between efficiency, external component
size, and cost.
The SC1103’s manufacturing process has
been optimized for 12V operation and is
capable of handling up to 26V at it’s BST
pin.
APPLICATIONS
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•
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•
Pentium® P55 Core Supply
Low Cost Microprocessor Supplies
Peripheral Card Supplies
Industrial Power Supplies
High Density DC/DC Conversion
1
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
LOW COST PWM CONTROLLER
AN99-5
January 13, 2000
LAYOUT GUIDELINES
Careful attention to layout requirements are necessary
for successful implementation of the SC1101/03 PWM
controller. High currents switching at 200kHz are present
in the application and their effect on ground plane voltage differentials must be understood and minimized.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and
position of ground plane interruptions should be such as
to not unnecessarily compromise ground plane integrity.
Isolated or semi-isolated areas of the ground plane may
be deliberately introduced to constrain ground currents
to particular areas, for example the input capacitor and
bottom Schottky ground.
tant, however adding unnecessary impedance will reduce efficiency.
4) The Output Capacitor(s) (Cout) should be located as
close to the load as possible, fast transient load currents
are supplied by Cout only, and connections between
Cout and the load must be short, wide copper areas to
minimize inductance and resistance.
5) The SC1101/03 is best placed over an isolated
ground plane area. GND and PGND should be returned
to this isolated ground. This isolated ground area should
be connected to the main ground by a trace that runs
from the GND pin to the ground side of (one of) the output capacitor(s). If this is not possible, the GND pin may
be connected to the ground path between the Output
2). The loop formed by the Input Capacitor(s) (Cin), the Capacitor(s) and the Cin, Q1, D1 loop. Under no circumstances should GND be returned to a ground inside the
Top FET (Q1) and the Schottky (D1) must be kept as
small as possible. This loop contains all the high current, Cin, Q1, D1 loop.
fast transition switching. Connections should be as wide 6) Vcc for the SC1101/03 should be supplied from the
and as short as possible to minimize loop inductance.
VIN supply through a 10Ω resistor, the Vcc pin should be
Minimizing this loop area will reduce EMI, lower ground decoupled directly to GND by a 0.1mF ceramic capaciinjection currents, resulting in electrically “cleaner”
tor, trace lengths should be as short as possible.
grounds for the rest of the system and minimize source 7) The Current Sense resistor and the divider across it
ringing, resulting in more reliable gate switching signals. should form as small a loop as possible, the traces running back to CS(+) and CS(-) on the SC1101/03 should
3). The connection between the junction of Q1, D1 and
the output inductor should be a wide trace or copper re- run parallel and close to each other. The 0.1µF capacitor
should be mounted as close to the CS(+) and CS(-) pins
gion. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connec- as possible.
tion short will minimize EMI. The connection between the 8) To minimize noise pickup at the sensitive FB pin, the
output inductor and the sense resistor should be a wide feedback resistors should both be close to the
trace or copper area, there are no fast voltage or current SC1101/03 with the bottom resistor (Rb) returned to
transitions in this connection and length is not so impor- ground at the GND pin.
12V
24V IN
10
0.1uF
2.32k
Cin
Q1
SC1103CS
1
2
3
0.1uF
4
VCC
CS(-)
GND
FB
CS(+)
BST
PGND
DH
+
1.00k
8
5mOhm
Vout
7
4uH
Rb
6
+
D1
Cout
5
Ra
Heavy lines indicate
high current paths.
2
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
AN99-5
LOW COST PWM CONTROLLER
January 13, 2000
TYPICAL APPLICATIONS
1. Small footprint - Low power
This circuit utilizes SO-8 MOSFET and SMC Schottky Diode. The area is 1 sq. in.
Top - Component View
Bottom - Component View
Top - Copper
Bottom - Copper
D2
LL42
C6
0.1
L1
6.8uH
Q1
Si4420DY
+5V
R5
0.02
+2.5V
R6
124
C1
0.1
C7
1500/6.3V
C2
1500/6.3V
D1
B520C
C8
0.1
R7
124
GND
GND
R1
10
U1
SC1103
1
R2
1k
C3
0.1
R3
1k
2
C4
0.01
3
4
VCC
GND
Cs(-)
FB
Cs(+)
BST
PGND
DH
R4
2.7
8
C5
0.01
7
6
5
5V to 2.5V @ 4A with “flying capacitor” boost voltage.
3
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
AN99-5
LOW COST PWM CONTROLLER
January 13, 2000
TYPICAL APPLICATIONS (Cont.)
2. Small footprint - Medium power
This circuit utilizes DPAK MOSFET and Schottky Diode. The area is 2.2 sq. in.
Top - Component View
Bottom - Component View
Top - Copper
Bottom - Copper
L1
5.6uH
Q1
IRLR3103
+5V
R5
0.01
+3.3V
R6
205
C1
0.1
C2
1500/6.3V
D1
MBRD835lL
C3
1500/6.3V
C9
1500/6.3
C10
1500/6.3
C11
1500/6.3V
C12
0.1
R7
124
GND
GND
R1
10
U1
SC1101
1
VCC
GND
R4
2.7
8
C7
0.01
R2
1k
R3
1k
C5
0.1
2
C6
0.01
3
4
Cs(-)
FB
Cs(+)
BST
PGND
DH
7
6
5
C8
0.1
+12V
5V to 3.3V @ 8A
4
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
AN99-5
LOW COST PWM CONTROLLER
January 13, 2000
TYPICAL APPLICATIONS (Cont.)
3. Medium footprint - High power
This circuit utilizes D2PAK MOSFET and Schottky Diode. The area is 4.1 sq. in.
Bottom
Top
D2
LL42
C8
0.1
L1
5.6uH
Q1
IRL3103S
+12V
R5
0.01
Vout(+)
R6
205
C1
0.1
C2
820/16V
C9
1500/6.3
C4
820/16V
C3
820/16V
D1
MBRB1530CT
C10
1500/6.3
C11
1500/6.3V
C12
0.1
3.3V
R7
124
Vout(-)
GND
R1
10
U1
SC1103
1
R2
1k
R3
1k
C5
1.0
2
C6
0.01
3
4
VCC
GND
Cs(-)
FB
Cs(+)
BST
PGND
DH
R4
2.7
8
C7
0.01
7
6
5
12V to 3.3V @ 10A with “flying capacitor” boost voltage.
5
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
AN99-5
LOW COST PWM CONTROLLER
January 13, 2000
TYPICAL PLOTS & WAVEFORMS
40
180
35
0.050
30
135
90
Phase (deg)
Gain (dB)
20
15
Gain
Phase
10
45
5
Voltage Change (V)
Normalized to 0 at Io=2A.
0.040
25
0.030
0.020
0.010
0.000
-0.010
0
0
-0.020
0
-5
2
4
6
8
10
Current (Amps)
-10
100.0E+0
1.0E+3
10.0E+3
100.0E+3
1.0E+6
-45
10.0E+6
Frequency (Hz)
Fig.1: Error Amplifier, Gain and Phase
Fig. 2: Load Regulation @ VO = 3.3V, VIN = 12V
1.0%
0.8%
Load Regulation
0.6%
0.4%
Vo=
1.8V
2.5V
3.3V
5.0V
0.2%
0.0%
-0.2%
-0.4%
-0.6%
-0.8%
-1.0%
0
2
4
6
8
10
12
14
Output Current, (A)
Fig. 4: Load Regulation @ VIN = 12V
Fig. 3: VRIPPLE @ VIN = 12V, VO = 3.3V, IO = 10A
0.5%
100%
0.4%
90%
Efficiency
80%
1.8V
2.5V
3.3V
5V
70%
60%
Line Regulation
0.3%
0.2%
0.1%
0.0%
-0.1%
-0.2%
-0.3%
50%
-0.4%
40%
0
2
4
6
8
Output Current, (A)
Fig. 5: Efficiency @ VIN = 12V
10
12
14
-0.5%
11.4
11.6
11.8
12.0
12.2
12.4
12.6
Input Voltage, (V)
Fig. 6: Line Regulation @ VO = 3.3V, IO = 10A
6
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
LOW COST PWM CONTROLLER
AN99-5
January 13, 2000
OUTLINE DRAWING
JEDEC
REF: MS-012AA
LAND PATTERN SO-8
7
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320