IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 4, APRIL 2010
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Real-Time Electrical Load Emulator Using Optimal
Feedback Control Technique
Y. Srinivasa Rao, Member, IEEE, and Mukul C. Chandorkar, Member, IEEE
Abstract—This paper presents a method of emulating electrical
loads using power electronic converters. The loads include machines such as induction motors and their associated mechanical
load and also more complex machine systems such as wind-driven
generators. The load emulator is, effectively, a dynamically controllable source or sink which is capable of bidirectional power
exchange with either a grid or another power electronic converter
system. Using load emulation, the feasibility of connecting a particular machine to a grid under various load conditions can be
examined without the need for any electromechanical machinery.
This paper considers the case of a power electronic voltage source
inverter (VSI) emulating a three-phase induction motor connected
to a three-phase ac grid. The VSI is operated in a mode where
the current drawn from the ac grid is controlled by closed-loop
control. The consistency of the experimental results with the simulation results proves the ability of the emulator and the proposed
testing approach.
Index Terms—Digital signal processor (DSP), induction motor,
linear quadratic regulator (LQR), load emulator, phase-locked
loop (PLL), real-time simulation, voltage source inverter (VSI).
I. I NTRODUCTION
L
OAD EMULATION is the concept of controlling a power
electronic converter such as a voltage source inverter
(VSI) in such a manner that its behavior resembles that of an
electrical load such as an induction machine. Rapid prototyping
[1], [2] is a method of verifying the control techniques that
are implemented in embedded systems such as digital signal
processors (DSP). Reference [1] describes a method of simulating the details of DSPs and their associated analog-to-digital
interface. Reference [2] describes a method of combining simulations of the power circuit and the control circuit to closely
describe the behavior of the practical system that would be
implemented. There is an increasing usage of hardware-in-theloop technologies that design and test control systems [3]–
[5]. Currently, there are several kinds of real-time simulation
platforms [6]–[9] in academia and industry. However, load
emulation, as presented in this paper, provides a platform where
the behavior of an electrical load can be emulated in hardware
at real power levels using a controllable VSI. The load emulator
Manuscript received December 30, 2008; revised November 16, 2009. First
published December 4, 2009; current version published March 10, 2010.
Y. Srinivasa Rao is with the Department of Electrical Engineering, Indian
Institute of Technology Bombay, Mumbai 400076, India, and also with the
Sardar Patel Institute of Technology, University of Mumbai, Mumbai 400058,
India (e-mail: ysrao@ee.iitb.ac.).
M. C. Chandorkar is with the Department of Electrical Engineering,
Indian Institute of Technology Bombay, Mumbai 400076, India (e-mail:
mukul@ee.iitb.ac.in).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2009.2037657
Fig. 1. Schematic diagram of the load emulator.
can provide different load characteristics with which the control
algorithms and inverter design can be tested. Therefore, load
emulation offers a more flexible platform for testing inverters
in a laboratory environment.
The primary objective of load emulation is to design the
power interface for the actual electrical load. Therefore, the
behavior of the load emulator must be close to the actual load
when connected to a power supply. The load emulator configuration is shown in Fig. 1, where the power supply can be a threephase grid or another three-phase VSI. Therefore, accurate
information of the phase angle of the power supply voltages is
essential. The phase angle of a three-phase voltage is obtained
through the popular method called phase-locked loop (PLL).
This takes as its input the three-phase voltages of the power
supply and produces a sinusoidal signal of the same frequency
as the frequency of the supply voltages. The topic of PLL has
been extensively reported in literature [10]–[12]. However, the
effectiveness of the PLL has not been investigated in conditions
where the input voltages are the pulsewidth modulated (PWM)
voltages of a VSI with a switching frequency of approximately
5 kHz.
The main component of load emulation is the algorithm that
generates the desired currents to be drawn so as to mimic the
actual load. Thereafter, the control system ensures that the VSI
draws or supplies currents that are as close as possible to the
desired current references. The load emulator VSI is connected
to the power supply through an interface impedance known
as the filter. The topology of the filter discussed in this paper
has been chosen to be an inductor–capacitor–inductor (L–C–L)
filter. Since the load emulator VSI mimics the behavior of an
electrical load, it would have to draw or source active power as
per load characteristics. In order to enable the emulator VSI
to be a sink or source of active power, a back-to-back VSI
topology has been proposed. The dc link of the emulator
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 4, APRIL 2010
VSI is common to another VSI known as the reverse power
flow converter. This reverse power flow converter is a threephase VSI whose ac output is interfaced to the three-phase ac
grid. This converter draws or supplies active power from the
three-phase ac grid for the emulator VSI.
Two controllers are implemented for the entire system. In
order to ensure bidirectional power flow, the reverse power flow
converter is controlled in current control mode. The voltage of
the dc link common to both the emulator VSI and the reverse
power flow converter is maintained constant by this controller.
This current controller of the reverse power flow converter is
not the focus of this paper, and reported literature contains
this in sufficient detail [13]. The load emulator VSI that is
interfaced to the three-phase power supply through the L–C–L
filter has been controlled through an optimal control strategy.
The optimal feedback controller used is a linear quadratic
regulator (LQR) that has been discussed in this paper. This
paper also investigates the capability of the optimal controller,
and therefore, the limits of load emulation are presented.
Fig. 2. Inverter interface with an LC filter. (a) Inverter interface with an
inductor. (b) Inverter interface with an LC filter.
II. P RINCIPLE OF L OAD E MULATION
DSPs and microcontrollers have been widely used in implementing digital motor control algorithms [14], [15]. However, the processing speed of DSPs needs to be on the order
of microseconds to nanoseconds in order to deal with the
hardware-rich tasks. This becomes difficult with the software
computation environment. A hardware control system using a
field programmable gate array (FPGA) has been reported [16]–
[19]. One disadvantage of FPGAs is that they need many resources for complex mathematical operations since they are not
arithmetic-oriented like DSPs [20]. Fig. 1 shows the schematic
diagram of the load emulator with the associated digital control
consisting of a DSP and an FPGA. The diagram shows the
L–C–L filter that is used to interface the load emulator VSI
to the three-phase power supply. It also shows the three-phase
power supply as the three-phase distribution level ac grid. In the
later sections, the power supply will also be a three-phase VSI.
The supply voltages vs are used in generating references for
the currents to be drawn by the emulator VSI. The references
are generated by an algorithm in the DSP. The PLL is also
an essential component of reference generation and is implemented in DSP. The current is drawn from the three-phase ac
grid is the current that must be controlled to be approximately
equal to the reference currents. The optimal control algorithm
is implemented in DSP and requires the feedback of both the
currents is and the emulator VSI currents if . The PWM signals
are generated by the FPGA and fed to the gate drivers of the
emulator VSI. Before describing the optimal feedback control
strategy, a justification for using the L–C–L filter as an interface
between the emulator VSI and the ac grid is provided.
The well-reported method for current injection requires an
inverter with an output inductor filter [Fig. 2(a)]. In Fig. 2(a),
the VSI is connected to the ac grid as a node that is called as the
point of common coupling (PCC). With this topology, the current injected into the PCC would contain a substantial amount
of switching harmonic ripple. Due to the internal impedance
of the grid shown in Fig. 2(a), the voltage at the PCC will be
Fig. 3.
Emulator interface with an LCL filter.
distorted. Therefore, by connecting a VSI to the ac grid, a power
quality problem has been introduced.
As shown in Fig. 2(b), by connecting a capacitor Cf , a lowpass filter is present at the output of the VSI. This provides
a low-impedance path for high switching frequency ripple.
Therefore, the PCC voltages will be smooth. However, since
is = ic + if , current drawn from the grid will be different from
the desired references. Although a larger filter capacitor Cf will
provide smoother PCC voltages, the error in the currents drawn
from the grid will increase as ic = Cf · dvpcc /dt. Moreover, if
the ac grids were to be replaced by another inverter, the current
injection strategy would not work as the VSI replacing the grid
would not have an internal impedance.
Fig. 3 shows an LCL output filter structure which will
provide a solution to the two aforementioned drawbacks [21].
The Lf Cf filter removes some of the switching frequency
harmonics, resulting in a current through Ls that is relatively
smooth. The control strategy employed will attempt to control
the current is through the inductor Ls . Therefore, the error
in the current is from its desired reference will be negligible.
Moreover, in the case of the inverter being interfaced to another
inverter, the voltage at the filter capacitor Cf resembles a
back-emf, and therefore, the interfacing problems are removed.
Two methods of controlling is so that this is approximately
equal to the desired references have been examined. The first
method is an indirect method where the reference for vf has
been generated from the reference for is . The voltage vf can
be controlled, making it approximately equal to its reference
by using the flux modulator strategy [22]. Current is can be
directly controlled by using the optimal feedback controller.
This controller is a state feedback controller designed using the
LQR technique [23]–[25]. Both currents is and if are measured
and fed back to be compared with their respective references.
Voltage vf is implicitly controlled. In the case of the VSI
SRINIVASA RAO AND CHANDORKAR: ELECTRICAL LOAD EMULATOR USING OPTIMAL FEEDBACK CONTROL
Fig. 4.
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Closed-loop control scheme of the optimal feedback controller.
emulating an induction motor, the voltage across the capacitor
Cf is related to the induced rotor voltage of the induction motor.
A detailed description of the optimal feedback controller is
provided in the next section.
III. C ONTROLLER D ESIGN
The control system ensures that the emulator draws a current is that is approximately equal to the desired reference.
The transient response of the system determines the tracking
accuracy between the demanded and actual current drawn from
the inverter under test. Here, the control technique used is a state
feedback control strategy. Fig. 4 shows the closed-loop control
scheme employed for the VSI in Fig. 3. The state vector is
x = [ is
vf
if ]T .
(1)
The state space equations are obtained by applying Kirchoff’s
current law and Kirchoff’s voltage law to Fig. 3
⎡
⎤
−rs /Ls −1/Ls
0
ẋ = ⎣ 1/Cf
0
−1/Cf ⎦ x
0
1/Lf −rf /Lf
⎤
⎡
⎤
⎡
1/Ls
0
⎦ u + ⎣ 0 ⎦ vs
(2)
+⎣
0
0
−Vdc /Lf
y = is = [ 1 0
0 ] x.
(3)
The output variable y is therefore the current is that is
injected into the grid. However, as stated in the previous section,
both currents if and is are measured. The voltage vf across the
filter capacitor Cf also forms the state vector along with if and
is . However, its measurement has been excluded (a description
has been provided later in the section).
The objective of the VSI is to inject a current is that is
approximately equal to a desired reference isr . In the aforementioned equation, u is the emulator inverter’s switching function,
and ac grid voltage vs is considered to be a disturbance. The
state feedback controller is an optimal controller designed using
the LQR to achieve the objective [23].
For implementation using DSP, the controller is realized in
a discrete-time form. The continuous-time state equations are
converted to standard state space discrete-time form
x(n + 1) = Gx(n) + Hu u(n) + Hw w(n)
y(n) = Cx(n).
(4)
(5)
Here, w(n) = vs (nTs ) is a disturbance, and Ts is the sampling
time interval. The LQR seeks to minimize a performance index
J=
∞
1 T
e (n)Qe(n) + uT
c (n)Ruc (n)
2 n=0
(6)
Fig. 5. Closed-loop frequency response of the system.
where e = xr − x and T stands for the transpose of a vector.
In (6), Q is a diagonal matrix that decides the importance to
be given to the state variables, and R is the penalty which is
imposed on the controller. The dlqr function of the simulation
provides the state feedback matrix K
uc (n) = K (xr (n) − x(n))
x(n + 1) = Gx(n) + Hu K (xr (n) − x(n)) + Hw w(n)
Y (n) = Cx(n).
(7)
(8)
(9)
To obtain the transfer function between the output variable y
and the reference state vector xr , disturbance w(n) is neglected.
Equation (8) can be written as
x(n + 1) = Gx(n) + Hu Kxr (n) − Hu Kx(n).
(10)
This can be written as
x(n + 1) = (G − Hu K)x(n) + Hu Kxr (n)
y(n) = Cx(n).
(11)
(12)
Equations (11) and (12) are the closed-loop state equations. The
system parameters are chosen as Ls = 3 mH, Rs = 0.01 Ω,
Lf = 1 mH, Rf = 0.01 Ω, and Cf = 50 μF. The choices for
Q and R are
⎡
⎤
50
0
0
Q = ⎣ 0 0.05
0 ⎦ R = 65
(13)
0
0
0.01
where the weightage for is is chosen to be much larger than the
other states in the matrix Q. K = [0.6188 0.0404 0.0929],
with a sampling time of 20 μs. Since the control coefficient
for error in vf is extremely small [0.0404], it is possible to set
this constant at zero. This also provides another advantage of
eliminating measurement of vf .
The closed-loop frequency response characteristics can be
represented in a Bode plot as shown in Fig. 5. In Fig. 5, it can
be observed that the gain of the closed-loop system is unity for
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Fig. 6. Simulation of control system for harmonic references.
Fig. 8. Closed-loop scheme of the PLL. (a) Block diagram of the control
system. (b) Notch filter design.
This system using a notch filter and PID controller which
produce accurate information of the phase angle is discussed
in this section.
The basic control scheme of the PLL can be described as
follows. The grid voltages va , vb , and vc are converted to the
d–q reference frame through the standard transformation of
[10]–[12]
2 cos ω
vd
t sin ω
t
1 √
−1/2 −1/2
√
=
vq
3/2 − 3/2
t cos ω
t
0
3 − sin ω
Fig. 7. Simulation of control system for transient references.
frequencies of up to 10 000 rad/s. Moreover, the phase lag is
approximately zero for frequencies of up to 350 rad/s. From the
simulation results of Fig. 6, current references isr containing
fundamental 50-Hz components can be tracked with negligible
error. Harmonics in the current reference are tracked with a
phase lag. The controller tracks zero current references with
negligible error. Fig. 7 shows the results of transient response
and stability of the system. To enable the VSI to be able to inject
currents containing harmonic components, the bandwidth of the
controller can be increased by redesigning the controller.
IV. T HREE -P HASE PLL S YSTEM
In the proposed system, the reference voltages for the load
models in DSP are derived from the PCC. In Fig. 3, voltage vs
may be a PWM waveform or may be distorted by various external factors. In order to generate current references of particular
harmonic number, the frequency of the grid must be known
accurately. Moreover, in order to generate current references
that may lead or lag the grid voltages, the phase information
of the grid voltages must be known. Therefore, synchronization
and frequency estimation using a PLL scheme are employed.
× [ va
vb
vc ]T . (14)
The closed-loop control scheme of the PLL is shown in
Fig. 8(a). The block “abc to dq transformation” implements the
transformation of (14). Voltage vd is forced to zero through
a PID controller whose output is the estimated angular frequency ω
. In Fig. 8(a), by forcing vd to be equal to zero, the
d-axis of the rotating reference frame is forced to be aligned
with the voltage vector Vs . Therefore, the estimated angular
frequency ω
= ω. In the steady state, the cosine wave cos ω
t
has a frequency equal to the frequency of the grid voltages and
is in phase with the voltage va . When the grid voltages va ,
vb , and vc are balanced, vd can be forced to be very close to
zero, and therefore, the estimated angular frequency ω
will be
constant. However, when the grid voltages are unbalanced, they
possess a negative sequence component. On the transformation
to the d–q frame, the negative sequence component appears as
a component whose frequency is twice that of the fundamental
frequency. Therefore, ω
will contain oscillations of a frequency
twice that of the fundamental frequency. To prevent this, a notch
filter [11] is included after the d–q transformation to remove the
double harmonic component from vd .
Fig. 8(b) shows the design of the notch filter. The “O”s
represent zeros, and “X”s represent poles in the complex z
plane. The fundamental frequency of the grid is close to the
SRINIVASA RAO AND CHANDORKAR: ELECTRICAL LOAD EMULATOR USING OPTIMAL FEEDBACK CONTROL
Fig. 9.
Experimental results of PLL for unbalanced utility voltages.
nominal expected frequency of ω0 = 100π rad/s. The sampling
frequency of the analog-to-digital conversion is fs = 1250 Hz,
and ωs = 2.5π ∗ 103 rad/s. Since the objective of the notch
filter is to remove the double frequency harmonic term, a pair
of complex zeroes is added at z = e±j2ω0 /ωs = e±j0.08 . It is
to be noted that conjugate zeroes are added to ensure that the
coefficients of the filter are real. To ensure that the notch filter
is selective and has a low gain only for frequencies close to
the double frequency harmonic, complex poles are added at the
same frequency as the zeroes but within the unit circle to ensure
stability of the system. By adding the complex poles close to the
unit circle at a magnitude of 0.97 (z = 0.97e±j0.08 ), the system
is fairly resonant with a sharp notch. To ensure that the dc
quantity produced by the d–q transformation corresponding to
the fundamental frequency is not attenuated, another real pole
is added at z = 0.97. The total transfer function of the notch
filter is given by
0.03
z 2 − 1.9974z + 1
Hnf (z) = 4.7692 2
.
z − 1.7976z + 0.81z
z − 0.97
(15)
To prevent quantization errors while implementing in DSP,
the notch filter is implemented in cascade form, with the two
transfer functions within brackets converted separately into
difference equations.
The transfer function of the PID regulator is as follows:
Ki
+ Kd s · E(s).
(16)
Y (s) = Kp +
s
In the system transfer function (16), the derivative term is added
in order to improve system response. Sampling time step dt for
the PLL is selected as 80 μs. Therefore, Ki = 12.5, Kp = 1.0,
and Kd = 0.00004.
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Fig. 10. Performance of the control system and PLL for harmonic currents.
TABLE I
I NDUCTION M OTOR M ODEL PARAMETERS
response slower. This will also make the filter more sensitive to
the variations of the center frequency ωo which may occur in
some power systems. While designing the notch filter of PLL,
it was assumed that the grid frequency will be changed by a
maximum of 3%. Therefore, the PLL will continue to function
for small changes in grid frequency.
A three-phase experimental setup has been built to verify the
accuracy of the proposed system. In this setup, the power circuit
is rated at 30 A, 415-V input/output line-to-line voltages, and
750-V dc bus. Various linear and nonlinear current references,
representing different load characteristics, are emulated experimentally. The average switching frequency of the emulator
inverter was 5 kHz.
A. Current Harmonics
The source of the current harmonics can be considered as
nonlinear loads such as rectifiers.
The upper trace in Fig. 10 shows the tracking performance
of the grid interface emulator for current references containing
odd order harmonic components. In the experiment, these magnitudes are taken as one-third, one-fifth, one-seventh, etc., of
the fundamental current reference. The experimental data are
acquired and stored in real time in the DSP memory and then
plotted offline using a suitable plotting software. The lowest
trace shows the effectiveness of the PLL for distorted PCC
voltages. The PLL is observed to produce smooth waveforms
despite notches in the PCC voltages.
V. E XPERIMENTAL R ESULTS
Fig. 9 shows the performance of the PLL for unbalanced
t is seen to
grid voltages, where vb = 0. The cosine wave cos ω
have the same frequency and phase as that of va . By increasing
the filter’s order, it becomes sharper and hence suppresses the
undesired components even more effectively, but this makes the
B. Induction Motor Model
To implement the controller for the three-phase four-pole
squirrel cage induction motor emulator, the parameters mentioned in Table I are taken as a reference model in generating
reference currents [8].
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 4, APRIL 2010
Fig. 11. Offline simulation. (a) IM model a-phase stator current. (b) Load
emulation of the motor model.
Fig. 12. Experimental results of the motor a-phase stator current.
The model is simulated to obtain the free acceleration characteristics of the machine when started direct-on-line with no
load. While the motor is running under no load steady state,
an 80% rated torque is suddenly applied at t = 1 s to the
rotor in order to observe the transient behavior of the system.
The upper trace in Fig. 11 shows the offline simulation results
of the motor model, and the lower trace shows the emulation results. Fig. 12 shows the experimental waveform of the
a-phase stator current. The offline simulated load model currents and the experimental emulated currents are nearly identical. Fig. 13 shows the experimental waveforms of rotor
mechanical speed, electromagnetic torque, and active power
drawn by the emulator. For the given parameter values shown in
Table I, the transient and steady-state currents of the emulator
are as desired. The current waveforms have a nominal ripple,
and the control system is stable.
C. PWM Reference Voltages
Under the circumstances when both the source and the load
are VSIs, the reference voltages are PWM-type signals as the
source is also a VSI. The switching frequency of the source
VSI is 5 kHz, and the control algorithm is executed every
Fig. 13.
Waveforms for free acceleration of the IM model.
Fig. 14.
Emulator performance for PWM reference voltages.
20 μs. The upper trace in Fig. 14 shows the tracking accuracy
of the load VSI, where the currents drawn are from the inverter
under test. The lower trace shows the effectiveness of the PLL
in synchronizing with the PWM output of the source VSI. The
PLL is seen to synchronize to PWM voltages with negligible
phase error.
Fig. 15 shows the performance of the emulator for the
variable-frequency source VSI. The frequency and amplitude
of the source VSI are modulated from 0 to 50 Hz and 0.1 to 0.9,
respectively, over a period of 0–4 s. The upper trace in Fig. 15
shows the tracking accuracy of the emulator for constant v/f
reference currents, and the lower trace shows the response of
the emulator for the IM load model a-phase startup currents.
D. Unbalanced Three-Phase Three-Wire Load
Fig. 16 shows the emulator drawing unbalanced currents
from the source VSI. It is to be noted that, with the source
VSI being a three-phase three-wire VSI, the sum of the currents
drawn must be equal to zero. Therefore, the sum of the references for the currents to be drawn by the load VSI is also zero,
with a 50% unbalance in the b-phase current. The lower trace
SRINIVASA RAO AND CHANDORKAR: ELECTRICAL LOAD EMULATOR USING OPTIMAL FEEDBACK CONTROL
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Fig. 17. Single-phase diode bridge rectifier.
Fig. 15. Emulator performance for the v/f control source VSI.
Fig. 18. Experimental results of the emulator for the delta-connected diode
rectifier.
Fig. 16.
Emulator performance for three-phase unbalanced current references.
shows the tracking performance where the reference is tracked
with negligible error. These results demonstrate that this control
system, along with PLL, can be used to test the inverters with
acceptable accuracy.
E. Nonlinear Active Load
Three single-phase diode bridge rectifiers connected between
three phases and a neutral is used as a nonlinear load model.
Fig. 17 shows the diagram of a single-phase rectifier with a
large filter capacitor. The nonlinear circuit is represented by
three cases. Case 1 of the circuit is where diodes D1 and D2
are in the on state and D3 and D4 are in the off state. For this
case, when vs > vdc or is > 0, the system can be expressed as
d is
−Rs /Ls
is
−1/Ls
=
1/Cdc
−1/(Rload · Cdc )
vdc
dt vdc
1/Ls
+
vs . (17)
0
Case 2 of the circuit is where diodes D3 and D4 are in the on
state and D1 and D2 are in the off state. For this case, when
−vs > vdc or is < 0, the system can be expressed as
d is
−Rs /Ls
is
1/Ls
=
−1/Cdc −1/(Rload · Cdc )
vdc
dt vdc
1/Ls
+
vs .
0
(18)
When diodes D1, D2, D3, and D4 are in the off state (i.e.,
neither case 1 nor 2 are satisfied), therefore, is = 0.
To solve the circuit model, the following parameters are
taken as a reference, where vs = 230 vrms , Rs = 0.1 Ω, Ls =
100 μH, Cdc = 1000 μf, and Rload = 100 Ω. The model
is simulated using Euler’s method, with an integration time
step of ΔT = 20 μs. Fig. 18 shows the experimental waveforms of the emulator for the single-phase diode rectifier bank
connected between two lines in a delta topology. The figure
shows the unbalanced rectifier load model current references
isa = 17 A, isb = 16.5 A, and isc = 16 A (peak). The phase
currents add up to zero. The lowest trace shows the fourth leg
current in as equal to zero. From the results, it can be observed
that the controller constantly traces the reference currents of
the nonlinear active loads. The tracking performance of the
controller remains the same even during the periods when the
reference remains zero.
VI. E MULATOR T IME A NALYSIS
The emulator digital hardware structure is centered on the
Texas Instruments TMS320VC33 DSP, which has a clock
frequency of 75 MHz. This gives an instruction cycle time of
13.33 ns. The entire load emulation software is driven by an
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 4, APRIL 2010
TABLE II
P ROCESSOR E XECUTION T IME FOR L OAD E MULATION
interrupt service routine (ISR). The main code (background
loop) consists of simply peripheral initialization (timers,
analog-to-digital converter (ADC), interrupt control, and
buffer). The remainder of the code is taken up entirely by
Timer 0 ISR. This ISR is invoked every 20 μs by the period
event flag on Timer 0. Calculation of reference currents from
the model, sampling of ADC, and generation of PWM waveforms for power switches are done within 20 μs.
Table II shows the tasks performed and time taken by each
task. The tasks carried out by DSP–FPGA take 14.8 μs in
total for a time step of 20 μs. Three ADC sample time is
3.5 μs, and LQR current controller execution time is 2.06 μs.
Data conversion and communication between DSP and FPGA
is 640 ns. Motor model using the two-step Adams–Bashforth
integration method execution time is 2.04 μs. Buffer save and
inverter protection task execution time is 2.8 μs. Data transfer
between PC and DSP buffer is offline. The measurements are
taken with the help of external flag XF0 of the DSP.
VII. C ONCLUSION
This paper has discussed load emulation which is capable of
emulating an electrical load in real time with power electronic
converter. This proposed testing approach eliminates the need
of using real loads in the design process and, therefore, greatly
reduces the overall design cost. The state feedback controller
has been designed and implemented in a DSP–FPGA platform
and has been shown to perform satisfactorily in steady-state
and transient conditions. The system was operated to emulate
various electrical load models. Experimental results of control
system and PLL are discussed. The PLL is an additional
feature implemented in DSP using which nonlinear and leading/lagging power factor loads can be emulated.
The most attractive feature of the emulator is that the emulator is shown to mimic the behavior of induction motors and
diode rectifiers. The capacity of the emulator is limited by the
power rating and bandwidth of the system. A minimum realtime step of 20 μs has been achieved using this platform. This
time resolution is sufficient to simulate the dynamic behavior
of most power electronic control systems and electrical load
models.
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SRINIVASA RAO AND CHANDORKAR: ELECTRICAL LOAD EMULATOR USING OPTIMAL FEEDBACK CONTROL
Y. Srinivasa Rao (M’09) was born in Nandigama,
Andhra Pradesh, India, on May 19, 1968. He received the B.E. degree in electronics engineering and
the M.E. degree with specialization in computer engineering from Shivaji University, Kolhapur, India,
in 1990 and 1996, respectively. He is currently working toward the Ph.D. degree in the Department of
Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India.
He is currently an Assistant Professor with the
Sardar Patel Institute of Technology, University of
Mumbai, Mumbai. His current research interests are in the area of rapid prototyping tools for digital power electronics, embedded systems, DSP applications
using VLSI, power converters, and modulation techniques for inverters.
1225
Mukul C. Chandorkar (M’84) received the B.Tech.
degree from the Indian Institute of Technology
Bombay, Mumbai, India, the M.Tech. degree from
the Indian Institute of Technology Madras, Chennai,
India, and the Ph.D. degree from the University
of Wisconsin, Madison, in 1984, 1987, and 1995,
respectively, all in electrical engineering.
He has several years of experience in the power
electronic industry in India, Europe, and the U.S.
In 1996 through 1999, he was with ABB Corporate
Research Ltd., Baden–Daettwil, Switzerland. He is
currently a Professor with the Department of Electrical Engineering, Indian
Institute of Technology Bombay. His technical interests include electric power
quality compensation, drives, and real-time simulation of electrical systems.