TRIGGER DELAY
100µs
Requirements
• The trigger delay is a back
back-up
up system that generates an
asynchronous dump trigger for MKD and MKB in case of
problems with the synchronous
p
y
dump
p trigger.
gg
• Design goals are to make a system that is stand-alone,
simple and reliable.
• Stand–alone means that the system is completely selfcontained. Its function is not affected by any external
condition.
• Simplicity means to minimise number of components for
the critical part of the circuit.
G. Gräwer AB/BT/EC
LBDS Trigger Delay
2
Block diagram
230VAC
3U Eurochassis
Trigger
In
VB
Power
supply B
24VDC
VA
Power
supply A
24VDC
Delay 100µs
Interlock
loop
To 25 retrigger boxes
15 MKD and 10 MKB
Error
Warning
Interlock
Trigger
Out
To PLC
G. Gräwer AB/BT/EC
LBDS Trigger Delay
3
General description
• The trigger delay generates an output pulse 100µs after the
input trigger
• The trigger delay unit has got two internal 24V power
supplies. If one of them fails it continues working with the
g signal
g
is g
generated for the PLC. The
other one and a warning
faulty power supply should be replaced at the next possible
occasion.
• If both power supplies fail or in case of mains failure supply
voltage is maintained by internal capacitors. The unit still
remains operational for several minutes (up to 30min).
• In
I case off a fault
f lt in
i the
th trigger
ti
delay
d l unit
it th
the iinterlock
t l k circuit
i it
generates an error signal for the PLC.
• There are three p
possible faults that can cause an error:
• Input disconnected.
• Output disconnected.
• Low voltage off oscillator capacitor.
G. Gräwer AB/BT/EC
LBDS Trigger Delay
4
G. Gräwer AB/BT/EC
VCAP
LBDS Trigger Delay
BZX55C
C12
220n
C5
47
T1
R6
D24
D7
D4
BZX5
55C15 BZX55C15
D25
D
1k, 1W
5
R5
5V
2µ2, 35
1k2, 1W
ZK
KB T60403D4
4097-X054
1N4151
D16
6
22n
100
D9
100k
k
C8
R4
VB
1k
C16
1N5060
R16
47n
R43
1N5060
R17
7
1N4151
Trigger
gg in
100
0
D15
VT
R15
5
D3
10µ
C3
1N4151
100, 1W
350µ
L1
D5
R1
710n
n
C7
15
27k
1N4151
BYV27-200
C6
R9
D2
2N2324
1N4151
D14
R13
Q1
VA
470
220
32Z
R14
1N4151
68
R12
D1
VT
V
D11
VB
1N4151
D12
R11
24V in
1N415
51 1N4151 1N4151
D13
3
D10
30Z
YELLOW
D8
Trig
gger
Schematic of trigger delay
VA
C1
10m, 40V
1:1:1
Trigger
out
4Z
6Z
8Z
M1
IRFF130
5
Principle of operation
Main circuit
• The trigger delay circuit is completely analogue. The
semiconductors used in the critical part of the circuit are one
thyristor Q1, one MOSFET M1 and several diodes
diodes. The delay
time is determined by one period of an LC oscillator L1 and
C7.
• A trigger pulse at the input triggers Q1. For the first half of the
oscillation the current flows through Q1 until the zero
crossing. For the second half of the oscillation the current
changes direction and flows through the diode D14 while Q1
is turned off. At the end of the oscillation Q1 blocks the
voltage VT. The rising edge of VT turn on M1 and this
generates
t the
th output
t t trigger
ti
pulse.
l
G. Gräwer AB/BT/EC
LBDS Trigger Delay
6
Principle of operation
Interlock circuit
• The Interlock circuit monitors the internal 24V supply
voltages, the voltage VT at Q1 and the interlock loop.
• If one of the supply voltages fails a warning signal is
generated.
• If VT stays
y low for too long,
g, the interlock loop
p is broken or the
input is disconnected an error signal is generated. The cable
from the trigger delay unit to the retrigger boxes contains two
pairs of wires
wires. One for the trigger signal and one for the
interlock loop. At the end of the cable the interlock loop must
be shorted. This is to make sure that the trigger cable is
properly connected.
G. Gräwer AB/BT/EC
LBDS Trigger Delay
7
Waveforms
Oscillator
current
Oscillator
Voltage
Trigger in
Trigger out
VT
G. Gräwer AB/BT/EC
LBDS Trigger Delay
8
Input fault detection
Trigger line with fault detection
+12V
Trigger
Driver
Trigger
Receiver
C1
IN
50
coaxial cable
C2
OUT
IN
47n
OUT
47n
Trigger pulse on
cable with
offset voltage
Voffset
IN
Trigger pulse at
driver output.
Rise time <100ns
OUT
Schmitt trigger monitors
offset voltage.
Error if offset voltage
below threshold.
Time constant
R4, C3 >>time
constant trigger
pulse
The voltage divider R1, R2 generates an offset voltage that is monitored by the schmitt trigger on
the receiver side. If the driver is not working or the cable is broken the offset voltage is low or zero
and an error signal is generated.
G. Gräwer AB/BT/EC
LBDS Trigger Delay
9
Schematic of interlock circuit
G. Gräwer AB/BT/EC
LBDS Trigger Delay
10
Trigger delay PCB
G. Gräwer AB/BT/EC
LBDS Trigger Delay
11