NSERC Undergraduate Student Research Award (USRA) - Summer 2015
Student project on chip design: On-chip Capacitance Measurement
Techniques for Microelectronic Capacitive Sensors
1. Introduction to Research
Microelectronic capacitive-type sensors [1] are becoming commonly used components of
many Systems-on-Chip (SoC). Their function is to detect changes of a capacitance due to
various physical or chemical phenomena being exploited within a sensor/transducer.
Examples include measurement of internal capacitances of semiconductor devices used
as sensors, measurements of 2-D and 3-D parasitic capacitances of interconnects within
integrated circuits, measurements of capacitance change due to incidence of particles or
bubbles on the surface of electrodes of chemical, biochemical and microfluidic sensors,
etc. Some of the capacitance measurement techniques can be substantially miniaturized
[2] allowing for integration of signal processing circuitry with the capacitive sensors, in
effect resulting in large-area arrays of capacitive sensors integrated with read-out
electronics on a single chip. These capacitive sensor arrays find applications in highly
integrated Lab-on-Chip (LoC) systems [3], miniature electrical tomography systems [4],
MEMS inertial sensors, and capacitive fingerprint sensors [5].
Measuring a capacitance change has been done in many ways, depending mostly on
application and the required accuracy. A Charge-Based Capacitance Measurement
(CBCM) [6] has been proposed initially to measure femto- and atto-Farad level parasitic
interconnect capacitances in VLSI chips.
VDD
A
VP
C
VN
The CBCM test circuit (Fig.1) operates in two phases. In
the Phase 1, the n-MOS transistor is off but the p-MOS
transistor is on and it charges the unknown capacitor C
with the current I, which is measured with the ammeter.
In the phase 2, the p-MOS transistor is off but the nMOS transistor is on, discharging the capacitor C. If the
clock voltages VP and VN have a frequency f, then the
capacitance C can be evaluated from the relation:
I = C ⋅VDD ⋅ f
VSS
Figure 1. CBCM basic test circuit [6].
T
VDD
VN
Phase 2
Phase 1
The important feature of the CBCM method is that both n-MOS and p-MOS transistors
must be driven by non-overlapping signals (Fig.2), hence eliminating the possibility of
short circuit current between VDD and VSS.
VDD
VP
T=1/f
VSS
Figure 2. Example of nonoverlapping CBCM signals VN
and VP [6].
VSS
time
The CBCM method can be also used to measure a difference of two capacitances (Fig.3),
allowing practically to eliminate parasitic capacitances of interconnects always present in
integrated circuits, as well as all other capacitances that one does not want to measure.
VDD
I1
I2
I1 = C1 ⋅VDD ⋅ f
I 2 = C2 ⋅VDD ⋅ f
VP
I 2 − I1 = ( C2 − C1 ) ⋅VDD ⋅ f
C1
VN
C2
VSS
Figure 3. The concept of differential CBCM measurement.
Typical data obtained using the CBCM method (Fig.4) display the measured current as a
function of both power supply VDD and signal frequency f. In the submicron CMOS
technologies VDD is rather small, however frequency can be high, potentially alleviating
the problem of accurate measurement of small currents on-chip. In the past, the attempted
solution was to convert current to voltage by using an integrator and either to amplify the
voltage signal [4] or to use ΣΔ readout circuit [3]. New avenues should possibly exploit
current-domain and time- or frequency-domain signal processing, and they will be
attempted in this project.
Figure 4. Example of the test current measured using the CBCM method [6] vs. VDD and
frequency f. Capacitance is extracted from the slope of the straight-line approximation.
2. NSERC USRA Candidate Requirements
The research work in the Summer 2015 project will involve investigating on-chip
metrology for capacitive sensors, starting from the CBCM method outlined above.
Other methods can be added to the project, depending on results and time. The activities
include:
• literature study (25%)
• circuit simulation (50%)
• reporting results (25%)
The project has a potential to contribute to student's Thesis (if the candidate is interested)
and also result in possible publication (depending on results).
The student interested in this project should be familiar with microelectronic circuits,
CMOS technology and CMOS devices, usually being taught in such ENSC courses as
ENSC 325, ENSC 425, ENSC 450, and/or equivalent Directed Studies courses.
Knowledge of CMOS circuit industry-standard simulation software (HSPICE - available
in ESIL on Linux workstations) is an important asset for the project, and candidates with
this experience will be given priority. For the candidates who are familiar with other
versions of SPICE this project may be an opportunity to learn HSPICE.
References
[1] http://en.wikipedia.org/wiki/Capacitive_sensing
[2] http://www.analog.com/library/analogdialogue/archives/40-10/cap_sensors.pdf
[3] E. Ghafar-Zadeh, M.Sawan, "Charge-Based Capacitive Sensor Array for CMOSBased Laboratory-on-Chip Applications", IEEE Sensors J., April 2008, pp.325-332.
[4] I. Evans, T.York, Microelectronic Capacitance Transducer for Particle Detection",
IEEE Sensor J., June 2004, pp. 364-372.
[5] J-W.Lee, D-J Min, W.Kim, "A 600-dpi Capacitive Fingerprint Sensor Chip and
Image-Synthesing Technique", IEEE Solid-State Circuits J., Apr.1999, pp.469-475.
[6] J.C.Chen, B.W.McGaughy, D.Sylvester, C.Hu, "An on-chip, Attofarad Interconnect
Charge-Based Capacitance Measurement (CBCM) Technique", IEDM Tech. Dig.,
1966, pp.3.4.1-3.4.4.