Design and Implementation of a WISHBONEcompatible Low-noise Arbitrary Waveform Generator
with DAC compensation
Cecil Accetti R. de A. Melo1, Ricardo E. de Souza2
1
Centro de Informática, 2 Departamento de Engenharia Biomédica
UFPE – Universidade Federal de Pernambuco
Recife – PE – Brazil
1
caram@cin.ufpe.br
Abstract— This paper presents the design and FPGA
implementation of a WISHBONE Bus compatible arbitrary
waveform generator (AWG) module. Developed for use in
nuclear magnetic resonance (NMR) and other software-defined
radio applications, the AWG core is capable of generating
modulated signals as well as sine/cosine signals, using directdigital synthesis (DDS). Phase dithering is used to reduce spurs
created by phase truncation, and a DAC compensation systolicarray FIR filter extends the effective bandwidth of the AWG up
to 80% of the Nyquist limit. Logic synthesis was targeted to an
Altera Cyclone II device.
Keywords— DDS; SDR; WISHBONE; FPGA;
I.
INTRODUCTION
The design of a stable frequency source is a critical step in
a multitude of applications, from communications to medical
imaging systems, each one with its own requirements.
Therefore, for each application there must be a compromise
between cost, form-factor, power consumption and
performance.
Among the techniques used for frequency synthesis are
phase-locked loops (PLLs) and direct-digital frequency
synthesis (DDFS), also called direct-digital synthesis (DDS).
While PLLs present high spectral purity and very low phase
noise, they are extremely sophisticated [1] and technologydependent designs, and due to their feedback architecture, they
are usually not suitable for frequency-hopping or high-speed
frequency switching applications [2]. DDS-based generators,
on the other hand, are digital structures that translate a digital
frequency tuning word (FTW) into an output signal of desired
frequency, thus being suitable for wideband operations, with
the ease of software programmability.
FPGA-based DDS extend the capabilities of standard offthe-shelf DDS ICs, by the addition of performance enhancing
structures, e.g. programmable high-order digital filters, which
are usually not implemented on those commercial ICs.
In this work, the design of an arbitrary waveform generator
based on DDS is presented. The proposed architecture is
intended for use on small (less than 10k logic cells) FPGAs,
which are comparable in price to commercial DDS ICs with
less capabilities.
This work was supported by the Instituto de Nacional de Ciência e Tecnologia
de Nanotecnologia para Marcadores Integrados (INCT – INAMI), CNPq /
MCT, Brazil
Section II of this paper briefly explains DDS main
concepts and limitations. Section III presents the proposed
architecture, the strategies used in this design to mitigate the
limitations of DDS systems and results obtained from
simulation of the VHDL model. Section IV shows synthesis
and experimental results of the proposed module in a
hardware platform designed for magnetic resonance data
acquisition.
II.
BACKGROUND
Direct-digital synthesis has been widely [1-6] used for
generation of periodic signals by means of a numericallycontrolled oscillator, as illustrated on Fig.1. A NCO typically
consists of two main parts: a phase accumulator and a phaseto-amplitude converter, usually a look-up table ROM storing
part of, or a full period of the desired waveform. The
frequency fout of the output signal is controlled by the
frequency tuning word (FTW) which is the input of the phase
accumulator, and is determined by:
,
(1)
where fS is the sampling frequency of the desired signal, and N
is the phase accumulator width. For practical reasons, due to
the limited amount of memory, the phase accumulator word
should be truncated prior to the phase to amplitude converter.
This stage, known as phase quantization, leads to phase noise
and the introduction of periodical errors which appear in the
signal spectrum as spurs. The spurious-free dynamic range
(SFDR) is the ratio between the strength of the wanted signal
and the strongest spurious signal [5]. Typical wideband SFDR
values in commercial DDS ICs are in the 60dBc to 70dBc
range [1]. Several techniques to spread spurious signals have
been proposed [2-3].
Fig. 1. Conventional NCO architecture
Another limitation of DDS systems is the signal attenuation
inherent of digital-to-analog converters (DACs), due to the
zero-order
hold
effect
[7],
that
introduces
a
sin(πfout/fS)/(πfout/fS), or sinc(πfout/fS), distortion. Fig. 2 depicts
Fig. 2. Frequency response of a sample-and-hold DAC
the frequency response of a DAC, which is the same for all
sample-and-hold DACs.
To compensate for the sinc roll-off, equalization methods
can be employed [7]. These methods are covered in more
detail, alongside other DDS concepts in [6,7].
III.
ARCHITECTURE AND SIMULATION RESULTS
A block diagram of the arbitrary waveform generator is
depicted in Fig. 3. The proposed architecture contains two
numerically-controlled oscillators (NCOs), a digital mixer and
an even-symmetry, minimum-phase finite impulse response
(FIR) inverse-sinc filter DAC compensation. A set of sixteen
16-bit registers is responsible for the module operation, being
accessible via the WISHBONE Bus slave interface. These
registers allow operating mode selection, frequency and phase
control of both NCOs, enabling of DAC compensation filter,
and selection of the modulating signal for amplitude
modulation.
The AWG can be programmed into single-tone or
frequency sweep modes, and offers four independent userdefined operating profiles for frequency, phase and mode
settings. The external pulse input (ExtPulse) can be used to
produce RF pulses, controlled by an external pulse generator.
Fig. 3. Block diagram of the AWG IP-Core
A. Numerically Controlled Oscillators
The two NCOs are the main modules of the AWG core.
NCO1 is responsible for the synthesis of carrier wave signals,
and consists of four major blocks: A frequency accumulator, a
phase accumulator, a phase quantization stage, and a look-up
table. NCO2 structure is analogous to NCO1.
The frequency accumulator is used in the frequency sweep
mode. Its inputs are the 48-bit frequency increment (FI), 32bit increment rate (IR), 48-bit initial frequency (IF) and 48-bit
final frequency (FF) registers. By setting these registers, the
AWG can generate sweep (chirp) signals, which are widely
used in radar and spread-spectrum communication systems.
The phase accumulator and the phase-quantization stage
translate the user-defined frequency-tuning word into a 10-bit
address for the LUT, which stores the signal amplitude for the
respective phase. Exploiting the symmetry of sinusoidal
signals, only a quarter of a period is stored in the LUT. In
order to save memory resources, only 1024 10-bit memory
locations are used, storing sine values from 0 to 90º.
Cosinusoidal signals are recovered from the sine LUT by
applying basic arithmetic operations during reconstruction.
B. Quantization effects and Phase Dithering
To reduce the unwanted spurious components caused by
phase quantization, phase dithering [4] is implemented. By the
addition of a (pseudo) random number to the least significant
bits of the phase accumulator, phase errors are spread in the
spectrum, avoiding the occurrence of spurs. The width of the
pseudo-random word is B = N – P, where N is the phase
accumulator width, and P is the quantized word width. Thus
for N= 48 and P=12, B = 36 bits.
The pseudo-random sequence is generated by a linear
feedback shift register [8] in Fibonacci configuration,
corresponding to the mod-2 polynomial:
(2)
The effects of phase quantization and dithering can be seen
on Figs.4 and 5. Fig.4 shows the output spectrum obtained by
simulation of the VHDL model of the AWG core, using
Modelsim and processing the data obtained by the testbench
on MATLAB, with dithering disabled. In this case, SFDR is
roughly 40dBc, relative to a 10MHz carrier. Fig. 5 shows the
mean square spectrum of the same 10MHz carrier wave, but
with dithering enabled, which results in a much cleaner
spectrum, with a gain in SFDR of approximately 30dBc, if
compared with the previous case.
Fig. 4. Output signal spectrum – dithering disabled
Fig. 5. Output signal spectrum – dithering enabled
C. DAC compensation filter
To eliminate the effect of the sinc roll-off after digital-toanalog conversion and extend the effective bandwidth of the
AWG, a FIR filter with inverse-sinc response was designed.
The impulse response of such filter is symmetrical with an
even number of taps, characteristic that is exploited by the
filter architecture which uses half the number of multipliers
that would be required in a direct-form FIR implementation.
The compensation filter is organized in a systolic array
structure that is modularized in processing elements, as
depicted on Fig.6. A systolic-array structure allows the filter
operation at high clock rates, synchronized with the NCOs and
the DAC, typically at sampling rates of 100 MSPS, or greater.
All processing element operations are defined in 12-bit
fixed-point arithmetic, with ten bits on the fractional part, one
integer bit, and one signal bit for two’s complement
representation.
Since the inverse-sinc filter frequency response is greater
than one, as shown on Fig.7, the dynamic range of the DACcompensated signal is intentionally lower than the one of the
uncompensated signal, to avoid clipping or overflow in the
filter datapath, with the advantage of being flat over the
operating bandwidth. Flattening the DAC response allows for
the simplification of the external circuitry after analog
conversion. For example, instead of having a set of narrowband amplifiers, relays, or switches, a single wide-band
amplifier can be used over the entire AWG bandwidth,
reducing power consumption and saving PCB real-estate, as
well as improving the signal immunity to external noise, with
a smaller signal path.
Fig. 7. Frequency response of the DAC compensation filter – 16th order
inverse-sinc, 0.001% passband ripple – 44MHz passband
D. WISHBONE Bus Interconnect
The WISHBONE SoC Interconnection Architecture is a
free, open-source bus standard maintained by the Opencores
initiative [9], that is increasing in popularity among SoC and
System-on-a-programmable-chip (SOPC) designers. It
improves IP cores portability, by providing a flexible common
interface that results in faster time-to-market and reduces
development costs. WISHBONE defines only standard data
exchange between modules, allowing application-specific
signals to be incorporated in the interface. It supports single
and block transfers as well as read-modify-write cycles. Since
the standard does not specify electrical characteristics, it is
technology-agnostic and vendor-agnostic, being suitable to
implementation in both FPGA and ASIC applications.
IV.
SYNTHESIS AND EXPERIMENTAL RESULTS
Synthesis of the Arbitrary Waveform Generator IP-Core
was targeted to a Cyclone II FPGA [10] device
(EP2C5T144C8), using the Quartus II tool.
The experimental setup includes an Analog Devices
(Analog Devices, Inc. - Norwood, MA) AD9762 12-bit
125MSPS TxDAC - Digital-to-analog converter, assembled
on the home-built NMRHDB platform, shown on Fig. 8.
Synthesis results are presented at Table 1. The entire core
was designed in the VHDL hardware description language.
TABLE I.
SYNTHESIS RESULTS
Device: ALTERA CYCLONE II - EP2C5T144C8
Total logic elements (LEs)
988 / 4,608
Total Registers
724/4,608
Total Memory Bits
20,480 / 119,808
Total 9-bit Hardware Multipliers
20 / 26
FIR Filter multpliers (16-order)
18 / 26
FIR Filter Logic /elements (16-order)
281
RTL Code
1562 lines
Testbench
350 lines
Module count
13
Fig. 6. Structure of the DAC compensation filter, of processing elements in a
systolic-array configuration, for maximum throughput.
FPGA%
21%
16%
17%
77%
69%
-
a)
b)
Fig. 11. Measured wideband (a) and narrowband (b) output spectra, for
20MHz and 42.58MHz, respectively.
Fig. 8. Experimental setup – NMRHDB platform
Fig. 9 shows the output of the system for a 21MHz sinusoidal
carrier modulated by a sinc envelope. This particular
waveform is of great importance for magnetic resonance
imaging (MRI) systems, since it is employed for image slice
selection[11]. Other slice-selective pulse envelopes, such as
Gaussian pulses, can be synthesized by reprogramming the
NCO2 LUT, during run-time. Fig. 10 shows a rectangular
envelope pulse, using the ExtPulse input as the source of the
modulating signal.
Measured wideband and narrowband spectra for 20MHz
and 42.58MHz unmodulated signals are shown on Fig. 11.
SFDR is 63 dBc for the wideband spectrum and 70 dBc for the
narrowband spectrum.
V.
CONCLUSIONS
This paper presented the design and FPGA implementation
of an arbitrary waveform generator based on direct-digital
synthesis, with extended capabilities not usually found on
commercial off-the-shelf DDS ICs. An increase in the
spurious-free dynamic range was obtained by using phase
dithering, and the bandwidth of the signal after digital-toanalog conversion was extended by the use of a DACcompensating filter.
The module was designed to communicate with a bus
master using the open-source WISHBONE Bus standard,
which allows its integration in complex SOC/SOPC
architectures.
This AWG can be used as an alternative to traditional DDS
solutions, as it can help to reduce costs and PCB real-estate, in
a wide range of applications of software-defined radio and
medical imaging systems.
REFERENCES
[1]
Fig. 9. Amplitude-modulated “soft” pulse for MRI. Sinc function with 9
sidelobes
Fig. 10. Amplitude-modulated “hard” pulse for NMR/MRI.
Cronin, B. DDS Devices Generate High Quality Waveforms Simply,
Efficiently and Flexibly, Analog Dialogue 46-01, January 2012 –
http://www.analog.com/analogdialogue
[2] Direct digital synthesis-based all-digital phase-locked loop
Vezant,
B. ; Mansuy,
C. ; Hung
Tien
Bui ; Boyer,
F.-R.
Circuits and Systems and TAISA Conference, 2009. NEWCAS-TAISA
'09. Joint IEEE North-East Workshop on
[3] Cordesses, L. Direct digital synthesis: a tool for periodic wave
generation- part1, IEEE Signal Processing Magazine vol 21 issue 4,pp
50-54, 2004
[4] Cordesses, L. Direct digital synthesis: a tool for periodic wave
generation- part 2, IEEE Signal Processing Magazine vol 21 issue 5,pp
110-112 ,2004
[5] O’Leary,P. ; Maloberti, F. A direct-digital synthesizer with improved
spectral performance. IEEE Transactions on Communications, Vol. 39,
Issue 7, 1991
[6] Buchanan, D. Choosing DACs for Direct Digital Synthesis, Application
note AN-237, Analog Devices Inc., Norwood MA,USA.
[7] Yang. K. Flatten DAC frequency response, EDN magazine, pp 65-74,
April 2006
[8] Texas
Instruments,
What’s
an
LFSR?,
Dec.
1996,
http://www.ti.com/lit/an/scta036a/scta036a.pdf
[9] OpenCores – http://opencores.org/opencores,wishbone
[10] Cyclone II Device Handbook vol. 1, San Jose, CA: Altera Corp.2008
[11] Liang, Z. ; Lauterbur,P.C; Principles of Magnetic Resonance Imaging ,
IEEE press, 2000